Cross-point Memory Research Articles

A novel approach to enhancing performance and endurance in GeS2 OTS devices using amorphous carbon doped W2N electrodes

Three–dimensional (3D) cross-point (X–point) memory has gathered interest for its fast data processing and high density, achieved by stacking memory with a selector device to prevent misinterpretation. Ovonic threshold switching (OTS) is a promising selector due to its reversible switching behavior. Although, OTS devices typically employ transition metal nitrides (TMN) such as TiNx, TaNx, and WNx for electrodes owing to their good stability, high melting points, and low resistivity, TMNs can diffuse and degrade device performance by recrystallizing with chalcogenide alloys. Amorphous carbon (a–C) can be a good alternative electrode material due to its low roughness, cost–effectiveness, high work function (WF), and excellent thermal stability. However, the high resistivity of a–C (∼ 150 mΩ–cm) increases threshold voltage (Vth), causing high power consumption. Therefore, combining both a–C and TMN materials can effectively obtain their advantages. This study explores the effect of varying a–C content in W2N electrodes on GeS2–based OTS selectors. The (W2N)1-xCx (0 ≤ x ≤ 0.25) electrodes were deposited using DC magnetron co–sputtering. The phase of (W2N)1-xCx (0 ≤ x ≤ 0.25) films transformed from polycrystalline to amorphous with increasing x. Devices with (W2N)1-xCx/GeS2/W2N structure showed decreased Vth and off current, improving from 4.8 to 3.8 V and 8.0–4.17 nA, respectively. The subthreshold slope, distance between traps, and interface trap density (Nit) were extracted using the Pool–Frenkel model. The reduced Vth may be attributed to a higher WF and lower Nit with increasing x. The device’s lifetime improved up to 1.0 × 109 pulses for the highest a–C content in (W2N)1-xCx (0 ≤ x ≤ 0.25) electrodes.

CMOS-compatible Hf0.5Zr0.5O2-based ferroelectric memory crosspoints fabricated with damascene process

We report the fabrication of Hf0.5Zr0.5O2 (HZO) based ferroelectric memory crosspoints using a complementary metal-oxide-semiconductor-compatible damascene process. In this work, we compared 12 and 56 µm2 crosspoint devices with the 0.02 mm2 round devices commonly used as a benchmark. For all devices, a 9 nm thick ferroelectric thin film was deposited by plasma-enhanced atomic layer deposition on planarized bottom electrodes. The wake-up appeared to be longer for the crosspoint memories compared to 0.02 mm2 benchmark, while all the devices reached a 2Pr value of ∼50 µC cm−2 after 105 cycles with 3 V/10 µs squared pulses. The crosspoints stand out for their superior endurance, which was increased by an order of magnitude. Nucleation limited switching experiments were performed, revealing a switching time <170 ns for our 12 and 56 µm2 devices, while it remained in the µs range for the larger round devices. The downscaled devices demonstrate notable advantages with a rise in endurance and switching speed.

Modeling defect-level switching for nonlinear and hysteretic electronic devices

Previously, we demonstrated hysteretic and persistent changes of resistivity in two-terminal electronic devices based on charge trapping and detrapping at immobile metastable defects [Yin et al., Phys. Rev. Appl. 15, 014014 (2021)]; we termed these defect-level switching (DLS) devices. DLS devices feature all-electronic resistive switching and thus are volatile because of the “voltage-time” dilemma. However, the dynamics of volatile resistive switches may be valuable for emerging applications such as selectors in crosspoint memory and neuromorphic computing concepts. To design circuits using these volatile resistive switches, accurate modeling is essential. In this work, we develop an accurate and analytical model to describe the switching in DLS devices, based on the established theories of point defect metastability in Cu(In,Ga)Se2 (CIGS) and II–VI semiconductors. The analytical nature of our model allows for time-efficient simulations of dynamical behavior of DLS devices. We model the time durations of SET and RESET programming pulses, which can be exponentially shortened with respect to the pulse amplitude. We also demonstrate the concept of inverse design: given desired resistance states, the width and amplitude of the programming signal can be chosen accordingly.

Ultrafast and thermally stable ternary Ge0.33SexSy ovonic threshold switching selector using magnetron sputtering

3D cross–point memory, with its cost efficiency and simple structure, has gained attention and commercial success. In this memory architecture, chalcogenide–based ovonic threshold (OTS) selectors are promising due to their fast, volatile, and reliable transition without altering their amorphous structure. GeS–based OTs selectors have recently emerged as potential candidates due to their thermal stability and high Ion. However, Ge1−xSx selectors suffer from slow switching times (ton of 10 – 15 ns and toff of 20 – 100 ns), hindering fast data processing. To address this, synthesizing Ge1−xSex into Ge1−xSx is proposed as an effective method, as it reduces the activation energy (Ea) of Ge0.33SexSy, resulting in shorter ton. This study presents a thermally stable and ultrafast OTS selector based on Ge0.33SexSy (0.22 ≤ x ≤ 0.55) films. There films remain amorphous after annealing at 600 °C. the device with the highest Se composition (x = 0.55) exhibits a short ton of 6 ns and toff of 13 ns. Ge0.33SexSy devices show varying Vth (3.6 to 2.8 V) as the Se/S ratio increases, along with low Ioff (up to 1.2 nA). Further analysis using a modified Pool–Frenekl model reveals crucial parameters, and optical properties changes as the Se/S ratio increases. This ultrafast and thermally stable OTS selector promises outstanding performance for X–point memory architecture.

Thermal atomic layer deposition of ternary Ge-S-Se alloy for advanced ovonic threshold switch selectors in three-dimensional cross-point memory array

Two-terminal ovonic threshold switch (OTS) selectors based on chalcogenide alloys have attracted significant attention as alternatives to conventional silicon-based transistors. These selectors offer outstanding features that enable the mass production of three-dimensional cross-point arrays for advanced memory technologies. In this study, we developed a thermal atomic layer deposition (ALD) process for ternary Ge-S-Se alloys. By utilizing ALD super-cycles of Ge-Se and Ge-S, a broad range of film compositions can be achieved. We investigated the electrical characteristics and film properties of the deposited films, with a focus on their smooth surfaces and excellent conformality, which are indispensable characteristics for future vertical cross-point structures. By incorporating S into the Ge-Se film via an ALD super-cycle, we achieved a significant reduction in off-current of Ge0.50S0.15Se0.35 to approximately 35 nA. Additionally, the thermal stability of Ge0.50S0.15Se0.35 film is enhanced up to 420 ℃ due to the higher bandgap and shorter bonding length of S, exhibiting a cyclic endurance of more than 5 × 107. This research not only provides insight into the control of the film composition to improve and modify device characteristics but also constructs a foundation of ALD-based OTS research on ternary Ge-S-Se for a future X-point memory application.

Thermally stable threshold selector based on CuAg alloy for energy-efficient memory and neuromorphic computing applications

As a promising candidate for high-density data storage and neuromorphic computing, cross-point memory arrays provide a platform to overcome the von Neumann bottleneck and accelerate neural network computation. In order to suppress the sneak-path current problem that limits their scalability and read accuracy, a two-terminal selector can be integrated at each cross-point to form the one-selector-one-memristor (1S1R) stack. In this work, we demonstrate a CuAg alloy-based, thermally stable and electroforming-free selector device with tunable threshold voltage and over 7 orders of magnitude ON/OFF ratio. A vertically stacked 64 × 64 1S1R cross-point array is further implemented by integrating the selector with SiO2-based memristors. The 1S1R devices exhibit extremely low leakage currents and proper switching characteristics, which are suitable for both storage class memory and synaptic weight storage. Finally, a selector-based leaky integrate-and-fire neuron is designed and experimentally implemented, which expands the application prospect of CuAg alloy selectors from synapses to neurons.

High-Density Nanopatterning of SiGeAsTe Chalcogenide as Ovonic Threshold Switch Selectors for Memory Applications

Cross-point memory architecture involves high-density, fast yet cost-effective storage class memories (SCM). As a result, ovonic threshold switches (OTS) are extensively researched as they are needed in series with the SCM-based memory element for its precise functioning. In addition, these OTS-based devices exhibit the potential to be self-selecting memories too. Hence, its integration-friendly patterning becomes pivotal for large-scale manufacturing. Chalcogenide-based alloys are often the desired candidate for OTS. Here, we study the patterning of one of the widely investigated chalcogenide alloys─SiGeAsTe. While the elements of the alloy generate highly volatile halogenated etch by-products, this material is also prone to severe etch-induced lateral undercuts and material damage. Thus, its high-density patterning is challenging. A conventional method to minimize this undercut damage is to increase the hydrocarbon passivation during the etch process to prevent the exposure of the chalcogenide’s sidewalls (SWs) to any type of etchant. Inherently, this leads to the tapering of the OTS-based pillars, consequently becoming an impediment to their scaling at tighter pitches. Here, we clearly establish that OTS-based devices with well-preserved chemical and morphological properties can be fabricated using lower hydrocarbon passivation by tuning the ion energies during etching. Higher ion energies ensure better etch directionality. Concurrently, a well-controlled high energy ion bombardment is likely to enhance deposition of the passivating hydrocarbon from the etch front on to the chalcogenide’s SWs. This is achieved without any unwanted redeposition from underlying layers in the OTS-based stack. We successfully demonstrate high-density nanopatterning of chalcogenide-based OTS devices of diameter ∼65 nm at 200 nm wide pitch. This is also effectively reproduced on 300 mm semiconductor wafers. The electrically measured devices exhibit low leakage and high endurance. This distinctive yet uncomplicated etch tailoring is also discussed to be scalable for pitches <200 nm and for other chalcogenide compositions.

Improving the GeAsSe Ovonic Threshold Switching Characteristics by Carbon Buffer Layers for Ultralow Leakage Current (∼0.4 nA) and Low Drift Characteristics

Volatile Ovonic threshold switching (OTS) selectors have been regarded as the critical component of highly integrated three-dimensional (3D) cross-point array nonvolatile memory systems. However, relatively high leakage current hinders the further reduction of power consumption in the crossbar array. In addition, the threshold voltage drift phenomenon hinders the improvement of device reliability. Utilizing the buffer layer can effectively reduce the interaction between electrodes and the active layer in the cross-point architecture. Here, it manifests that leakage current can be reduced to ∼0.4 nA with a 5 nm thick amorphous carbon layer as a buffer layer in the GeAsSe-based OTS device, where the carbon layer stabilizes the composition of GeAsSe during the electrical switching cycles. It is also found that the carbon layer leads to a lower threshold voltage drift (35.6 mv/dec) and excellent endurance (>109 cycles with ∼0.4 nA ON-state current). The conduction mechanism analysis demonstrates that the inhibition of the carbon layer on drift originates from the high barrier height from delocalized states transformed into localized states. This work clearly demonstrates the role of the carbon layer and facilitates future 3D crossbar-storage technology applications.

Controllable coexistence of threshold and non-volatile crosspoint memory for highly linear synaptic device applications

A highly reliable and versatile resistive memory device that demonstrates threshold and non-volatile memory (NVM) switching behaviour depending on the compliance current (CC) modulation was utilised by doping a semiconducting (Si) material into a high-k (HfO x ) film with highly linear synaptic behaviour. The device shifted towards volatile switching at a CC less than 1 µA and exhibited NVM behaviour at a CC limit above 10 µA. A 3-bit/cell data storage capability on RESET voltage modulation was implemented for high-density memory application. The device exhibited excellent programming linearity of potentiation/depression responses up to 10 000 pulses compatible with fast pulse (100 ns) with good I ON/I OFF ratio (>103), stable data retention capability (105 s) at 85 °C and high WRITE endurance (∼107 cycles) with a pulse width of 200 ns. The neuromorphic applications were successfully emulated through neural network simulations using the experimentally calibrated data of the Si-doped HfO x resistive cross-point devices. Simulation results revealed a low nonlinearity of 0.03 with 98.08% pattern recognition accuracy. The estimated results revealed the potential of the device as a low-power selector and high-density NVM storage in large-scale crossbar array in future neuromorphic computing applications.

Amorphous Ge-Se-S chalcogenide alloys via post plasma sulfurization of atomic layer deposition GeSe for ovonic threshold switch applications

For the future scaling of 3D cross-point (X-point) memory, it is necessary to implement atomic layer deposition (ALD) of chalcogenides for ovonic threshold switch (OTS) applications. We investigated ternary Ge-Se-S amorphous chalcogenide alloys based on ALD process, motivated by the expectation of low off-current and stable OTS behavior by partially replacing S in binary Ge-Se. Ge-Se-S alloys were synthesized by post-deposition sulfurization of ALD GeSe2 thin films. Especially, we investigated the growth characteristics and film properties of ALD GeSe2 using HGeCl3 precursors with Se(SiMe3)2 together with density-functional theory (DFT) calculations. By changing the temperature and the low-temperature plasma sulfurization time, the compositions of 10-nm-thick Ge-Se-S thin films were controlled along the GeSe2-Ge2S pseudo-binary line in ternary phase diagram. It was confirmed that the Ge5Se3S2 alloys maintained an amorphous phase and excellent step coverage, similar to ALD GeSe2. Finally, we compared the OTS electrical characteristics of 10-nm-thick ALD GeSe2 with Ge5Se3S2 amorphous chalcogenide thin films in a mushroom-type device with a 50-nm bottom electrode. The novel Ge5Se3S2 had a slightly larger threshold voltage (Vth) drift than GeSe2 but exhibited the advantages of a higher threshold field, lower off-current, and smaller Vth fluctuation up to 106 cycles. Data availabilityThe data that has been used is confidential.

A Fast-Transient-Response NMOS LDO with Wide Load-Capacitance Range for Cross-Point Memory

In this paper, a fast-transient-response NMOS low-dropout regulator (LDO) with a wide load-capacitance range was presented to provide a V/2 read bias for cross-point memory. To utilize the large dropout voltage in the V/2 bias scheme, a fast loop consisting of NMOS and flipped voltage amplifier (FVA) topology was adopted with a fast transient response. This design is suitable to provide a V/2 read bias with 3.3 V input voltage and 1.65 V output voltage for different cross-point memories. The FVA-based LDO designed in the 110 nm CMOS process remained stable under a wide range of load capacitances from 0 to 10 nF and equivalent series resistance (ESR) conditions. At the capacitor-less condition, it exhibited a unity-gain bandwidth (UGB) of approximately 400 MHz at full load. For load current changes from 0 to 10 mA within an edge time of 10 ps, the simulated undershoot and settling time were only 144 mV and 50 ns, respectively. The regulator consumed 70 µA quiescent current and achieved a remarkable figure-of-merit (FOM) of 1.01 mV. At the ESR condition of a 1 µF off-chip capacitor, the simulated quiescent current, on-chip capacitor consumption, and current efficiency at full load were 8.5 µA, 2 pF, and 99.992%, respectively. The undershoot voltage was 20 mV with 800 ns settling time for a load step from 0 to 100 mA within the 10 ps edge time.

Space-Time-Efficient Modeling of Large-Scale 3-D Cross-Point Memory Arrays by Operation Adaption and Network Compaction

Three-dimensional (3-D) integrated cross-point memory arrays can be used to build high-density storage-class memory systems. However, the coupled network topology caused by sharing word lines or bit lines between adjacent memory layers significantly enlarges the memory space overhead and time cost of memory operation simulations on mega-scale 3-D cross-point memory arrays. We observe that different components of the 3-D cross-point array have different contribution significance to the key metrics of write or read operations, and the distribution patterns of principal components in the arrays are different for write and read operations. We propose an operation-adaptive array modeling framework that exploits the impact of the applied operation on the distribution of array principal components for 3-D cross-point memory arrays. Based on the modeling framework, we propose two array network compaction methods for efficient write and read operation simulations on 3-D cross-point arrays, respectively: 1) pruning zero-biased unselected cells and 2) group-merging neighboring half-selected cells with a specific granularity. Also, serially connected line segments are merged, and floating segments are deleted. Evaluations show that the proposed methods significantly reduce the memory space overhead and time cost of memory operation simulations for various layer sizes and different cell-level access parallelism in an array. Besides, the proposed methods can efficiently simulate memory operations on multilayered 3-D cross-point memory arrays with up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4096\times 4096$ </tex-math></inline-formula> layer size under the 16-GB memory space constraint, achieving a 64-times improvement in layer size that can be simulated compared with the conventional complete 3-D cross-point array network model.

Reliable Low Voltage Selector Device Technology Based on Robust SiNGeCTe Arsenic-Free Chalcogenide

Modern data-centric computing applications are increasingly demanding in terms of memory density and performance. The cross-point memory architecture based on the two-terminal one-selector/one-resistor memory cell is an attractive solution for high-density and 3D-compatible embedded memory. In this letter, we introduce a new arsenic-free chalcogenide material, namely SiNGeCTe, for low voltage selector applications, and we report on its remarkable reliability characteristics. The inclusion of the Si dopant allows for an enhanced material robustness in terms of stable high current operation and extended thermal stability (≥450°C, 30 min), and reduces the First Fire impact on the subthreshold conduction. We investigate the threshold voltage drift and reveal a marked trend of the drift slope with the thickness of the chalcogenide layer. Finally, based on the reported drift trend, the optimized device with 5 nm thickness is highlighted for low threshold voltage and low drift applications, demonstrating low threshold voltage drift with slope <30 mV/dec. The optimized device proves an excellent cycling endurance ≥1e10 cycles.

High uniformity and stability of 1S1R directly stacked for high-density cross-point memory applications

High uniformity and stability of 1S1R directly stacked for high-density cross-point memory applications

A combinatorial study of SiGeAsTe thin films for application as an Ovonic threshold switch selector

In this paper, we investigate the thermal stability of a wide range of ternary and quaternary (Si)GeAsTe alloy thin films. These type of materials are reported to show Ovonic threshold switching, which means they conduct the current above a specific threshold voltage and are not conducting at lower voltages, making them ideal as a selector element for crosspoint memory devices. For threshold switching to occur in these chalcogenides, the amorphous state of the material is crucial, and hence the material may not crystallize below 400°C to be compatible with temperatures used in device process flows. A combinatorial deposition technique is used to create a thin film library of 36 different compositions, and in situ X-ray diffraction and X-ray fluorescence spectroscopy is used to investigate the thermal stability of the films. We show that Si doping of GeAsTe improves the thermal stability by increasing the crystallization temperature and small amounts of Si (i.e.5at%) decreases the tendency to lose material by sublimation. Also capping the films with a W cap avoids material loss if the capping layer does not show cracking under annealing. An optimal chalcogenide composition, being As50Te20Ge20Si10 combined with a W electrode is identified and is integrated in 65nm mushroom type devices for electrical characterization. The material shows threshold switching and excellent endurance with over 108 cycles.

A Sneak Current Compensation Scheme With Offset Cancellation Sensing Circuit for ReRAM-Based Cross-Point Memory Array

A sneak current compensation scheme with offset cancellation sensing circuit (SCC-OCSC) adopting dummy bitline and wordline is proposed to resolve sneak current problem in the cross-point memory array. The sneak current degrades sensing yield because it disturbs read operation for high resistance cell, especially, by contaminating read current. Since the sneak current increases proportionally to the array size, the array size is limited to achieve the target sensing yield, which makes it hard to implement high density memory. The proposed SCC-OCSC cancels-out the sneak current through two phases. In first phase, the sneak current is sampled by connecting dummy BL or WL to the sensing circuit. In the second phase, the sneak current is compensated by subtracting the current sampled in the first phase. Furthermore, sensing yield is enhanced by applying the offset cancellation technique, sharing the same sensing circuit in the two phases. The proposed SCC-OCSCs with dummy BL and WL effectively improve read margin with generally used biasing schemes, floating and half-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> schemes, respectively. In Monte-carlo simulation including post-layout sensing circuit with 65nm CMOS technology, it is verified that sensing yield is significantly improved. Thus, the array size assigned to single sensing circuit is extended up to 8-times with SCC-OCSC, leading 88% area reduction with reduced number of required sensing circuit. Performance is improved as 66% and 25% while power consumption is improved as 47% and 37%, by SCC-OCSC with dummy BL in floating scheme and SCC-OCSC with dummy WL in half-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> scheme, respectively.

Enhanced Switching Characteristics of an Ovonic Threshold Switching Device With an Ultra-Thin MgO Interfacial Layer

In this study, the effect of a MgO interfacial layer on the electrical characteristics of an ovonic threshold switching (OTS) device was investigated. Compared to the control OTS device, the device with the MgO interfacial layer showed excellent switching uniformity and ultralow off-state leakage current (<inline-formula> <tex-math notation="LaTeX">$\sim 440$ </tex-math></inline-formula>pA) without noticeable changes in the electrical forming process. By extracting the activation energy before and after the forming process, we confirmed that the enhanced switching characteristics were obtained by reducing the interaction between the OTS film and electrodes. Furthermore, the 1S-1R operation with TaO_x-based resistive random access memory (ReRAM) showed successful suppression of the leakage current, which is suitable for a cross-point memory array application.

Fenton Reaction for Enhancing Polishing Rate and Protonated Amine Functional Group Polymer for Inhibiting Corrosion in Ge1Sb4Te5 Film Surface Chemical-Mechanical-Planarization

A Fenton reaction and a corrosion inhibition strategy were designed for enhancing the polishing rate and achieving a corrosion-free Ge1Sb4Te5 film surface during chemical-mechanical planarization (CMP) of three-dimensional (3D) cross-point phase-change random-access memory (PCRAM) cells and 3D cross-point synaptic arrays. The Fenton reaction was conducted with 1,3-propylenediamine tetraacetic acid, ferric ammonium salt (PDTA–Fe) and H2O2. The chemical oxidation degree of GeO2, Sb2O3, and TeO2 evidently increased with the PDTA–Fe concentration in the CMP slurry, such that the polishing rate of the Ge1Sb4Te5 film surface linearly increased with the PDTA–Fe concentration. The addition of a corrosion inhibitor having protonated amine functional groups in the CMP slurry remarkably suppressed the corrosion degree of the Ge1Sb4Te5 film surface after CMP; i.e., the corrosion current of the Ge1Sb4Te5 film surface linearly decreased as the corrosion inhibitor concentration increased. Thus, the proposed Fenton reaction and corrosion inhibitor in the Ge1Sb4Te5 film surface CMP slurry could achieve an almost recess-free Ge1Sb4Te5 film surface of the confined-PCRAM cells, having an aspect ratio of 60-nm-height to 4-nm-diameter after CMP.

An Optimum Structure of Scalable Capacitors in 3D Crosspoint Memory Technology

Memory chips need large capacitors in their periphery to drive boosted word-lines and bit-lines for read and write operations. In a previous work, scalable capacitors were proposed for 3D crosspoint memory to keep the area for the capacitors constant over technology generations. This paper proposes the capacitance models of three types of wiring capacitors: (1) vertical capacitor, (2) vertical and horizontal capacitor with next-neighbor wires connected with the other terminal, and (3) vertical and horizontal capacitor with next-neighbor pairs connected with the other terminal. These models are based on Wong’s crossover capacitor model to determine the capacitor structure with the highest capacitance density in 3D crosspoint memory technology. One can determine the best structure through optimizing the process parameters such as the height H of the insulation material between the metal wires and the thickness T of the metal wires and the design rules such as the width W and space S of metal wires. The model accuracy was in good agreement with the measurement of twelve types of capacitor structures fabricated in a 180 nm 6 metal standard CMOS process with the maximum error of 20%. Contour plots of the capacitance density across H vs. S where it is assumed that W = T = S are shown. As a result, the boundary condition regarding H and S is determined per 3D crosspoint memory technology with three, four, or five levels of wires.

Effect of TiN Liner Thickness on the Electrical Characteristics and Reliability of CuGeS2/GeS2-Based Selector Device

Three-dimensional (3D) cross-point memory technology has attracted much attention for the future ultrahigh-density memory applications [1]. However, when the resistor (1R) without the selector device is applied to the 3D crosspoint memory cell, the power consumption is extrememly high due to the leakage current, which is a major obstacle in large-scale memory operation. To supress the leakage current, it has been proposed that a selector (1S) is stacked vertically with a resistor (1R). The selector device should have ultralow leakage current and high selectivity to avoid any undesired operation of the unselected memory cells. Among the various selector devices, mixed-ionic-electronic-conduction (MIEC) type selector has been intensively researched as it showed abrupt resisitive switching through the formation and rupture of the metal filaments, resulting in high selectivity (~ 104) and low leakage current (~ 10 pA) [2]. However, the selector device using metal filaments suffer from reliability issues such as endurance failure due to the accumulation of excessive amounts of metal ions in the switching layer [3]. Therefore, it is important to find an efficient solution that improves selectivity and endurance characteristics by controlling the diffusion of excessive amounts of metal ions.In this work, we demonstrated the selector device adopting TiN liner as a diffusion barrier to control the diffusion of Cu into the switching layer. The effects of the TiN liner thickness on the reliability and electrical chacateristics (i.e. Vth, Vh, selectivity) of the GeS2-based selector device were investigated in detail. The schematic image of a selector device without a TiN liner, with a 1-nm-thick TiN liner, and with a 2-nm-thick TiN liner were demonstrated, as shown in Fig. 1(a-c). The GeS2 based selector device has a structure of the plug-type bottom W electrode, 5-nm-thick GeS2 switching layer, 0 to 2 nm-thick TiN liner, 5-nm-thick CuGeS2 ion supply layer, and 50-nm-thick Pt top electrode. A typical DC I-V curve of GeS2 based selector device without a TiN liner exhibited a threshold voltage (V th) of ~ 0.60 V, a holding voltage (V h) of ~ 0.00 V, and a selectivity of ~ 4.59 × 105, as shown in Fig. 1(d). Moreover, a typical DC I-V curve of GeS2 based selector device with a 1-nm-thick TiN liner exhibited a threshold voltage (V th) of ~ 0.75 V, a holding voltage (V h) of ~ 0.15 V, and a selectivity of ~ 1.14 × 106, as shown in Fig. 1(e). Lastly, a typical DC I-V curve of GeS2 based selector device with a 2-nm-thick TiN liner exhibited a threshold voltage (V th) of ~ 1.00 V, a holding voltage (V h) of ~ 0.25 V, and a selectivity of ~ 3.10 × 106, as shown in Fig. 1(f). These results indicated that the threshold voltage (V th), the holding voltage (V h), and the selectivity increased as the thickness of the TiN liner increased. Afterwards, the dependence of the endurance characteristics according to the thickness of the TiN liner of the selector device was evaluated. GeS2 based selector device without a TiN liner demonstrated endurance cycles of ~ 5 × 105, as shown in Fig. 1 (g). Moreover, the endurance characteristic of GeS2 based selector device with 1-nm-thick TiN liner demonstrated endurance cycles of ~ 5 × 106, as shown in Fig. 1 (h). Lastly, the endurance characteristic of GeS2 based selector device with 2-nm-thick TiN liner demonstrated endurance cycles of ~ 1 × 106, as shown in Fig. 1 (i). This result suggested that the optimal liner thickness for the diffusion of an adequate amount of Cu is important to achieve electrically reliable switching characteristics. In the presentation, the effects of TiN liner thickness on Cu diffusion will be assessed in detail using transmission electron microscopy (TEM), energy dispersive spectroscopy (EDS) elemental mapping, and line profile. Reference [1] Geoffrey W. Burr. et al. J. Vac. Sci. Technol. B 32, 040802 (2014)[2] K. Virwani et al., IEDM Tech. Dig. 2012, 2.7.[3] Song, J. et al. IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 11, 2017 Acknowledgement This research was supported by the MOTIE (Ministry of Trade, Industry & Energy (10068055) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Figure 1