Cross-point Array Research Articles

Monarch: A Durable Polymorphic Memory for Data Intensive Applications

3D die stacking has often been proposed to build large-scale DRAM-based caches. Unfortunately, the power and performance overheads of DRAM limit the efficiency of high-bandwidth memories. Also, DRAM is facing serious scalability challenges that make alternative technologies more appealing. This paper examines Monarch, a resistive 3D stacked memory based on a novel reconfigurable crosspoint array called XAM. The XAM array is capable of switching between random access and content-addressable modes, which enables Monarch (i) to better utilize the in-package bandwidth and (ii) to satisfy both the random access memory and associative search requirements of various applications. Moreover, the Monarch controller ensures a given target lifetime for the resistive stack. Our simulation results on a set of parallel memory-intensive applications indicate that Monarch outperforms an ideal DRAM caching by <inline-formula><tex-math notation="LaTeX">$1.21\times$</tex-math></inline-formula> on average. For in-memory hash table and string matching workloads, Monarch improves performance up to <inline-formula><tex-math notation="LaTeX">$12\times$</tex-math></inline-formula> over the conventional high bandwidth memories.

Read Disturbance in Cross-Point Phase-Change Memory Arrays—Part II: Array Simulations Considering External Currents

In Part I of this study, we demonstrated that when a high-read current from phase-change memory (PCM) programmed at a high-SET current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {SET}}{)}$ </tex-math></inline-formula> is achieved, melting dynamics in the chalcogenide layer are promoted, thus leading to read disturbances. Therefore, we analyzed additional external current sources that worsened the read disturbances by considering the PCM cell and additional selector and core circuits used in practical applications. By means of HSPICE simulations, the impact of two noticeable external overshoot and inrush currents generated during respective SET and read operations in one-selector and one-PCM (1S-1R) array was investigated. Our findings show that resistance-related components mainly affect the magnitude of the inflowing external current to the 1S-1R cell. The PCM can thus be easily heated up by the current, making the memory state vulnerable to the melting process. For these reasons, we showed that the disturbance primarily observed in the high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {SET}}$ </tex-math></inline-formula> operated PCM can also occur even at low- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {SET}}$ </tex-math></inline-formula> settings, given the actual cross-point array environment. Finally, we explored the maximum achievable array size that ensures disturbance-free read endurance by quantifying the read current to examine the location wherein the melting occurs.

Convolutional kernel with PrCaMnOx-based resistive random-access memory for neuromorphic image processing

This paper investigated the conductance-state stability of TiN/PrCaMnOx (PCMO)-based resistive random-access memory (RRAM), which serves as a kernel weight element in convolutional neural networks (CNNs), to realize accurate feature extraction from images. On application of the initial forming process that actively drives more oxygen ions to form an interfacial layer between TiN and PCMO to RRAM devices with a high voltage of ±4 V, resistive switching behavior with a noticeable memory window was observed. However, the achieved conductance states continued to decrease during repeated cycling. The oxidation at the interface tended to occur thermodynamically, implying an increase in interfacial layer thickness. Considering the hardware implementation of the kernel weight matrix, with specifically assigned conductance values of the RRAM, state instability in the RRAM renders image edge detection difficult, eventually degrading the overall recognition accuracy of the CNN. Thus, we introduced an asymmetric programming voltage method, wherein a higher set voltage of −3 V than a reset voltage of +2.5 V can shift more oxygen ions back into PCMO. Consequently, when the RRAM devices programmed to different states were maintained without degradation in the 1 K cross-point array, eight clearly distinct weighted sum currents were demonstrated in the 3 × 1 subarray. Based on the measurement results, we performed feature extraction in CNN algorithms through MATLAB simulation, demonstrating input image edge detection with a high accuracy of 92%.

Analysis of electro-chemical RAM synaptic array for energy-efficient weight update

While electro-chemical RAM (ECRAM)-based cross-point synaptic arrays are considered to be promising candidates for energy-efficient neural network computational hardware, array-level analyses to achieve energy-efficient update operations have not yet been performed. In this work, we fabricated CuOx/HfOx/WOx ECRAM arrays and demonstrated linear and symmetrical weight update capabilities in both fully parallel and sequential update operations. Based on the experimental measurements, we showed that the source-drain leakage current (ISD) through the unselected ECRAM cells and resultant energy consumption—which had been neglected thus far—contributed a large portion to the total update energy. We showed that both device engineering to reduce ISD and the selection of an update scheme—for example, column-by-column—that avoided ISD intervention via unselected cells were key to enable energy-efficient neuromorphic computing.

Space-Time-Efficient Modeling of Large-Scale 3-D Cross-Point Memory Arrays by Operation Adaption and Network Compaction

Three-dimensional (3-D) integrated cross-point memory arrays can be used to build high-density storage-class memory systems. However, the coupled network topology caused by sharing word lines or bit lines between adjacent memory layers significantly enlarges the memory space overhead and time cost of memory operation simulations on mega-scale 3-D cross-point memory arrays. We observe that different components of the 3-D cross-point array have different contribution significance to the key metrics of write or read operations, and the distribution patterns of principal components in the arrays are different for write and read operations. We propose an operation-adaptive array modeling framework that exploits the impact of the applied operation on the distribution of array principal components for 3-D cross-point memory arrays. Based on the modeling framework, we propose two array network compaction methods for efficient write and read operation simulations on 3-D cross-point arrays, respectively: 1) pruning zero-biased unselected cells and 2) group-merging neighboring half-selected cells with a specific granularity. Also, serially connected line segments are merged, and floating segments are deleted. Evaluations show that the proposed methods significantly reduce the memory space overhead and time cost of memory operation simulations for various layer sizes and different cell-level access parallelism in an array. Besides, the proposed methods can efficiently simulate memory operations on multilayered 3-D cross-point memory arrays with up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4096\times 4096$ </tex-math></inline-formula> layer size under the 16-GB memory space constraint, achieving a 64-times improvement in layer size that can be simulated compared with the conventional complete 3-D cross-point array network model.

Artificial synaptic and self-rectifying properties of crystalline (Na1-K )NbO3 thin films grown on Sr2Nb3O10 nanosheet seed layers

• Crystalline Na 1-x K x NbO 3 (CNKN) film grown on Sr 2 Nb 3 O 10 (SNO) seed layer at 370 °C. • CNKN film grown on one SNO monolayer shows typical bipolar switching properties. • CNKN film grown on two SNO monolayers shows self-rectifying switching properties. • The CNKN memristor with two SNO monolayers shows artificial synaptic properties. • The CNKN film can be used to fabricate ANNs with a cross-point array structure. Crystalline (Na 1- x K x )NbO 3 (NKN) thin films were deposited on Sr 2 Nb 3 O 10 /TiN/Si (S-TS) substrates at 370 °C. Sr 2 Nb 3 O 10 (SNO) nanosheets served as a template for the formation of crystalline NKN films at low temperatures. When the NKN film was deposited on one SNO monolayer, the NKN memristor exhibited normal bipolar switching characteristics, which could be attributed to the formation and destruction of oxygen vacancy filaments. Moreover, the NKN memristor with one SNO monolayer exhibited artificial synaptic properties. However, the NKN memristor deposited on two SNO monolayers exhibited self-rectifying bipolar switching properties, with the two SNO monolayers acting as tunneling barriers in the memristor. The conduction mechanism of the NKN memristor with two SNO monolayers in the high-resistance state is attributed to Schottky emission, direct tunneling, and Fowler–Nordheim (FN) tunneling. The current conduction in this memristor in the low-resistance state was governed by direct tunneling and FN tunneling. Additionally, the NKN memristor with two SNO monolayers exhibited large ON/OFF and rectification ratios and artificial synaptic properties. Therefore, an NKN memristor with two SNO monolayers can be used for fabricating artificial synaptic devices with a cross-point array structure.

Memristive Switching and Density-Functional Theory Calculations in Double Nitride Insulating Layers.

In this paper, we demonstrate a device using a Ni/SiN/BN/p+-Si structure with improved performance in terms of a good ON/OFF ratio, excellent stability, and low power consumption when compared with single-layer Ni/SiN/p+-Si and Ni/BN/p+-Si devices. Its switching mechanism can be explained by trapping and de-trapping via nitride-related vacancies. We also reveal how higher nonlinearity and rectification ratio in a bilayer device is beneficial for enlarging the read margin in a cross-point array structure. In addition, we conduct a theoretical investigation for the interface charge accumulation/depletion in the SiN/BN layers that are responsible for defect creation at the interface and how this accounts for the improved switching characteristics.

Super-Linear-Threshold-Switching Selector with Multiple Jar-Shaped Cu-Filaments in the Amorphous Ge3 Se7 Resistive Switching Layer in a Cross-Point Synaptic Memristor Array.

The learning and inference efficiencies of an artificial neural network represented by a cross-point synaptic memristor array can be achieved using a selector, with high selectivity (Ion /Ioff ) and sufficient death region, stacked vertically on a synaptic memristor. This can prevent a sneak current in the memristor array. A selector with multiple jar-shaped conductive Cu filaments in the resistive switching layer is precisely fabricated by designing the Cu ion concentration depth profile of the CuGeSe layer as a filament source, TiN diffusion barrier layer, and Ge3 Se7 switching layer. The selector performs super-linear-threshold-switching with a selectivity of > 107 , death region of -0.70-0.65 V, holding time of 300 ns, switching speed of 25 ns, and endurance cycle of >106 . In addition, the mechanism of switching is proven by the formation of conductive Cu filaments between the CuGeSe and Ge3 Se7 layers under a positive bias on the top Pt electrode and an automatic rupture of the filaments after the holding time. Particularly, a spiking deep neural network using the designed one-selector-one-memory cross-point array improves the Modified National Institute of Standards and Technology classification accuracy by ≈3.8% by eliminating the sneak current in the cross-point array during the inference process.

Improved threshold switching characteristics of vanadium oxide/oxynitride-based multilayer selector in a cross-point array

We developed a selector device with the bi-directional threshold switching characteristics of vanadium oxide (VOx) by implementing vanadium oxynitride (VOx:Ny) in a sandwich structure. The proposed device with the Pt/VOx:Ny/VOx/VOx:Ny/Pt structure as opposed to a cell with a Pt/VOx/Pt structure exhibits lower off-current and stable switching characteristics. The elements of the device were analyzed using high-resolution transmission electron microscopy and X-ray photoelectron spectroscopy, and its memory characteristics were verified by applying the Pt/VOx:Ny/VOx/VOx:Ny/Pt selector to amorphous indium-gallium-zinc oxide-based resistive switching (RS) devices in the 1 selector-1 ReRAM structure. Our device shows stable RS properties over 100 DC cycles and> 106 AC cycles, an improved ON/OFF ratio (~67), a high switching speed (<110 ns), and a rectification ratio of ~1 × 103 when the read margin is 10%.

Forming‐Free Resistive Switching Memory Crosspoint Arrays for In‐Memory Machine Learning

In‐memory computing (IMC) with crosspoint arrays of resistive switching memory (RRAM) has gained wide attention for accelerating machine learning, data analysis, and deep neural networks. By IMC, matrix‐vector multiplication (MVM) can be executed in the crosspoint array in just one step, thus accelerating a broad range of tasks in machine learning and data analytics. However, a key issue for RRAM crosspoint arrays is the forming operation of the memories which limits the stability and accuracy of the conductance state in the memory device. In this work, a hardware implementation of crosspoint array of forming‐free devices for fast, energy‐efficient accelerators of MVM is reported. RRAM devices with a 1.5 nm‐thick HfO2 layer show an initial low resistance without forming and an analogue‐mode programming behavior for high‐accuracy IMC. Accurate hardware MVM is demonstrated by experimental eigenvalue/eigenvector calculation according to the power‐iteration algorithm, with a fast convergence within about ten iterations to the correct solution. Deflation technique and principal component analysis (PCA) enable the classification of the Iris dataset with 98% accuracy compared with floating‐point implementation. These results support forming‐free crosspoint arrays for accelerating advanced machine learning with IMC.

A Sneak Current Compensation Scheme With Offset Cancellation Sensing Circuit for ReRAM-Based Cross-Point Memory Array

A sneak current compensation scheme with offset cancellation sensing circuit (SCC-OCSC) adopting dummy bitline and wordline is proposed to resolve sneak current problem in the cross-point memory array. The sneak current degrades sensing yield because it disturbs read operation for high resistance cell, especially, by contaminating read current. Since the sneak current increases proportionally to the array size, the array size is limited to achieve the target sensing yield, which makes it hard to implement high density memory. The proposed SCC-OCSC cancels-out the sneak current through two phases. In first phase, the sneak current is sampled by connecting dummy BL or WL to the sensing circuit. In the second phase, the sneak current is compensated by subtracting the current sampled in the first phase. Furthermore, sensing yield is enhanced by applying the offset cancellation technique, sharing the same sensing circuit in the two phases. The proposed SCC-OCSCs with dummy BL and WL effectively improve read margin with generally used biasing schemes, floating and half-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> schemes, respectively. In Monte-carlo simulation including post-layout sensing circuit with 65nm CMOS technology, it is verified that sensing yield is significantly improved. Thus, the array size assigned to single sensing circuit is extended up to 8-times with SCC-OCSC, leading 88% area reduction with reduced number of required sensing circuit. Performance is improved as 66% and 25% while power consumption is improved as 47% and 37%, by SCC-OCSC with dummy BL in floating scheme and SCC-OCSC with dummy WL in half-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> scheme, respectively.

In-Memory Principal Component Analysis by Crosspoint Array of Resistive Switching Memory: A new hardware approach for energy-efficient data analysis in edge computing

In-Memory Computing (IMC) is one of the most promising candidates for data-intensive computing accelerators of machine learning (ML). A key ML algorithm for dimensionality reduction and classification is principal component analysis (PCA), which heavily relies on matrix-vector multiplications (MVM) for which classic von Neumann architectures are not optimized. Here, we provide the experimental demonstration of a new IMC-based PCA algorithm based on power iteration and deflation executed in a 4-kbit array of resistive switching random-access memory (RRAM). The classification accuracy of the Wisconsin Breast Cancer data set reaches 95.43&#x0025;, close to floating-point implementation. Our simulations indicate a 250&#x00D7; improvement in energy efficiency compared to commercial GPUs, thus supporting IMC for energy-efficient ML in modern data-intensive computing.

Modeling and Compensation of IR Drop in Crosspoint Accelerators of Neural Networks

In-memory computing (IMC) has the potential of accelerating data-intensive computing tasks, such as inference and training of neural networks, by the matrix vector multiplication (MVM) in the crosspoint array. As the array size increases, however, a significant problem arises due to the parasitic IR drop at row and column lines. Understanding and compensating IR drop is essential to enable high-density accelerators of MVM. This work presents an analytical model for the IR drop and a numerical algorithm capable of accelerating the nodal analysis of crosspoint arrays up to five orders of magnitude with respect to SPICE analysis. The numerical algorithm is used to study the impact of array size, data density, device/wire resistance, and nonlinearity on the IR drop and the related loss of accuracy in IMC. We also derive two simple compensation schemes and an architectural solution for the mitigation of IR drop that are able to increase the accuracy of neural networks from 59&#x0025; up to 96.6&#x0025;, compared to an ideal accuracy of 97&#x0025;.

Enhanced Switching Characteristics of an Ovonic Threshold Switching Device With an Ultra-Thin MgO Interfacial Layer

In this study, the effect of a MgO interfacial layer on the electrical characteristics of an ovonic threshold switching (OTS) device was investigated. Compared to the control OTS device, the device with the MgO interfacial layer showed excellent switching uniformity and ultralow off-state leakage current (<inline-formula> <tex-math notation="LaTeX">$\sim 440$ </tex-math></inline-formula>pA) without noticeable changes in the electrical forming process. By extracting the activation energy before and after the forming process, we confirmed that the enhanced switching characteristics were obtained by reducing the interaction between the OTS film and electrodes. Furthermore, the 1S-1R operation with TaO_x-based resistive random access memory (ReRAM) showed successful suppression of the leakage current, which is suitable for a cross-point memory array application.

Controlling the Grain Size of Dion–Jacobson-Phase Two-Dimensional Layered Perovskite for Memory Application

Organic-inorganic halide perovskites (OIHPs) have emerged as an active layer for resistive switching memory (RSM). Among various OIHPs, two-dimensional OIHPs are advantageous in RSMs because of their stability. This stability can be further improved using two-dimensional Dion-Jacobson OIHPs. Moreover, OIHP-based RSMs operated by the formation of halide-ion filaments are affected by grain boundaries because they can act as a shortcut for ion migration. Therefore, it is essential to control the grains in OIHPs for reliable memory operation. Here, we present RSMs using Dion-Jacobson OIHP with controlled grain sizes. The grain sizes of the OIHP are effectively controlled by adjusting the ratio of the N,N-dimethylformamide and dimethyl sulfoxide. The controlled grain sizes can modulate the paths for halide ion migration, which enables the change of the on/off ratio in RSM. In addition, cross-point array structure is essential for high-density memory applications. However, in the cross-point array structure, unwanted current flow through unselected memory cells can happen due to sneak-current paths, so it is necessary to suppress leakage current from neighboring cells by adopting selector devices. We demonstrate the application of selector devices to OIHP-based RSMs to prevent sneak current paths. These results provide the potential of OIHP for use in high-density memory applications.

Impact of Asymmetric Weight Update on Neural Network Training With Tiki-Taka Algorithm.

Recent progress in novel non-volatile memory-based synaptic device technologies and their feasibility for matrix-vector multiplication (MVM) has ignited active research on implementing analog neural network training accelerators with resistive crosspoint arrays. While significant performance boost as well as area- and power-efficiency is theoretically predicted, the realization of such analog accelerators is largely limited by non-ideal switching characteristics of crosspoint elements. One of the most performance-limiting non-idealities is the conductance update asymmetry which is known to distort the actual weight change values away from the calculation by error back-propagation and, therefore, significantly deteriorates the neural network training performance. To address this issue by an algorithmic remedy, Tiki-Taka algorithm was proposed and shown to be effective for neural network training with asymmetric devices. However, a systematic analysis to reveal the required asymmetry specification to guarantee the neural network performance has been unexplored. Here, we quantitatively analyze the impact of update asymmetry on the neural network training performance when trained with Tiki-Taka algorithm by exploring the space of asymmetry and hyper-parameters and measuring the classification accuracy. We discover that the update asymmetry level of the auxiliary array affects the way the optimizer takes the importance of previous gradients, whereas that of main array affects the frequency of accepting those gradients. We propose a novel calibration method to find the optimal operating point in terms of device and network parameters. By searching over the hyper-parameter space of Tiki-Taka algorithm using interpolation and Gaussian filtering, we find the optimal hyper-parameters efficiently and reveal the optimal range of asymmetry, namely the asymmetry specification. Finally, we show that the analysis and calibration method be applicable to spiking neural networks.

Improved Threshold Switching Characteristics of Vanadium Oxide/Oxynitride-Based Multilayer Selector in a Cross-Point Array

Improved Threshold Switching Characteristics of Vanadium Oxide/Oxynitride-Based Multilayer Selector in a Cross-Point Array

Reinforcement-Learning-Based Signal Integrity Optimization and Analysis of a Scalable 3-D X-Point Array Structure

In this article, we, for the first time, propose a reinforcement learning (RL) model to design an optimal 3-D cross-point (X-Point) array structure considering signal integrity issues. The interconnection design problem is modeled to the Markov decision process (MDP). The proposed RL model designs the 3-D X-Point array structure based on three reward factors: the number of bits, the crosstalk, and the IR drop. We applied multilayer perceptron (MLP) and long short-term memory (LSTM) to parameterize the policy. Proximal policy optimization (PPO) is used to optimize the parameters to train the policy. The reward of the proposed RL model is well-converged with variations in the array structure size and hyperparameters of the reward factors. We verified the scalability and sensitivity of the proposed RL model. With the optimal 3-D X-Point array structure design, we analyzed the reward factor and signal integrity issues. The optimal design of the 3-D X-Point array structure shows 17&#x0025;&#x2013;26.5&#x0025; better signal integrity performance than the conventional design in finer process technology. In addition, we suggest a range of possible directions for improvement of the proposed model with variations in MDP tuples, reward factors, and learning algorithms, among other factors. Using the proposed model, we can easily design an optimal 3-D X-Point array structure with a certain size, performance capabilities, and specifications based on reward factors and hyperparameters.

A Brain-Inspired In-Memory Computing System for Neuronal Communication via Memristive Circuits

Brain-inspired approaches can efficiently analyze the activities of biological neural networks and solve computationally hard problems with energy efficiencies unattainable with von Neumann architectures, indicating a significant improvement in the understanding of neuronal communications and functionalities. Here, we present a brain-inspired multimodal signal processing system with organic memristor arrays that can potentially integrate the signal sensory, storage, and computation. To facilitate the multimodal signal processing system design, we used four components. First, we present a multimodal signal sensory module mainly responsible for multimodal (iconic, echoic, olfactory, muscular, and gustatory) signal collection, fusion, and storage. Second, a high-density cross-point memristive synapse array is constructed after fabrication of the albumin protein memristor to realize the dense connectivity between layers of computing, data storage, and communication. Third, considering the structure and function of the brain region, we demonstrate a general learning module for hierarchy learning, which can recognize and imagine multimodal information. Finally, the necessary peripheral circuit module (consisting of winnerless competition function circuit, analog-to-digital converter, digital-to-analog converter, pulse modulator, etc.) is designed. Notably, our system can capture massive amounts of data every second and perform in situ processing of multimodal signals. This study is expected to help achieve the deep integration of nano materials into neuromorphic computing systems and energy-efficient integrated circuits.

Artificial synapse characteristics of a ZnO-based memristor with a short-term memory effect

We fabricated and characterized a Ni/ZnO/TiN memristor device designed to emulate an artificial synapse for use in a neuromorphic system. Chemical and material characterization was conducted using ultraviolet photoelectron spectroscopy, energy-dispersive X-ray spectroscopy, and transmission electron microscopy. The device exhibited gradual resistive switching as a multi-level cell with an increase in the DC sweep voltage. Current decay was observed after the set process, indicating that it could feasibly be employed in short-term memory applications. We demonstrated both short-term memory and long-term memory behavior in the proposed device. Higher conductance was maintained via repetitive pulses with a high voltage and a short time interval, while conductance was lower when repetitive pulses with a low voltage and a short time interval were employed. Pulse interval-dependent paired-pulse facilitation characteristics were used to mimic an artificial synapse, with potentiation and depression observed over multiple cycles. We also evaluated the pattern-recognition accuracy of the proposed conductance modulation with degradation based on the short-term memory effect using a 784 × 10 cross-point array netlist and a SPICE resistor model.