Cross-point Array Research Articles

Study of Weight Quantization Associations over a Weight Range for Application in Memristor Devices

The development of hardware-based cognitive computing systems critically hinges upon the integration of memristor devices capable of versatile weight expression across a spectrum of resistance levels while preserving consistent electrical properties. This investigation aims to explore the practical implementation of a digit recognition system utilizing memristor devices with minimized weighting levels. Through the process of weight quantization for digits represented by 25 or 49 input signals, the study endeavors to ascertain the feasibility of digit recognition via neural network computation. The integration of memristor devices into the system architecture is poised to streamline the representation of the resistors required for weight expression, thereby facilitating the realization of neural-network-based cognitive systems. To minimize the information corruption in the system caused by weight quantization, we introduce the concept of “weight range” in this work. The weight range is the range between the maximum and minimum values of the weights in the neural network. We found that this has a direct impact on weight quantization, which reduces the number of digits represented by a weight below a certain level. This was found to help maintain the information integrity of the entire system despite the reduction in weight levels. Moreover, to validate the efficacy of the proposed methodology, quantized weights are systematically applied to an array of double-layer neural networks. This validation process involves the construction of cross-point array circuits with dimensions of 25 × 10 and 10 × 10, followed by a meticulous examination of the resultant changes in the recognition rate of randomly generated numbers through device simulations. Such endeavors contribute to advancing the understanding and practical implementation of hardware-based cognitive computing systems leveraging memristor devices and weight quantization techniques.

Schottky barrier memory based on heterojunction bandgap engineering for high-density and low-power retention

Dynamic random-access memory (DRAM) has been scaled down to meet high-density, high-speed, and low-power memory requirements. However, conventional DRAM has limitations in achieving memory reliability, especially sufficient capacitance to distinguish memory states. While there have been attempts to enhance capacitor technology, these solutions increase manufacturing cost and complexity. Additionally, Silicon-based capacitorless memories have been reported, but they still suffer from serious difficulties regarding reliability and power consumption. Here, we propose a novel Schottky barrier memory (SBRAM), which is free of the complex capacitor structure and features a heterojunction based on bandgap engineering. SBRAM can be configured as vertical cross-point arrays, which enables high-density integration with a 4F2 footprint. In particular, the Schottky junction significantly reduces the reverse leakage current, preventing sneak current paths that cause leakage currents and readout errors during array operation. Moreover, the heterojunction physically divides the storage region into two regions, resulting in three distinct resistive states and inducing a gradual current slope to ensure sufficient holding margin. These states are determined by the holding voltage (Vhold) applied to the programmed device. When the Vhold is 1.1 V, the programmed state can be maintained with an exceptionally low current of 35.7 fA without a refresh operation.

An emergent attractor network in a passive resistive switching circuit

Resistive memory devices feature drastic conductance change and fast switching dynamics. Particularly, nonvolatile bipolar switching events (set and reset) can be regarded as a unique nonlinear activation function characteristic of a hysteretic loop. Upon simultaneous activation of multiple rows in a crosspoint array, state change of one device may contribute to the conditional switching of others, suggesting an interactive network existing in the circuit. Here, we prove that a passive resistive switching circuit is essentially an attractor network, where the binary memory devices are artificial neurons while the pairwise voltage differences define an anti-symmetric weight matrix. An energy function is successfully constructed for this network, showing that every switching in the circuit would decrease the energy. Due to the nonvolatile hysteretic function, the energy change for bit flip in this network is thresholded, which is different from the classic Hopfield network. It allows more stable states stored in the circuit, thus representing a highly compact and efficient solution for associative memory. Network dynamics (towards stable states) and their modulations by external voltages have been demonstrated in experiment by 3-neuron and 4-neuron circuits.

Effects of Group IVA Elements on the Electrical Response of a Ge2Se3-Based Optically Gated Transistor.

The optically gated transistor (OGT) has been previously demonstrated as a viable selector device for memristor devices, and may enable optical addressing within cross-point arrays. The OGT current-voltage response is similar to a MOSFET device, with light activating the gate instead of voltage. The OGT also provides a naturally built-in compliance current for a series resistive memory element, determined by the incident light intensity on the gate, thus keeping the integrated periphery circuitry size and complexity to a minimum for a memory array. The OGT gate comprises an amorphous Ge2Se3 material that can readily be doped with other elements to alter the transistor's electrical properties. In this work, we explore the operation of the OGT when the Ge2Se3 gate material is doped with the Group IVA elements C, Si, Sn, and Pb. The dopant atoms provide changes to the optical and electrical properties that allow key electrical properties such as the dark current, photocurrent, switching speed, and threshold voltage to be tuned.

Retention-aware zero-shifting technique for Tiki-Taka algorithm-based analog deep learning accelerator.

We present the fabrication of 4 K-scale electrochemical random-access memory (ECRAM) cross-point arrays for analog neural network training accelerator and an electrical characteristic of an 8 × 8 ECRAM array with a 100% yield, showing excellent switching characteristics, low cycle-to-cycle, and device-to-device variations. Leveraging the advances of the ECRAM array, we showcase its efficacy in neural network training using the Tiki-Taka version 2 algorithm (TTv2) tailored for non-ideal analog memory devices. Through an experimental study using ECRAM devices, we investigate the influence of retention characteristics on the training performance of TTv2, revealing that the relative location of the retention convergence point critically determines the available weight range and, consequently, affects the training accuracy. We propose a retention-aware zero-shifting technique designed to optimize neural network training performance, particularly in scenarios involving cross-point devices with limited retention times. This technique ensures robust and efficient analog neural network training despite the practical constraints posed by analog cross-point devices.

Exploration of electrode-modulated memory and threshold switching behaviour in Se-Te-Sn thin film devices

Due to their potential use in high-density, three-dimensional stackable cross-point array structures, the electrical switching ability of chalcogenide glasses has captured a lot of attention. Herein, the switching behaviour of unique Se86-xTe14Snx (x = 0, 2, 4, 6) chalcogenide glassy alloys in the form of a thin film were investigated. The electrode modulated dual functionality in switching was achieved by employing Aluminium (Al) and Silver (Ag), as top electrodes. The films with Al/Se86-xTe14Snx/Al interface exhibited memory-type switching due to the phase-changing properties of the material. The threshold voltage (Vth) decreased linearly from 12.75 V to 4.2 V at room temperature as Sn concentration in the glass increased. On the other hand, when the top electrode was replaced with Ag, the Ag/Se86-xTe14Snx/Al interface acted as a programmable metallization cell (PMC) showing threshold-switching properties. Ag/Se82Te14Sn4/Al thin film of thickness 200 nm showed promising results as a material for a unidirectional selector, due to the formation of temporary Ag filament inside chalcogenide material. The composition showed high selectivity (∼104), high endurance (>104 cycles), and low threshold voltage (∼1.6 V). The ability of the composition to exhibit electrode-dependent memory and threshold-switching phenomena makes the material an interesting case.

Modulation of GeSe and As2Se3 motifs to optimise GeAsSe OTS performance and its mechanism

Ovonic threshold switching (OTS) selectors are pivotal in the construction of highly integrated 3D crosspoint array volatile storage systems, necessitating materials with superior electrical properties.

Multi-Bit Self-Rectifying Synaptic Memristor Having Tri-Layer Structure for Quantization Aware Training of Quantized Neural Network

Recently, a cross-point synaptic memristor arrays have been employed to implement synaptic cores of various ANNs, i.e., deep neural networks (DNNs), spiking neural networks (SNNs), and convolutional neural networks (CNNs). The most of reported studies conducted training and inference of ANNs using analog synaptic weight modulation of memristors such as resistive random access memory (ReRAM), phase change random access memory (PCRAM), and ferroelectric random access memory (FeRAM). In other words, no case has been reported so far in which a synaptic memristor with quantized multi-bit is utilized onto a synaptic core of a quantized neural network (QNN).In this study, for the first time, we introduced the multi-bit self-rectifying synaptic memristor having tri-layer structure being composed of oxygen-rich AlOx rectifying layer, oxygen-deficient HfOx top switching layer, and oxygen-rich HfOy bottom switching layer for quantization aware training of QNN. The resistive switching and self-rectifying mechanism of the multi-bit self-rectifying synaptic memristor was evidently proven by precisely investigating migration of oxygen ions and vacancies in resistive switching layers via ToF-SIMS and XPS depth profiles depending on the resistance states (i.e., pristine, set, and reset). The designed multi-bit self-rectifying synaptic memristor presented linear, discrete, and quantized 4-bit (i.e., 16-level) conductance level depending on incremental write pulse number, which was 4-bit self-rectifying synaptic memristor for the first time. In addtion, the quantization aware training (QAT) was conducted using 4-bit quantized conductance level of the desgiend multi-bit self-rectifying synaptic memristor via stright through estimator (STE). Finally, three different iris datasets were successfully classified using a quantized neural network designed via SPICE circuit simulation. The conductance mechanism of the self-rectifying synaptic memristor and its application of QNN will be presented in detail. Acknowledgement This research was supported by National R&D Program through the National Research Foundation of Korea(NRF) funded by Ministry of Science and ICT(2021M3F3A2A01037733) Figure 1

Ag-GST/HfOx-based unidirectional threshold switching selector with low leakage current and threshold voltage distribution for high-density cross-point arrays

Ag-GST/HfOx-based unidirectional threshold switching selector with low leakage current and threshold voltage distribution for high-density cross-point arrays

Thermal atomic layer deposition of ternary Ge-S-Se alloy for advanced ovonic threshold switch selectors in three-dimensional cross-point memory array

Two-terminal ovonic threshold switch (OTS) selectors based on chalcogenide alloys have attracted significant attention as alternatives to conventional silicon-based transistors. These selectors offer outstanding features that enable the mass production of three-dimensional cross-point arrays for advanced memory technologies. In this study, we developed a thermal atomic layer deposition (ALD) process for ternary Ge-S-Se alloys. By utilizing ALD super-cycles of Ge-Se and Ge-S, a broad range of film compositions can be achieved. We investigated the electrical characteristics and film properties of the deposited films, with a focus on their smooth surfaces and excellent conformality, which are indispensable characteristics for future vertical cross-point structures. By incorporating S into the Ge-Se film via an ALD super-cycle, we achieved a significant reduction in off-current of Ge0.50S0.15Se0.35 to approximately 35 nA. Additionally, the thermal stability of Ge0.50S0.15Se0.35 film is enhanced up to 420 ℃ due to the higher bandgap and shorter bonding length of S, exhibiting a cyclic endurance of more than 5 × 107. This research not only provides insight into the control of the film composition to improve and modify device characteristics but also constructs a foundation of ALD-based OTS research on ternary Ge-S-Se for a future X-point memory application.

Dual-Mode Operations of Self-Rectifying Ferroelectric Tunnel Junction Crosspoint Array for High-Density Integration of IoT Devices

This study proposes a self-rectifying ferroelectric tunnel junction (SR-FTJ) crosspoint array to satisfy the stringent size requirements of the Internet-of-Things devices. Each cell in the SR-FTJ crosspoint array consists of two SR-FTJs stacked vertically, resulting in ultrahigh density. The SR-FTJ crosspoint array can operate as: 1) ternary content-addressable memory (TCAM) or 2) binary content addressable memory (BCAM) or physically unclonable function (PUF) in the dual-mode operation. In the dual-mode operation, the amount of the current flowing through the SR-FTJs remains the same, resulting in a stable PUF response regardless of the BCAM data. The dual-mode operation of the SR-FTJ crosspoint array is experimentally verified by 4-in wafer-level demonstrations. HSPICE simulation results using the industrial-compatible 180-nm technology with the SR-FTJ model reflecting measured characteristics show that the SR-FTJ crosspoint array achieves the lowest search energy (2.05 fJ/search/bit) and the highest randomness (Hamming weight of 0.5000) among the previous content addressable memories (CAMs) and PUFs. In addition, the SR-FTJ crosspoint array reduces area by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt;$</tex-math> </inline-formula> 84.2% compared to the previous structures that implement individual CAM and PUF.

Thermally stable threshold selector based on CuAg alloy for energy-efficient memory and neuromorphic computing applications

As a promising candidate for high-density data storage and neuromorphic computing, cross-point memory arrays provide a platform to overcome the von Neumann bottleneck and accelerate neural network computation. In order to suppress the sneak-path current problem that limits their scalability and read accuracy, a two-terminal selector can be integrated at each cross-point to form the one-selector-one-memristor (1S1R) stack. In this work, we demonstrate a CuAg alloy-based, thermally stable and electroforming-free selector device with tunable threshold voltage and over 7 orders of magnitude ON/OFF ratio. A vertically stacked 64 × 64 1S1R cross-point array is further implemented by integrating the selector with SiO2-based memristors. The 1S1R devices exhibit extremely low leakage currents and proper switching characteristics, which are suitable for both storage class memory and synaptic weight storage. Finally, a selector-based leaky integrate-and-fire neuron is designed and experimentally implemented, which expands the application prospect of CuAg alloy selectors from synapses to neurons.

A Generalized Block-Matrix Circuit for Closed-Loop Analog In-Memory Computing

Matrix-based computing is ubiquitous in an increasing number of present-day machine learning applications such as neural networks, regression and 5G communications. Conventional systems based on von-Neumann architecture are limited by the energy and latency bottleneck induced by the physical separation of the processing and memory units. Inmemory computing (IMC) is a novel paradigm where computation is performed directly within the memory, thus eliminating the need for constant data transfer. IMC has shown exceptional throughput and energy efficiency when coupled with crosspoint arrays of resistive memory devices in open-loop matrix-vector-multiplication and closed-loop inverse-matrix-vector multiplication (IMVM) accelerators. However, each application result in a different circuit topology, thus complicating the development of reconfigurable, general-purpose IMC systems. In this paper, we present a generalized closed-loop IMVM circuit capable of performing any linear matrix operation by proper memory remapping. We derive closed-form equations for the ideal input/ output transfer functions, static error, and dynamic behavior, introducing a novel continuous-time analytical model allowing for orders-of-magnitude simulation speedup with respect to SPICE-based solvers. The proposed circuit represents an ideal candidate for general-purpose accelerators of machine learning.

Improving the GeAsSe Ovonic Threshold Switching Characteristics by Carbon Buffer Layers for Ultralow Leakage Current (∼0.4 nA) and Low Drift Characteristics

Volatile Ovonic threshold switching (OTS) selectors have been regarded as the critical component of highly integrated three-dimensional (3D) cross-point array nonvolatile memory systems. However, relatively high leakage current hinders the further reduction of power consumption in the crossbar array. In addition, the threshold voltage drift phenomenon hinders the improvement of device reliability. Utilizing the buffer layer can effectively reduce the interaction between electrodes and the active layer in the cross-point architecture. Here, it manifests that leakage current can be reduced to ∼0.4 nA with a 5 nm thick amorphous carbon layer as a buffer layer in the GeAsSe-based OTS device, where the carbon layer stabilizes the composition of GeAsSe during the electrical switching cycles. It is also found that the carbon layer leads to a lower threshold voltage drift (35.6 mv/dec) and excellent endurance (>109 cycles with ∼0.4 nA ON-state current). The conduction mechanism analysis demonstrates that the inhibition of the carbon layer on drift originates from the high barrier height from delocalized states transformed into localized states. This work clearly demonstrates the role of the carbon layer and facilitates future 3D crossbar-storage technology applications.

A Self-Rectifying Synaptic Memristor Array with Ultrahigh Weight Potentiation Linearity for a Self-Organizing-Map Neural Network

Two-terminal self-rectifying (SR)-synaptic memristors are preeminent candidates for high-density and efficient neuromorphic computing, especially for future three-dimensional integrated systems, which can self-suppress the sneak path current in crossbar arrays. However, SR-synaptic memristors face the critical challenges of nonlinear weight potentiation and steep depression, hindering their application in conventional artificial neural networks (ANNs). Here, a SR-synaptic memristor (Pt/NiOx/WO3-x:Ti/W) and cross-point array with sneak path current suppression features and ultrahigh-weight potentiation linearity up to 0.9997 are introduced. The image contrast enhancement and background filtering are demonstrated on the basis of the device array. Moreover, an unsupervised self-organizing map (SOM) neural network is first developed for orientation recognition with high recognition accuracy (0.98) and training efficiency and high resilience toward both noises and steep synaptic depression. These results solve the challenges of SR memristors in the conventional ANN, extending the possibilities of large-scale oxide SR-synaptic arrays for high-density, efficient, and accurate neuromorphic computing.

Hybrid Precision in Resistive Memory-Based Convolutional Kernel for Fault-Resilient Neuromorphic Systems

As simple convolution computation is intensively and iteratively performed to extract features from input images, cross-point arrays with resistive random access memory (RRAM) serving as a kernel weight can accelerate the relevant mathematical operations in hardware. However, considering actual RRAM characteristics, either variability or unexpected permanent failure from the filamentary switching mechanism is observed, degrading recognition performance. This study investigates the impact of fault in a conventional kernel structure, where two adjacent columns in the array represent a single weight, on feature extraction using MATLAB. First, the fault types of HfO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\textit{x}}$</tex-math> </inline-formula> -based multilevel RRAM is categorized. The results reveal that the unidirectional fault of RRAM primarily worsens the accuracy of image recognition. This is because the subtraction of negative weights from positive ones is crucial for identifying the edges of images through convolution operations. Therefore, we exploit a kernel structure, in which a single column dedicated to negative weights is located next to a matrix of positive weights. In addition, we reduce the weight precision for negative weights, while quantizing positive weights to higher bits. By mitigating the subtraction errors achieved by the kernel structure with hybrid precision, we improved fault tolerance, minimizing accuracy degradation.

Neuromorphic learning and forgetting functions of Pt/Ti0.99Sc0.01O2−δ /Pt multilayer by Schottky barrier modulation

We have studied the neuromorphic learning and forgetting functions of Pt/Ti0.99Sc0.01O2–δ /Pt multilayer films with a cross-point array prepared by RF magnetron sputtering and probed their mechanism. The Ti0.99Sc0.01O2–δ layer with an oxygen vacancy ratio of ∼2.5% exhibited high electron–proton mixed conduction. The multilayer draws a nonlinearity current–voltage curve owing to the Schottky barrier between the upper or lower Pt and Ti0.99Sc0.01O2–δ layers. Two singular current modulations corresponding to the learning long-term memory (LTM) and the short-term memory (STM) functions were observed by applying positive voltage pulses of 0.8 V with interval times of 14 s and 80 s, respectively. Furthermore, the forgetting LTM function of the human brain is also exhibited by applying negative voltage pulses of 1.0 V with an interval time of 14 s. These neuromorphic current responses are considered to be attributed to the collaborative behaviors of electron, proton, and oxygen vacancy at the Schottky barrier.

Cell Design Considerations for Ovonic Threshold Switch-Based 3-D Cross-Point Array

This study presents cell design parameters to be considered for a two-terminal ovonic threshold switch (OTS) and phase-change memory (PCM)-based array, with an example of 3-D cross-point array (XPA). The 1-Mb 3-D XPA in this study was simulated using MATLAB. The array characteristics were analyzed using the Monte–Carlo simulation for the variability of OTS characteristics. We observed that the OTS threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{th}}$ </tex-math></inline-formula> ) variation further accelerates the IR drop, increasing <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{th}}$ </tex-math></inline-formula> of cells in real XPAs. This further reduces the read window margin (RWM) and inhibit-fail margin (IFM), creating constraints on 1-Mb normal operation. The IR drop is more significant at RESET (RST) than the selected cell is at SET. Furthermore, the higher the RST resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text{rst}}$ </tex-math></inline-formula> ), the more severe it is, increasing the inhibit bias and worsening inhibit fails. Based on the simulation results, the raw bit error rate (RBER) of the 3-D XPA device can be minimized by balancing <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text{rst}}$ </tex-math></inline-formula> of the PCM to minimize the error bits between failures from insufficient RWMs and inhibit fails, as the two errors are directly related to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text{rst}}$ </tex-math></inline-formula> . Finally, we show that the 3-D XPA device can be fabricated when <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text{rst}}$ </tex-math></inline-formula> of the memory material is sufficiently large to minimize failures from insufficient RWM, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{th}}$ </tex-math></inline-formula> (OTS <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{th}}$ </tex-math></inline-formula> ) of the selector material is adjustable to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text{rst}}$ </tex-math></inline-formula> to minimize inhibit fails.

Locally formed conductive filaments in an amorphous Ga2Te3 ovonic threshold switching device

Ovonic threshold switching (OTS) selector devices based on chalcogenide materials are promising candidates for addressing the sneak current in high-density cross-point array structures owing to their high selectivity, high endurance, and fast switching speed. However, the OTS mechanism remains controversial and needs to be clarified. In this study, the formation of local conductive filaments (CFs) during threshold switching in an amorphous Ga2Te3 OTS selector device was investigated by electrical measurements and conductive-atomic force microscopy (C-AFM). The amorphous Ga2Te3 OTS selector device requires a forming process before the threshold switching processes. In addition, the off-current density (JOFF) was dependent on the area of the bottom electrode. The difference between the threshold voltage (VTH) and the hold voltage (VH) increased as the applied higher electric field increased. The drift of VTH (VTH drift) depended on the relaxation time and measurement temperature. The requirements of the forming process, area dependence of the JOFF, the difference between the VTH−VH with the applied electric field, and VTH drift are expected to depend on locally formed CFs. In addition, the analysis of the C-AFM results strongly supports the formation of local CFs during threshold switching in an amorphous Ga2Te3 OTS selector device. The understanding of OTS behavior uncovered in this study may provide guidance for improving the characteristics of and designing materials for future applications of OTS selector devices.

In-memory computing with emerging memory devices: Status and outlook

In-memory computing (IMC) has emerged as a new computing paradigm able to alleviate or suppress the memory bottleneck, which is the major concern for energy efficiency and latency in modern digital computing. While the IMC concept is simple and promising, the details of its implementation cover a broad range of problems and solutions, including various memory technologies, circuit topologies, and programming/processing algorithms. This Perspective aims at providing an orientation map across the wide topic of IMC. First, the memory technologies will be presented, including both conventional complementary metal-oxide-semiconductor-based and emerging resistive/memristive devices. Then, circuit architectures will be considered, describing their aim and application. Circuits include both popular crosspoint arrays and other more advanced structures, such as closed-loop memory arrays and ternary content-addressable memory. The same circuit might serve completely different applications, e.g., a crosspoint array can be used for accelerating matrix-vector multiplication for forward propagation in a neural network and outer product for backpropagation training. The different algorithms and memory properties to enable such diversification of circuit functions will be discussed. Finally, the main challenges and opportunities for IMC will be presented.