Cross-point Array Structure Research Articles

Artificial synaptic and self-rectifying properties of crystalline (Na1-K )NbO3 thin films grown on Sr2Nb3O10 nanosheet seed layers

• Crystalline Na 1-x K x NbO 3 (CNKN) film grown on Sr 2 Nb 3 O 10 (SNO) seed layer at 370 °C. • CNKN film grown on one SNO monolayer shows typical bipolar switching properties. • CNKN film grown on two SNO monolayers shows self-rectifying switching properties. • The CNKN memristor with two SNO monolayers shows artificial synaptic properties. • The CNKN film can be used to fabricate ANNs with a cross-point array structure. Crystalline (Na 1- x K x )NbO 3 (NKN) thin films were deposited on Sr 2 Nb 3 O 10 /TiN/Si (S-TS) substrates at 370 °C. Sr 2 Nb 3 O 10 (SNO) nanosheets served as a template for the formation of crystalline NKN films at low temperatures. When the NKN film was deposited on one SNO monolayer, the NKN memristor exhibited normal bipolar switching characteristics, which could be attributed to the formation and destruction of oxygen vacancy filaments. Moreover, the NKN memristor with one SNO monolayer exhibited artificial synaptic properties. However, the NKN memristor deposited on two SNO monolayers exhibited self-rectifying bipolar switching properties, with the two SNO monolayers acting as tunneling barriers in the memristor. The conduction mechanism of the NKN memristor with two SNO monolayers in the high-resistance state is attributed to Schottky emission, direct tunneling, and Fowler–Nordheim (FN) tunneling. The current conduction in this memristor in the low-resistance state was governed by direct tunneling and FN tunneling. Additionally, the NKN memristor with two SNO monolayers exhibited large ON/OFF and rectification ratios and artificial synaptic properties. Therefore, an NKN memristor with two SNO monolayers can be used for fabricating artificial synaptic devices with a cross-point array structure.

Memristive Switching and Density-Functional Theory Calculations in Double Nitride Insulating Layers.

In this paper, we demonstrate a device using a Ni/SiN/BN/p+-Si structure with improved performance in terms of a good ON/OFF ratio, excellent stability, and low power consumption when compared with single-layer Ni/SiN/p+-Si and Ni/BN/p+-Si devices. Its switching mechanism can be explained by trapping and de-trapping via nitride-related vacancies. We also reveal how higher nonlinearity and rectification ratio in a bilayer device is beneficial for enlarging the read margin in a cross-point array structure. In addition, we conduct a theoretical investigation for the interface charge accumulation/depletion in the SiN/BN layers that are responsible for defect creation at the interface and how this accounts for the improved switching characteristics.

Controlling the Grain Size of Dion–Jacobson-Phase Two-Dimensional Layered Perovskite for Memory Application

Organic-inorganic halide perovskites (OIHPs) have emerged as an active layer for resistive switching memory (RSM). Among various OIHPs, two-dimensional OIHPs are advantageous in RSMs because of their stability. This stability can be further improved using two-dimensional Dion-Jacobson OIHPs. Moreover, OIHP-based RSMs operated by the formation of halide-ion filaments are affected by grain boundaries because they can act as a shortcut for ion migration. Therefore, it is essential to control the grains in OIHPs for reliable memory operation. Here, we present RSMs using Dion-Jacobson OIHP with controlled grain sizes. The grain sizes of the OIHP are effectively controlled by adjusting the ratio of the N,N-dimethylformamide and dimethyl sulfoxide. The controlled grain sizes can modulate the paths for halide ion migration, which enables the change of the on/off ratio in RSM. In addition, cross-point array structure is essential for high-density memory applications. However, in the cross-point array structure, unwanted current flow through unselected memory cells can happen due to sneak-current paths, so it is necessary to suppress leakage current from neighboring cells by adopting selector devices. We demonstrate the application of selector devices to OIHP-based RSMs to prevent sneak current paths. These results provide the potential of OIHP for use in high-density memory applications.

Bipolar and Complementary Resistive Switching Characteristics and Neuromorphic System Simulation in a Pt/ZnO/TiN Synaptic Device.

In this work, a ZnO-based resistive switching memory device is characterized by using simplified electrical conduction models. The conventional bipolar resistive switching and complementary resistive switching modes are accomplished by tuning the bias voltage condition. The material and chemical information of the device stack including the interfacial layer of TiON is well confirmed by transmission electron microscopy (TEM) and X-ray photoelectron spectroscopy (XPS) analysis. The device exhibits uniform gradual bipolar resistive switching (BRS) with good endurance and self-compliance characteristics. Moreover, complementary resistive switching (CRS) is achieved by applying the compliance current at negative bias and increasing the voltage at positive bias. The synaptic behaviors such as long-term potentiation and long-term depression are emulated by applying consecutive pulse input to the device. The CRS mode has a higher array size in the cross-point array structure than the BRS mode due to more nonlinear I–V characteristics in the CRS mode. However, we reveal that the BRS mode shows a better pattern recognition rate than the CRS mode due to more uniform conductance update.

Nonlinear Characteristics of Complementary Resistive Switching in HfAlOx-Based Memristor for High-Density Cross-Point Array Structure

In this work, we present the nonlinear current–voltage (I–V) characteristics of a complementary resistive switching (CRS)-like curve from a HfAlOx-based memristor, used to implement a high-density cross-point array. A Pt/HfAlOx/TiN device has lower on-current and larger selectivity compared to Pt/HfO2/TiN or Pt/Al2O3/TiN devices. It has been shown that the on-current and first reset peak current after the forming process are crucial in obtaining a CRS-like curve. We demonstrate transient CRS-like characteristics with high nonlinearity under pulse response for practical applications. Finally, after finding the optimal conditions for high selectivity, the calculated read margin proves that a Pt/HfAlOx/TiN device with a CRS-like curve is most suitable for use in a high-density cross-point array. Our results suggest that the built-in selector properties in a Pt/HfAlOx/TiN single layer device offer considerable potential in terms of the simplicity of the processes involved in the cross-point structure.

Improving Multilevel Writes on Vertical 3-D Cross-Point Resistive Memory

Resistive memory is promising to be constructed as a high-density storage-class memory. Multilevel cell, access-transistor-free cross-point array structure, and 3-D array integration are three approaches to scale up the density of resistive memory. However, composing the three approaches together strengthens the interactions between array-level and cell-level nonidealities (interconnect resistance-induced IR drop, sneak current, and device variability) of resistive memory arrays during write operations and significantly degrades write performance and reliability. In this article, we analyze the dynamic voltage-dividing effect along a selected write current path in 3-D cross-point memory arrays. We propose a nonideality-tolerant high-density resistive memory (HD-RRAM) architecture, that can weaken the interactions between nonidealities and mitigate their degradation effects on the performance and reliability of array multilevel write operations. HD-RRAM is equipped with a double-transistor array architecture with two-transistor- $n$ -resistor (2TnR) cell organization along pillars to reduce the current driving requirement and the large undesired voltage drop across each vertical pillar access transistor. Moreover, multiside asymmetric bias improves the resistive switching velocity by leveraging current-dividing effects. Variability-aware multilevel state partition reduces the worst-case write error rate by leveraging target state dependency of variability. Proportional-control multilevel state tuning reduces the average number of required write-and-verify iterations by leveraging pulse amplitude dependency of variability. Multilevel cell parallel writing improves the cell-level parallelism by leveraging the pass-through feature of intermediate resistance states. The evaluations show that HD-RRAM reduces both memory access latency and energy consumption over an aggressive baseline.

Firing voltage reduction in thermally annealed Ge–As–Te thin film with ovonic threshold switching

Recently, chalcogenide materials have exhibited ovonic threshold switching characteristics, improving their suitability as selector devices to effectively depress the sneak current in the cross-point array (CPA) structures. However, chalcogenides must be subjected to a firing process before they can exhibit the threshold switching behavior. The firing process causes operation problems with respect to the memory operation process in the case of the CPA structure. Although the firing process is expected to be related to Joule heating with a high electric current, the physical nature of the changes during the firing process remains unclear. In this study, selector devices are fabricated by sandwiching amorphous Ge–As–Te thin films between the TiN and W layers. Furthermore, the authors examine the microstructure of the Ge–As–Te thin films before and after the electric firing process using transmittance electron microscopy (TEM, JEOL JEM-F200). The TEM analysis of the pristine Ge–As–Te thin films denotes the uniform contrast of the image, which implies the uniform chemical composition of the film. However, the Ge–As–Te thin films exhibit nonuniform contrast due to the effects of Joule heating after the electric firing process. The Ge–As–Te thin films were thermally annealed at 150 and 250 °C for 1 min via the rapid thermal annealing process to verify the effects of thermal treatment on the firing process in chalcogenide thin films. The effect of thermal annealing on the threshold switching behavior was also investigated by studying the compositional stability. Their results showed that the thermal annealing process caused the uniform compositions on the pristine Ge–As–Te films to be fluctuated with decreasing firing voltage for threshold switching.

Design and Measurement Requirements for Short Flow Test Arrays to Characterize Emerging Memories

Emerging non-volatile memories are becoming increasingly attractive for embedded and storage-class applications. Among the development challenges of Back-End integrated memory cells are long learning cycles and high wafer cost. We propose a short-flow based approach for characterization of Memory Arrays using a Cross-Point Array structure and highly parallel Parametric Test. A detailed analysis of design requirements and testability, including inverse circuit simulation, confirms feasibility of the approach to reduce Turn-Around Time and development costs.

Selection Device with Cu Doped-Chalcogenide Material for 3D Cross-Point Array Structure of 1selector-1resistor Memory Cells

Resistive random access memories (ReRAMs) have been researched to replace current NAND flash memory due to non-volatile memory characteristics, low power consumption, high operation speed, and minimum 4F2 memory cell size[1]. However, to achieve high density of tera-bit level cells, it is needed to operate ReRAM cells with cross-point array structure which required selection device to limit the sneak current path in high-density ReRAM cells. Therefore, recently bi-directional selection devices with two-terminal structure such as ovonic threshold switching (OTS)[2], p-n-p type (PNP)[3], and mixed ionic electronic conduction (MIEC)[4] have been researched to suppress the sneak current path. In this work, we investigated the electrical features of the selection device with Cu-doped chalcogenide material to attain high non-linearity(>105), high on-state current(Ion )(>10 MA/cm2) and low off-state current(Ioff )(<0.01 kA/cm2) because Cu ions moved well by E-field and generated interstitials/vacancies acting as dopants. We fabricated the selection device of the structure of W / Cu-doped chalcogenide material / Pt by varying the pattern size of ranging 34 to 1,921 nm as shown in Fig.1. The device performance of Ion , Ioff , threshold voltage(VT ), and non-linearity(Ion @Von/Ioff @1/2Von ) was characterized. The Cu-doped chalcogenide material layer was deposited by RF magnetron co-sputtering on W bottom electrode patterned by photo lithography process. Then, Pt top electrode was deposited by DC magnetron sputtering. The selection device with Cu-doped chalcogenide material demonstrated threshold voltage of ~1.0 V, low Ioff of < 3.66 mA/cm2, Ion of > 1.82 A/cm2, and non-linearity of > 500 as shown in Fig.2. Finally, we present how the device performance is affected by varying the film thickness, annealing temperature, device size and stack-layer structure. In addition, the uniformity and the reliability of the selection device such as endurance cycling and retention time were investigated. In particular, the mechanism on operating behavior of the selection device will be presented by analyzing the composition and crystallinity of Cu-doped chalcogenide film by using Auger, energy-dispersive X-ray spectroscopy (EDS), cross sectional transmission electron microscopy (TEM) and X-ray diffraction (XRD). *This work was financially supported by the Ministry of Trade, Industry & Energy(MOTIE, Korea) under Industrial Technology Innovation Program (10068055), the Brain Korea 21 Plus 2016, Republic of Korea and Hanyang University-Samsung Electronics selector research project. Reference [1] Choi, B. J et al., Advanced Materials 23, 3847-3852 (2011). [2] S. Kim et al., VLSI, T240 (2013) [3] S. Jo et al., IEDM, 6.7.1 (2014) [4] G. Burr et al., VLSI, p41 (2012) Figure 1

Metal Halide Perovskites: A Strategy to Design High‐Density Nanoscale Devices utilizing Vapor Deposition of Metal Halide Perovskite Materials (Adv. Mater. 29/2017)

In article number 1701048, Jang-Sik Lee and Bohee Hwang report an approach for designing high density memory devices utilizing organolead halide perovskite (OHP) materials with a cross-point array structure which is deposited by sequential vapor deposition. The OHP-based nanoscale memory devices exhibit remarkably fast switching speed, low operating voltage, and long data retention. OHPs which are a key material in solar cells have a great potential to be used in high-density information storage devices.

A Strategy to Design High-Density Nanoscale Devices utilizing Vapor Deposition of Metal Halide Perovskite Materials.

The demand for high memory density has increased due to increasing needs of information storage, such as big data processing and the Internet of Things. Organic-inorganic perovskite materials that show nonvolatile resistive switching memory properties have potential applications as the resistive switching layer for next-generation memory devices, but, for practical applications, these materials should be utilized in high-density data-storage devices. Here, nanoscale memory devices are fabricated by sequential vapor deposition of organolead halide perovskite (OHP) CH3 NH3 PbI3 layers on wafers perforated with 250 nm via-holes. These devices have bipolar resistive switching properties, and show low-voltage operation, fast switching speed (200 ns), good endurance, and data-retention time >105 s. Moreover, the use of sequential vapor deposition is extended to deposit CH3 NH3 PbI3 as the memory element in a cross-point array structure. This method to fabricate high-density memory devices could be used for memory cells that occupy large areas, and to overcome the scaling limit of existing methods; it also presents a way to use OHPs to increase memory storage capacity.

Nonlinear and multilevel resistive switching memory in Ni/Si3N4/Al2O3/TiN structures

In this letter, we extensively investigate the nonlinear resistive switching characteristics of Si3N4-based resistive random access memory (RRAM) devices that contain an Al2O3 tunnel barrier layer to alleviate sneak path currents in the cross-point array structure. When the compliance current (ICC) exceeds 1 mA, the Ni/Si3N4/TiN device shows both unipolar and bipolar switching with Ohmic characteristics in the low resistance state. Nonlinear resistive switching characteristics were observed for this device when ICC was ≤100 μA. We fabricated Si3N4/Al2O3 bilayer devices with different tunnel barrier layer thickness and characterized their nonlinear characteristics and failure resistance during the reset process. Furthermore, we obtained stable multiple resistance levels in the devices by varying ICC and the stop voltage for the set and reset switching, respectively. Our results suggest that an Al2O3 tunnel barrier layer embedded in Si3N4-based RRAM devices offers considerable potential to realize high-density cross-point memory array applications.

Ferroelectric Tunnel Junction for Dense Cross-Point Arrays.

Cross-point array (CPA) structure memories using a memristor are attracting a great deal of attention due to their high density integration with a 4F2 cell. However, a common significant drawback of the CPA configuration is crosstalk between cells. To date, the CPA structure using a redox-based memristor has restrictions to minimize the operating current level due to their resistive switching mechanism. This study demonstrates suitable characteristics of a ferroelectric tunnel junction (FTJ) for the memristor of the CPA structure using an electrostatic model. From the FTJ of the Au/p-type Pr0.98Ca0.02MnO3 (4 nm)/BaTiO3 (4.3 nm)/n-type Ca0.98Pr0.02MnO3 (3 nm)/Pt(111) structure, which has a higher and thicker potential barrier, a good memristive effect for the CPA structure with a high nonlinear current-voltage curve and low current operation, was obtained by Δ Fowler-Nordheim tunneling with effectively blocked direct tunneling and thermionic emission. The FTJ demonstrated reduced sneak current and the possible for high nonlinearity.

Ovonic Threshold Switching Selection Device Based on Chalcogenide ZnTe for Cross-Point ReRAM Device

Cross-point array structure has attracted increasing attention for high-density ReRAM, owing to the development of ReRAM with promising scalability. Cross-point array of only resistors(1R) cannot function because of sneak current through unselected devices, which can be reduced by integrating resistive memory elements with bidirectional nonlinear selection devices(1S1R). Namely, the high value of Kw in ON states, which is the writing current @ Vwrite / the current @ 1/2Vwrite, was required in cross-point ReRAM memory industry. In this study, the high current density non-linear IV curve of Ovonic threshold switching(OTS) selection device based on Chalcogenide ZnTe was shown and the ALD HfO2 switching device has the linear properties of ON states and the compliance current of 100uA. In 1S1R unit cells based on ZnTe OTS selection device of low off current (< 400nA) and HfO2 switching device, excellent non-linear characteristics of ON states such as Kw of 522, Kr (reading current @Vread / current @ 1/2Vread) of 1430 and on/off ratio of 43 were shown. OTS behaviors with ZnTe film thickness, device area and annealing temperatures were investigated. Initial current during electro-forming process was decreased but OTS characteristics were not changed with increasing ZnTe thickness and decreasing device area. Initial current in electro-forming process and OTS characteristics at annealing temperature of below 200°C was not changed, but initial current and off current was rapidly increased and threshold voltage (Vth) in OTS was decreased at above 250°C because of Te diffusion in ZnTe film. To suppress the diffusion of Te atoms, the reactive N2during deposition which can improve the thermal stability of the chalcogenide glass was performed. And chemical compositions of ZnTe thin films were analyzed by Rutherford backscattering spectrometry(RBS). Also, crystallinity as a function of annealing temperature was investigated by Raman spectroscopy, X-ray diffraction (XRD) and plan-view transmission electron microscopy (TEM).

Array Architecture for a Nonvolatile 3-Dimensional Cross-Point Resistance-Change Memory

This work explores the design and capabilities of a three-dimensional cross-point array structure suitable for use with resistance-change non-volatile memory. The resistance-change cell serves as both the access element and the memory element, eliminating the need for individual selection devices. This work presents novel architecture and circuit techniques that minimize leakage current effects while maintaining a high effective bit density. A test chip fabricated in 0.18 μm CMOS technology verifies the architecture and circuit functionality. The performance of an 8 Gb memory chip built in 65 nm technology has been simulated. A random access time of 104 ns is achieved with a power dissipation of 61.2 mW. This makes the 3D cross-point memory competitive with NOR flash in terms of read time, and competitive with NAND flash in terms of area efficiency.