Cross-coupled Inverters Research Articles

Design of reliable and fast Schmitt trigger 10T SRAM cells using in-memory computing

Abstract Microprocessors, integrated data storage systems, and cache memories are just a few applications that can benefit from Static random access memory (SRAM). Computing In memory provides a solution for the von Neumann bottleneck problems. Simultaneously, it removes needless repeated data transmission between CPU and memory. Schmitt trigger was utilized for energy-efficient operation to get high reading and writing capacity. Two cross-coupled inverters with a transistor in between increase the design writing process. Furthermore, voltage boost logic is prioritized to maximize the node capacity. Using two dummy columns and dummy rows in RAM, the Replica technique controls the flow of signals via the core. The simulated results are compared to the designs that already exist. The simulation results show that the leakage power of the proposed design is 0.75 nw at 0.6 volts. The write static noise margin (WSNM) of the proposed cell is twice that of SEDF10T, which can be helpful for high-performance computing applications.

A Cryo-CMOS 10-bit 60-MS/s SAR ADC with common-mode variation suppression switching scheme and gain boosting dynamic comparator

This paper presents a 10-bit 60-MS/s SAR ADC using an energy-efficient common-mode variation suppression (CMVS) switching scheme. The proposed CMVS switching scheme reduces energy consumption by about 92 % compared to the conventional scheme. Also, it narrows the common-mode variation to 16.6 % VDD. It improves the accuracy of the SAR ADC and makes the comparator and SAR ADC operate at the best-performance region. The proposed comparator adopts a gain boosting dynamic capacitive pre-amplifier to enhance the amplification and accelerate the comparison speed. The regeneration latch keeps the cross-coupled inverter structure to ensure high-speed regeneration. The input pair of the latch suppresses the through current while decreasing the regeneration speed. Therefore, an auxiliary input pair is added to enhance the regeneration speed. The SAR ADC is designed and simulated using 65-nm Cryo-CMOS technology with VDD = 1.2 V. At T = 300 K, it achieves a FoM of 15.39 fJ/conversion-step with 55-MS/s. At T = 4 K, it achieves a FoM of 14.15 fJ/conversion-step with 60-MS/s.

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

In this paper, a carbon nanotube field-effect transistor (CNTFET) based low power and robust ternary SRAM (TSRAM) cell with enhanced static noise margin (SNM) has been proposed. The proposed cell uses a low-power cell core and a stack of 2 CNTFETs to discharge the read bit line (RBL) to ground, unlike the previous SRAM designs which use read buffers or transmission gates (TG) to alter the voltage levels on the RBL. The proposed TSRAM cell has been simulated relentlessly, using the Stanford 32 nm CNTFET technology mode file with Synopsis HSPICE tool under various operating conditions. Unlike other designs, the cross-coupled ternary inverters used as the cell core in the proposed TSRAM show higher gain and steep curves in the transition region mitigating the static power of the cell. The simulation results exhibit improvements in performance parameters like power consumption, energy, noise margins, and reliability. At 0.9 V supply voltage, the proposed TSRAM cell offers 52.44% and 43.17% reduction in write and read static power, a PDP reduction of 35.29% in comparison, and a 36.36% improvement in SNM compared to the best designs under investigation. Also, the proposed TSRAM design shows higher robustness compared to other designs.

Design and analysis of a high-speed low-power comparator with regeneration enhancement and through current suppression techniques from 4 K to 300 K in 65-nm Cryo-CMOS

This paper presents a high-speed low-power cryogenic CMOS two-stage dynamic comparator for SAR ADC. The pre-amplifier uses the dynamic bias technique to save power. To increase the output voltage difference of the pre-amplifier, the StrongARM latch is inserted. The proposed latch keeps a cross-coupled inverter to ensure good positive feedback. The tail current source of the proposed latch is replaced by the input pair to suppress the through current. The auxiliary input pair enhances the gain and positive feedback to speed up the latch. The paper also presents a delay analysis of the dynamic bias technique, which gives a deep understanding and a good intuition for circuit design. The simulation results demonstrate the proposed comparator achieved a CLK-Q delay of 162.1 ps and 295.4 ps at Vid = 1 mV and VCM = 0.7 V with VDD = 1.2 V and fs = 1 GHz in 300 K and 4K. The energy per comparison is 34.04 fJ and 27.75 fJ.

-Memory Computing Based Reliable and High Speed Schmitt trigger 10T SRAM cell design

Static random access memories (SRAM) are useful building blocks in various applications, including cache memories, integrated data storage systems, and microprocessors. The von Neumann bottleneck difficulties are solved by in-memory computing. It eliminates unnecessary frequent data transfer between memory and processing units simultaneously. In this research, the replica-based 10T SRAM design for in-memory computing (IMC) is designed by adapting the word line control scheme in 14nm CMOS technology. In order to achieve high reading and writing capability, the Schmitt trigger inverter was used for energy-saving and stable use. To speed up the writing process of the design, a single transistor is inserted between the cross-coupled inverters. In addition, to increase the node capacity, the voltage boosting circuitry is emphasized. The adaptive word line control scheme was utilized by integrating the replica column based circuit. The Replica approach regulates signal flow through the core by using a dummy column and a dummy row in RAM. To demonstrate the viability of the suggested design, the simulated outcomes are contrasted with those of existing designs. The various performance metrics examined are Read Static Noise Margin (RSNM), Write (WSNM), Hold (HSNM), Read Access Delay (RAD), Write Access Delay (WAD), Read performance and Write performance the varying supply voltage is evaluated.

SEU Hardened D Flip-Flop Design with Low Area Overhead.

D flip-flop (DFF) is the basic unit of sequential logic in digital circuits. However, because of an internal cross-coupled inverter pair, it can easily appear as a single event upset (SEU) when hit by high-energy particles, resulting in the error in the value stored in the flip-flop. On this basis, a new structure D flip-flop is proposed in this paper. This flip-flop uses an asymmetric scheme in which the master-slave latch adopts different hardening structures. By sacrificing circuit speed in exchange for stronger SEU fortification capability, the SEU threshold of this structure is improved by 10 times compared to traditional D flip-flops. It has also been compared with Dual Interlocked Storage Elements (DICEs), and it saves the area cost of six transistors compared to the DICE structure. Under the same operating conditions, the average power consumption and peak power consumption are, respectively, 9.8% and 18.8% lower than those of the DICE circuit, making it suitable for soft radiation environments where high circuit speed is not a critical requirement.

Soft-Error-Aware Radiation-Hardened Ge-DLTFET-Based SRAM Cell Design

In this paper, a soft-error-aware radiation-hardened 6T SRAM cell has been implemented using germanium-based dopingless tunnel FET (Ge DLTFET). In a circuit level simulation, the device-circuit co-design approach is used. Semiconductor devices are very prone to the radiation environment; hence, finding out the solution to the problem became a necessity for the designers. Single event upset (SEU), also known as soft error, is one of the most frequent issues to tackle in semiconductor devices. To mitigate the effect of soft error due to single-event upset, the radiation-hardening-by-design (RHBD) technique has been employed for Ge DLTFET-based SRAM cells. This technique uses RC feedback paths between the two cross-coupled inverters of an SRAM cell. The soft-error sensitivity is estimated for a conventional and RHBD-based SRAM cell design. It is found that the RHBD-based SRAM cell design is more efficient to mitigate the soft-error effect in comparison to the conventional design. The delay and stability parameters, obtained from the N-curve, of the Ge DLTFET-based SRAM cell performs better than the conventional Si TFET-based SRAM cell. There is an improvement of 305x & 850x in the static power noise margin and write trip power values of the Ge DLTFET SRAM cell with respect to the conventional Si TFET SRAM cell.

CMOS-compatible ising machines built using bistable latches coupled through ferroelectric transistor arrays

Realizing compact and scalable Ising machines that are compatible with CMOS-process technology is crucial to the effectiveness and practicality of using such hardware platforms for accelerating computationally intractable problems. Besides the need for realizing compact Ising spins, the implementation of the coupling network, which describes the spin interaction, is also a potential bottleneck in the scalability of such platforms. Therefore, in this work, we propose an Ising machine platform that exploits the novel behavior of compact bi-stable CMOS-latches (cross-coupled inverters) as classical Ising spins interacting through highly scalable and CMOS-process compatible ferroelectric-HfO2-based Ferroelectric FETs (FeFETs) which act as coupling elements. We experimentally demonstrate the prototype building blocks of this system, and evaluate the scaling behavior of the system using simulations. Our work not only provides a pathway to realizing CMOS-compatible designs but also to overcoming their scaling challenges.

A New Design Paradigm for Auto-Nonvolatile Ternary SRAMs Using Ferroelectric CNTFETs: From Device to Array Architecture

Preserving the data stored in a static random access memory (SRAM) during power gating or a sudden power outage is a necessary but costly need. This work proposes an ultraefficient auto-nonvolatile ternary SRAM (ATSRAM) cell using ferroelectric carbon nanotube field-effect transistors (Fe-CNTFETs). By harnessing the unique features in Fe-CNTFETs, the proposed ATSRAM utilizes only 12 transistors. The proposed design can automatically perform backup and restore operations without additional resources and nonvolatile elements during a power outage. This unique specification eliminates the redundancies usually required to provide nonvolatility. The utilized hysteretic cross-coupled two-transistor standard ternary inverters (STIs) provide a superior static noise margin (SNM) beyond the binary SRAMs and the ideal noise margin limitation ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DD}}$ </tex-math></inline-formula> /4). The proposed ATSRAM array structure benefits from a row-shared supply disconnector to mitigate the static current drawn from the power supply during data retention. Our results demonstrate that the proposed ATSRAM indicates, on average, 40% improvement in transistor count, 2.8 times higher SNMs, 27% reduction in total power consumption, and 41% (66%) improvement in the read (write) energy compared with the state-of-the-art volatile ternary SRAMs. In a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${32} \times {32}$ </tex-math></inline-formula> ternary array configuration, 94% (98%) improvement in the read (write) energy is obtained compared with the other counterparts. Our design methodology provides a new paradigm for designing ultraefficient and ultracompact nonvolatile multivalued logic (MVL) memories using ferroelectric-based FETs.

Heuristic Approach in Ring Voltage Controlled Oscillator Design for V.C.O. Based Analog to Digital Conterters

Abstract This paper introduces a procedure that relies on Computer Aided Design tools (industry compatible SPICE simulator and MATLAB) to get a first rapid design solution for a ring voltage controlled oscillator (VCO) that can be further analyzed and optimized for usage in a VCO based analog to digital converter (ADC). Due to the fact that linearity is a key performance metric of an ADC a special attention will be given to this characteristic during the design and for this matter control mechanism will be analyzed. To exemplify the design procedure two different delay cell topologies (simple inverter and pseudo-differential cross-coupled inverters) will be analyzed and designed in a 130 nm CMOS technology.

Improved Read/Write Stability-Based Level Shift 5T Ternary SRAM Cell Design Using Enhanced Gate Diffusion Input BWGCNTFET

Nowadays, CNTFET introduced the complexity of SRAM design along with the stability. To overcome these complexities, an enhanced Gate Diffusion Input technique-based Ballistic wrap gate CNTFET (EGDI-BWGCNTFET) technology with ternary static random-access memory (T-SRAM) is proposed in this paper. The aim of the proposed technique is “to give higher stability with less stagnant power consumption, voltage drop and store appropriate read/write value of the SRAM cells”. Here, level shift 5T ternary SRAM cell design using Enhanced Gate Diffusion Input Ballistic wrap gate CNTFET (level shift EGDI-BWGCNTFET 5T-ternary SRAM) is proposed for improving read and write stability. It uses two cross-coupled EGDI-BWGCNTFET ternary inverter, which is used for data storage elements along with one access transistor which is connected with bit line (BL) and word line (WL) with minimum supply voltage resulting in leakage current that is decreased. By this, proposed method reduces delay in the write cycles and read cycles. It provides good read static noise margin (RSNM) and controls precharge voltage. The proposed level shift EGDI-BWGCNTFET 5T-ternary SRAM is done in HSPICE platform. The performance of the proposed level shift EGDI-BWGCNTFET 5T-ternary SRAM design is measured in terms of lower Read Delay 23.25%, 22.94%, 18.38%, 23.97%, lower Write Delay 33.92%, 28.94%, 42.83%, 31.98% compared with the existing methods, such as 8T CNTFET-Ternary SRAM, 24T CNTFET-2Ternary SRAM, 18T CNTFET-Ternary SRAM and 17T CNTFET-Ternary SRAM, respectively.

Quadruple and Sextuple Cross-Coupled SRAM Cell Designs With Optimized Overhead for Reliable Applications

Aggressive technology scaling makes modern advanced SRAMs more and more vulnerable to soft errors such as single-node upsets (SNUs) and double-node upsets (DNUs). This paper proposes two SRAM cells; the first one is called Quadruple Cross-Coupled SRAM (QCCS) and the second one is called Sextuple Cross-Coupled SRAM (SCCS). The QCCS cell comprises four cross-coupled input-split inverters to keep stored values, and provides self-recoverability from SNUs at low cost. To improve reliability, the SCCS cell uses six cross-coupled input-split inverters to construct a large error-interceptive feedback loop and hence robustly keep stored values. The SCCS cell can self-recover from all possible SNUs and one part of DNUs; for remaining DNUs, a node-separation mechanism is used to avoid their occurrence. Simulation results demonstrate the robustness of the proposed cells. Moreover, compared with the state-of-the-art hardened cells, i.e., NASA13T, RHBD12T, We-Quatro, Zhang14T, QUCCE12T, DNUSRM, QCCM10T, QCCM12T, S4P8N, and S8P4N, the QCCS cell reduces read access time by 17%, write access time by 19%, power dissipation by 4% and silicon area overhead by 10% on average, while the SCCS cell reduces read access time by 44% as well as write access time by 13% on average at the cost of moderate increase in power dissipation and silicon area overhead.

Non-Volatile Latch Compatible With Static and Dynamic CMOS for Logic in Memory Applications

To overcome the performance bottleneck of the CMOS-only logic circuits, logic-in-memory (LiM)-based circuits can be used. Herein, the memory and logic are combined to reduce the power requirements and the data access delay. The LiM architecture is proposed to be better in terms of efficiency when compared to the Von-Neumann architecture which is currently being used. In this article, a novel non-volatile (NV) latch is proposed to realize the LiM-based computation. It is compared with previous circuit architectures of the NV latch. The proposed latch consists of multiple magnetic tunnel junctions (MTJs) connected in series which are accessed through an NMOS transistor for reading the data. A cross-coupled inverter (CCI) is used to regenerate the output to the appropriate logic levels using its inherent regenerative action. The proposed latch has a simple design, higher stability, and lower tunnel magnetoresistance (TMR) degradation, and compatibility with static and dynamic CMOS logic styles. Furthermore, the proposed latch is having fewer transistor count in logic implementation which result in minimized area overhead and lower power consumption. The existing write circuit is also modified for writing the MTJs in the proposed NV latch which results in a 29.57% reduction in power consumption for a write margin of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$20 ~\mu \text{A}$ </tex-math></inline-formula> and 34.92% for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$40 ~\mu \text{A}$ </tex-math></inline-formula> write margin. Furthermore, the area requirement of the modified write circuit is found to be significantly lower than that of the existing write circuit.

An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications

In this paper, a latch-based energy-efficient dynamic comparator is presented in Carbon Nanotube Field Effect Transistor (CNTFET) technology. The proposed comparator consists of two main stages: pre-amplifier and latch. The latch stage is designed for the main purpose of low-power consumption and high-speed performances. The proposed speed-up technique for the latch structure controls the threshold voltage (Vth) of the cross-coupled inverters. So, the delay of the latch stage decreases and consequently, the overall delay of the comparator circuit is also reduced up to 19.4% while the maximum speed performance of the proposed comparator increases by 54% compared to the conventional double-tail dynamic comparator. Additionally, the use of the proposed distinctive structure for the tail transistors in the latch stage, leads to more than 11% reduction in the energy per conversion of the proposed circuit compared to the conventional double-tail dynamic comparator. To verify the circuit performances, the comparator circuit is simulated in HSPICE using 32 nm CNTFET Stanford model technology parameters. The simulation results show that the proposed comparator with the proposed speed-up approach can operate up to 14.2 GHz with a sensitivity of 30 μV at the supply voltage of 1 V, while consumes only 42.38 μW of power. Therefore, the proposed comparator can be used in high-resolution (up to 12 bit) and high-speed low-power analogue-to-digital converter applications. Moreover, the effects of the non-ideal fabrication process (including the pitch and the threshold voltage variations), supply voltage and temperature variations are investigated in this work. Monte-Carlo analysis shows that the standard deviation of the offset voltage is approximately 1.24 mV. Finally, the kickback noise of the proposed comparator is obtained as 80 μV, which shows the proper performance of the proposed comparator circuit in comparison with other reported designs.

Distributed sensing via the ensemble spectra of uncoupled electronic chaotic oscillators

An electronic chaos generator involving cross-coupled inverter rings with lengths equal to the smallest odd prime numbers is considered, and a spatiotemporally-varying control parameter, hypothetically corresponding to a physical variable to be sensed, is introduced akin to a baseband signal. It is shown that, owing to the fine-grained structure of the spectrogram conveniently generated by this circuit, the control parameter setting and its fluctuations can be accurately estimated from the frequency spectrum, or a portion of it, for instance using a small neural network. Mimicking the effect of a passive receiver listening to a set of such nodes, the effect of summing the partially spectrally-overlapping and largely incoherent signals arising from multiple unsynchronized transmitters is then considered. The possibility of estimating some features of the statistical and topographical distribution of the control parameter from the frequency spectrum of the population ensemble signal(s) is indicated. Physical feasibility is corroborated by experiments involving an integrated circuit prototype realized using 65 nm CMOS technology, through which measurement reproducibility is also assessed. The proposed approach may have advantages for realizing distributed sensing applications because synchronization among the sensor nodes is not required, allowing the use of considerably simpler transmitters rather than mutually-coupled oscillators.

Low-power 25Gb/s 16:1 Multiplexer for 400Gb/s Ethernet PHY

A lower power 25Gb/s 16:1 multiplexer using 65nm CMOS technology for 400Gb/s Ethernet (400GbE) physical layer (PHY) interface was presented. CMOS+CML mixed logic is adopted to achieve hierarchical architecture, avoiding the high clock requirement of one-step structure and improving the transmission speed. In order to reduce power while achieving high data rate, multiplexing structure is also optimized by utilizing multi-frequency multi-phase technology which not only ensures the requirement of the phase stabilization, but also leaves out some flip-flops. For CMOS-CML conversion circuit, transmission gate and cross-coupled CMOS inverter are used to match the delay of CMOS inverter, suppressing the effect of common-mode noise. Simulation results show that the multiplexer works correctly and jitter of output signal is less than 0.1UI. When voltage is 1.2V, the total power is 32.7mW at 25Gb/s.

A Comprehensive Analysis of Different SRAM Cell Topologies in 7-nm FinFET Technology

Complementary metal-oxide-semiconductor (CMOS) device faces various unknown short channel effects (SCEs) such as subthreshold leakage and drain-induced barrier lowering (DIBL) in advanced technologies. This degrades the circuit’s performance, especially SRAM cell, owing to the high demand for large density. Fin-shaped field-effect transistor (FinFET) is one of the trending choices for memory designers, which can improve the stability and minimize the SCEs of the CMOS devices. In this study, different SRAM cell topologies are redesigned and re-simulated by using 7-nm FinFET devices, and then, their performance metrics including the stability, access time, and power are measured at a certain range of supply voltage (VDD) below the nominal value of 0.7 V. Moreover, the layout of these SRAM cells is designed and compared in which the ST12T cell consumes the maximum area due to having a higher count of transistors. Simulated results inferred that the ST11T cell offers the highest RSNM among all the SRAM cells, which can be explained with the use of read decoupling technique and cross-coupled Schmitt-trigger inverters. Moreover, the ST12T cell has the highest WSNM in comparison to other SRAM cells because this cell performs its write operation in fully differential form along with a power-gating write-assist technique. In the view of power consumption, the ST11T and ST12T cell offers the least dynamic and leakage power dissipation, respectively, because the former cell is single-ended bitcell with a low frequency and the latter one has stacked transistors in its cell core in which the path from power VDD to GND is long. An electrical quality metric (EQM) is utilized to assess the overall performance of these SRAM cells, which displays the superiority of the ST12T cell.

5‐T and 6‐T thermometer‐code latches for thermometer‐code shift‐register

This paper proposes thermometer-code latches having five and six transistors for unidirectional and bidirectional thermometer-code shift-registers, respectively. The proposed latches omit the set and reset transistors by changing from two supply voltage nodes to the set and reset signals in the cross-coupled inverter. They set or reset the data by changing the supply voltage to ground in either of two inverters. They reduce the number of transistors to five and six compared with the conventional thermometer-code latches having six and eight transistors, respectively. The proposed thermometer-code latches were simulated using a 65 nm complementary metal-oxide-semiconductor (CMOS) process. For comparison, the proposed and conventional latches are adapted to the 64 bit thermometer-code shift-registers. The proposed unidirectional and bidirectional shift-registers occupy 140 μm2 and 197 μm2, respectively. Their consumption powers are 4.6 μW and 5.3 μW at a 100 MHz clock frequency with the supply voltage of 1.2 V. They decrease the areas by 16% and 13% compared with the conventional thermometer-code shift-register.

Differential Read/Write 7T SRAM With Bit-Interleaved Structure for Near-Threshold Operation

Near-threshold voltage ( $V_{th}$ ) operation is an effective method for lowering energy consumption. However, it increases the impact of $V_{th}$ variation significantly, which makes it difficult for previously proposed static random access memory (SRAM) bitcells to achieve high read stability and write ability yields. To achieve these in the near- $V_{th}$ region, a differential 7T SRAM bitcell is proposed in which an additional row-based control signal and an nMOS transistor between the pull-up and pull-down transistors is adopted on one side of the cross-coupled inverter. In addition, the proposed SRAM bitcell can use a bit-interleaved structure without the half-select issue. Compared to differential 10T and 12T SRAM, the proposed differential 7T SRAM achieves 5% and 6% higher SRAM operating frequency and 70% and 23% lower operation energy consumption with a 33% and 49% smaller bitcell area, respectively.

A Reconfigurable SRAM Based CMOS PUF With Challenge to Response Pairs

This paper presents a reconfigurable SRAM-based physically unclonable function (PUF) topology with multiple challenge-response pairs (CRPs) per cell. The proposed PUF structure enables a very large CRP space by connecting additional pull-up and pull-down paths to each SRAM cell. These alternate pathways to the supply rail and ground are activated by the challenge inputs, which effectively reconfigure the transfer characteristics of each cross-coupled inverter. A newly proposed response instability detector improves bit error rate (BER) performance by discarding unstable response. In addition, the proposed PUF adds indirect challenges by scrambling the responses using a Galois linear feedback shift register (LFSR). The proposed PUF can be applied to a wider range of applications as a CRP PUF because it has multiple CRPs in addition to the small area and fast operating speed, which are the advantages of the conventional SRAM structure. In order to verify the performance of the proposed architecture, a 32×32-bit reconfigurable SRAM PUF array with 32-bit challenge is implemented in a 65 nm CMOS process. Experimental results show a core area of 88.867 μ m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /bit, energy efficiency of 0.082 pJ/bit, and inter-chip Hamming distance (HD) of 48.93% across 40 chips. By applying an unstable bit discard (UBD) scheme, BER is improved from 13.7% to 0.9%. Compared to the state-of-the-art, the proposed PUF is shown to be highly competitive in area, throughput and energy efficiency.