CPU Processing Research Articles

Performance Evaluation of Selected Encryption Algorithms

Data security is a key aspect of today’s communication trend and growth. Various mechanisms have been developed to achieve this security. One is cryptography, which represents a most effective method of enhancing security and confidentiality of data. In this work, a hybrid based 136bit key algorithm involving a sequential combination of XOR (Exclusive –Or) encryption and AES (Advanced Encryption Standard) algorithm to enhance the security strength is developed. The hybrid algorithm performance is matched with XOR encryption and AES algorithm using encryption and decryption time, throughput of encryption, space complexity and CPU process time.

FSEI-GPU: GPU accelerated simulations of the fluid–structure–electrophysiology interaction in the left heart

The reliability of cardiovascular computational models depends on the accurate solution of the hemodynamics, the realistic characterization of the hyperelastic and electric properties of the tissues along with the correct description of their interaction. The resulting fluid–structure–electrophysiology interaction (FSEI) thus requires an immense computational power, usually available in large supercomputing centers, and requires long time to obtain results even if multi–CPU processors are used (MPI acceleration). In recent years, graphics processing units (GPUs) have emerged as a convenient platform for high performance computing, as they allow for considerable reductions of the time–to–solution.This approach is particularly appealing if the tool has to support medical decisions that require solutions within reduced times and possibly obtained by local computational resources. Accordingly, our multi–physics solver [1] has been ported to GPU architectures using CUDA Fortran to tackle fast and accurate hemodynamics simulations of the human heart without resorting to large–scale supercomputers. This work describes the use of CUDA to accelerate the FSEI on heterogeneous clusters, where both the CPUs and GPUs are used in synergistically with minor modifications of the original source code. The resulting GPU accelerated code solves a single heartbeat within a few hours (from three to ten depending on the grid resolution) running on premises computing facility made of few GPU cards, which can be easily installed in a medical laboratory or in a hospital, thus opening towards a systematic computational fluid dynamics (CFD) aided diagnostic.

Direct Numerical Simulation of Stratified Turbulent Flows and Passive Tracer Transport on HPC Systems: Comparison of CPU Architectures

In this paper we assess the influence of CPU architectures commonly used in HPC systems on the efficiency of the implementation of algorithms used for direct numerical simulation (DNS) of turbulent flows. We consider a stably stratified turbulent plane Couette flow as a benchmark problem supplemented with the additional transport of passive substances. The comparison includes the Intel Xeon, AMD Rome x86 CPU architecture processors and the Huawei Kunpeng ARM CPU processor. We discuss the role of memory-oriented optimizations on the efficiency of tracer transport implementation on each platform.

Low-Complexity 2D-MUSIC for Joint Range and Angle Estimation of Frequency Modulated Continuous-Wave Radar

A pre-processing technique is proposed to reduce the complexity of two-dimensional multiple signal classification (2D-MUSIC) for the joint range and angle estimation of frequency-modulated continuous-wave (FMCW) radar systems. By using the central symmetry of the angle steering vector from a uniform linear array (ULA) antenna and the linearity of the beat signal in the FMCW radar, this preprocessing technique transforms 2D-MUSIC from complex values into real values. To compare the computational complexity of the proposed algorithm with the conventional 2D-MUSIC, we measured the CPU processing time for various numbers of snapshots, and the evaluation results indicated that the 2D-MUSIC with the proposed pre-processing technique is approximately three times faster than the conventional 2D-MUSIC.

Energy-efficient algebra kernels in FPGA for High Performance Computing

The dissemination of multi-core architectures and the later irruption of massively parallel devices, led to a revolution in High-Performance Computing (HPC) platforms in the last decades. As a result, Field-Programmable Gate Arrays (FPGAs) are re-emerging as a versatile and more energy-efficient alternative to other platforms. Traditional FPGA design implies using low-level Hardware Description Languages (HDL) such as VHDL or Verilog, which follow an entirely different programming model than standard software languages, and their use requires specialized knowledge of the underlying hardware. In the last years, manufacturers started to make big efforts to provide High-Level Synthesis (HLS) tools, in order to allow a grater adoption of FPGAs in the HPC community.Our work studies the use of multi-core hardware and different FPGAs to address Numerical Linear Algebra (NLA) kernels such as the general matrix multiplication GEMM and the sparse matrix-vector multiplication SpMV. Specifically, we compare the behavior of fine-tuned kernels in a multi-core CPU processor and HLS implementations on FPGAs. We perform the experimental evaluation of our implementations on a low-end and a cutting-edge FPGA platform, in terms of runtime and energy consumption, and compare the results against the Intel MKL library in CPU.

A User-Centric Data Protection Method for Cloud Storage Based on Invertible DWT

Protection on end users’ data stored in Cloud servers becomes an important issue in today’s Cloud environments. In this paper, we present a novel data protection method combining Selective Encryption (SE) concept with fragmentation and dispersion on storage. Our method is based on the invertible Discrete Wavelet Transform (DWT) to divide agnostic data into three fragments with three different levels of protection. Then, these three fragments can be dispersed over different storage areas with different levels of trustworthiness to protect end users’ data by resisting possible leaks in Clouds. Thus, our method optimizes the storage cost by saving expensive, private, and secure storage spaces and utilizing cheap but low trustworthy storage space. We have intensive security analysis performed to verify the high protection level of our method. Additionally, the efficiency is proved by implementation of deploying tasks between CPU and General Purpose Graphic Processing Unit (GPGPU) in an optimized manner.

Impact of Processing-Resource Sharing on the Placement of Chained Virtual Network Functions

Network Function Virtualization (NFV) provides higher flexibility for network operators and reduces the complexity in network service deployment. Using NFV, Virtual Network Functions (VNF) can be located in various network nodes and chained together in a Service Function Chain (SFC) to provide a specific service. Consolidating multiple VNFs in a smaller number of locations would allow decreasing capital expenditures. However, excessive consolidation of VNFs might cause additional latency penalties due to processing-resource sharing, and this is undesirable, as SFCs are bounded by service-specific latency requirements. In this paper, we identify two different types of penalties (referred as "costs") related to the processingresource sharing among multiple VNFs: the context switching costs and the upscaling costs. Context switching costs arise when multiple CPU processes (e.g., supporting different VNFs) share the same CPU and thus repeated loading/saving of their context is required. Upscaling costs are incurred by VNFs requiring multi-core implementations, since they suffer a penalty due to the load-balancing needs among CPU cores. These costs affect how the chained VNFs are placed in the network to meet the performance requirement of the SFCs. We evaluate their impact while considering SFCs with different bandwidth and latency requirements in a scenario of VNF consolidation.

Multi-GPU implementation of a cellular automaton model for dendritic growth of binary alloy

A parallel three-dimensional (3D) cellular automaton (CA) model is developed for dendritic growth simulation during solidification of binary alloy. The CA model is implemented using the graphic processing unit (GPU). Compute Unified Device Architecture (CUDA) is combined with Message Passing Interface (MPI) to perform large-scale simulation on the multi-GPU architecture. A CUDA-Aware OpenMPI is used to reduce the communication cost between different GPU cards. The accuracy and the speedup ratio of the CA model are investigated. First, the simulated steady-state tip velocity under different undercooling is compared with the LGK analytical solution. Then, dendritic growth during directional solidification and equiaxed multi-dendrite growth are simulated. Dendritic growth simulation with a domain size up to 453 million grids is performed. Finally, the speedup ratio of the CA model using four GPUs is compared with that using four CPU processes via MPI, which leads to a maximal speedup ratio of 152.19. The developed CA model achieves high parallel performance compared with the MPI-based parallel model. The developed CA model is capable of predicting the columnar to equiaxed transition (CET) event during directional solidification. The results indicate that increasing cooling rate promotes the occurrence of the equiaxed dendrites in the melt ahead of the solidification front, and equiaxed dendrites are prone to nucleate in the columnar dendrite groove zone when a middle cooling rate is applied.

Comparison of the Efficiency and Theoretical Hardware Consumption of Four Different Dynamic and Static Branch Predictors

When CPU enters the era of instruction level parallelism, the execution cycle of instructions has become shorter and shorter. Meanwhile, the processing speed of CPU has become faster and faster. However, only from the execution process of CPU instructions, there is a key factor that limits the speed of CPU processing instructions, namely, the branch instruction processing. The branch predictor is used to predict the execution result of the current branch instruction (taken/non-taken), which can make the program counter get the target instruction to continue to execute according to the prediction result before calculating the target jump address. If the prediction is correct, it will greatly improve the execution efficiency of CPU. This paper starts from the two basic categories of static branch prediction and dynamic branch prediction. Then analyse their prediction principle, prediction accuracy and component consumption used for prediction. For static branch predictor, its hardware consumption is less than that of dynamic branch predictor, and its accuracy is also lower than that of dynamic branch predictor. Moreover, their shortcomings are pointed out in this paper. At last, based on the original branch predictor, better branch predictors developed in recent years are introduced. In the future, considering the hardware consumption, I think the development of branch predictor will continue to optimize the branch predictor combining global history and local history, from the number of stored entries, the correlation between branch instructions and so on. On the premise of executing a large number of instructions, every little improvement in the efficiency of the predictor will bring huge benefits.

Optimization of deep neural network-based human activity recognition for a wearable device

Human activity recognition (HAR) attempts to classify performed activities from data retrieved from different sensors attached to the body. Most publications pertaining to HAR based on deep neural networks (DNNs) report the development of a suitable architecture to improve recognition accuracy by increasing the parameters of the architecture. Our work follows a different approach by attempting to optimise DNN-based HAR by reducing the dimensions of acceleration data, by finding a suitable sample size for processing by the DNN and by reducing the parameters of the proposed architecture. The experiments rely on employing two previously presented DNN-based HAR architectures as the baselines and starting points to create our candidate architectures. The variations in the dimensions of acceleration data, i.e., {xy, yz, xz, x, y, z}, and the sample size, i.e. {4, 6, 8} s duration, to these candidate architectures are experimented to produce the winner architecture which takes the shortest sample size and the minimal dimensions of acceleration data while preserving the recognition precision. The results indicate that despite the number of parameters is approximately half of the baseline architecture with two dimensions of acceleration data and shorter sample size (i.e., using a sample of 4 s duration instead of 8 s and only the xy axes of acceleration data), the resulting DNN-based HAR classifiers can produce comparable or better recognition precision than the baseline classifiers. The experimental results were obtained using three different popular datasets: the WISDM, the UCI HAR, and the Real World 2016. The proposed classifiers with optimised settings are useful as they require less processing time and reduce power consumption, both in terms of retrieving acceleration data from the sensor and the CPU processing time. Furthermore, they reduce the memory requirements for parameter storing and are suitable for incorporation in a wearable device.

On the performance of a highly-scalable Computational Fluid Dynamics code on AMD, ARM and Intel processor-based HPC systems

No area of computing is hungrier for performance than High Performance Computing (HPC), the demands of which continue to be a major driver for processor performance and adoption of accelerators, and also advances in memory, storage, and networking technologies. A key feature of the Intel processor domination of the past decade has been the extensive adoption of GPUs as coprocessors, whilst more recent developments have seen the increased availability of a number of CPU processors, including the novel ARM-based chips. This paper analyses the performance and scalability of a state-of-the-art Computational Fluid Dynamics (CFD) code on two HPC cluster systems: Hawk, equipped with AMD EPYC-Rome (EPYC, 4096 cores) and Intel Skylake (SKL, 8000 cores) processors and Infiniband EDR interconnect; and Isambard, equipped with ARM-based Marvell ThunderX2 (TX2, 8192 cores) and a Cray Aries interconnect. The code Hydro3D was analysed in three benchmark cases with increasing level of numerical complexity, namely lid-driven cavity flow using 4th-order central-differences, Taylor-Green vortex solved with a 5th-order WENO scheme, and a travelling solitary wave computed using the level-set method and WENO; in problem sizes designed with larger computation-to-communication ratio on a single or multiple nodes. Our results show that the EPYC cluster delivers the best code performance for all the setups under consideration. In the first two benchmarks, the SKL cluster demonstrates faster computing times than the TX2 system, whilst in the solitary wave simulations, the TX2 cluster achieves good scalability and similar performance to the EPYC system, both improving on that obtained with the SKL cluster. These results suggest that while the Intel SKL cores deliver the best strong scalability, the associated cluster performance is lower compared to the EPYC system. The TX2 cluster performance is promising considering its recent addition to the HPC portfolio.

A Set of Batched Basic Linear Algebra Subprograms and LAPACK Routines

This article describes a standard API for a set of Batched Basic Linear Algebra Subprograms (Batched BLAS or BBLAS). The focus is on many independent BLAS operations on small matrices that are grouped together and processed by a single routine, called a Batched BLAS routine. The matrices are grouped together in uniformly sized groups, with just one group if all the matrices are of equal size. The aim is to provide more efficient, but portable, implementations of algorithms on high-performance many-core platforms. These include multicore and many-core CPU processors, GPUs and coprocessors, and other hardware accelerators with floating-point compute facility. As well as the standard types of single and double precision, we also include half and quadruple precision in the standard. In particular, half precision is used in many very large scale applications, such as those associated with machine learning.

Secure mobile internet voting system using biometric authentication and wavelet based AES

The number of mobile phone users increases daily, and mobile devices are used for various applications like banking, e-commerce, social media, internet voting, e-mails, etc. This paper presents a secure mobile internet voting system in which a biometric method authenticates the voter. The biometric image can either be encrypted at the mobile device and send to the server or process the biometric image at the mobile device to generate the biometric template and send it to the server. The implementation of biometrics on mobile devices usually requires simplifying the algorithm to adapt to the relatively small CPU processing power and battery charge. This paper proposes a wavelet-based AES algorithm to speed up the encryption process and reduce the mobile device’s CPU utilization. The experimental analysis of three methods(AES encryption, wavelet-based AES encryption, and biometric template generation) exhibits that wavelet-based AES encryption is much better than AES encryption and template generation. The security analysis of three methods shows that AES and wavelet-based AES encryption provides better security than the biometric template’s protection. The study of the proposed internet voting system shows that biometric authentication defeats almost all the mobile-based threats.

HGP4CNN: an efficient parallelization framework for training convolutional neural networks on modern GPUs

Graphics Processing Units (GPUs) have evolved into powerful accelerators for the development of Convolutional Neural Network (CNN) models. Most existing GPU-based frameworks adopt a kernel-based execution approach and only focus on optimizing individual kernels for better performance and resource utilization. With this approach, kernels involved will be launched sequentially, which may result in the underutilization of GPU resources due to the limited optimization space of a single kernel. In this paper, we propose an efficient software parallelization framework, called HGP4CNN, to accelerate the training of CNN models by considering the characteristics of workloads from both the same layer and adjacent layers as well as new GPU features such as concurrent kernel execution. In the intra-layer level, to achieve a better training performance of a single network layer, we design a novel model-based lightweight parallelization module to make better use of the concurrent kernel execution feature on modern GPUs. An asynchronous resource tracker is used to collect kernels’ information at runtime, and a kernel analyzer is devised to calculate the number of kernels that can be dispatched concurrently. Moreover, to avoid consuming too many CPU threads or process resources, we integrate a runtime scheduler module for kernel launch and a pool-based stream manager for GPU work queue management. While in the inter-layer level, we present a pipeline execution strategy to overlap the processing of workloads from adjacent layers. To determine the number of samples to be processed by a single pipeline stage, the analysis result from the intra-layer module is considered. In the end, we implement a prototype of the proposed framework with Caffe, a well-known deep learning framework and conduct experiments with four off-the-shelf CNN models on three NVIDIA GPUs. Results show that HGP4CNN can be exploited to achieve better performance over the original implementation and keep the convergence property of networks. We can achieve a speedup of up to 6.X for a single convolutional layer and 2.X for multiple layers within pipelines of a network model.

Efficient Road Crack Detection Based on an Adaptive Pixel-Level Segmentation Algorithm

Cracks considerably reduce the life span of pavement surfaces. Currently, there is a need for the development of robust automated distress evaluation systems that comprise a low-cost crack detection method for performing fast and cost-effective roadway health monitoring practices. Most of the current methods are costly and have labor-intensive learning processes, so they are not suitable for small local-level projects with limited resources or are only usable for specific pavement types. This paper proposes a new method that uses an adapted version of the weighted neighborhood pixels segmentation algorithm to detect cracks in 2-D pavement images. The method uses the Gaussian cumulative density function (CDF) as the adaptive threshold to overcome the drawback of fixed thresholds in noisy environments. The proposed algorithm was tested on 300 images containing a wide range of noise representative of various pavement noise conditions. The method proved to be time and cost-efficient as it took less than 3.15 s per 320 × 480 pixels image for a Xeon (R) 3.70 GHz CPU processor to generate the detection results. This makes the proposed method a perfect choice for county-level pavement maintenance projects requiring cost-effective pavement crack detection systems. The validation results were promising for the detection of medium to severe-level cracks (precision = 79.21%, recall = 89.18%, and F1 score = 83.90%).

Approaching DRAM performance by using microsecond-latency flash memory for small-sized random read accesses

For applications in which small-sized random accesses frequently occur for datasets that exceed DRAM capacity, placing the datasets on SSD can result in poor application performance. For the read-intensive case we focus on in this paper, low latency flash memory with microsecond read latency is a promising solution. However, when they are used in large numbers to achieve high IOPS (Input/Output operations Per Second), the CPU processing involved in IO requests is an overhead. To tackle the problem, we propose a new access method combining two approaches: 1) optimizing issuance and completion of the IO requests to reduce the CPU overhead. 2) utilizing many contexts with lightweight context switches by stackless coroutines. These reduce the CPU overhead per request to less than 10 ns, enabling read access with DRAM-like overhead, while the access latency longer than DRAM can be hidden by the context switches. We apply the proposed method to graph algorithms such as BFS (Breadth First Search), which involves many small-sized random read accesses. In our evaluation, the large graph data is placed on microsecond-latency flash memories within prototype boards, and it is accessed by the proposed method. As a result, for the synthetic and real-world graphs, the execution times of the graph algorithms are 88--141% of those when all the data are placed in DRAM.

Efficient activation functions for embedded inference engines

The importance of the choice of the activation function for training and inferencing in machine learning cannot be overemphasized. Activation functions can influence network training convergence, performance accuracy, and can make training and inference stages computationally expensive. We introduce a family of square-based activation functions for embedded devices that consume only one instruction cycle with the potential of being resource efficient when constructed in silicon. We show that the proposed family are computationally efficient when compared with exponential-based non-linearities. The family includes functions for deep neural network architectures, support vector machines, recurrent neural networks, and others. We demonstrate the universal ability of the square-based family of activation functions on a variety of neural network architectures. We analyze the hidden representations of our trained multilayer perceptron network in an attempt to explain the performance gains, and speed-up observed when using square non-linearities. Speed-up was recorded with the quadratic-based kernel transformation on support vector machines. We record higher performance accuracy for recurrent neural network architectures and logistic regression using this family. Speed up was also recorded for implementation on Intel CPU and ARM processors. This family will find particular importance in low-end hardware devices with limited hardware capabilities.

A Comparative Study of the Implementation of SJF and SRT Algorithms on the GPU Processor Using CUDA

GPU (Graphical Processing Units) have become in a few years very powerful tools for parallel computing. They are currently used in several fields such as image processing, bioinformatics, medical applications and numerical computation...etc. Their advantages are faster processing and lower power consumption compared to CPU power. It is simple to program a GPU processor using the CUDA C language to perform tasks that are typically computed in parallel. But you need to understand the different architectural aspects of the GPU. In this paper, we will define and implement the two operating system algorithms the SJF (Shortest Job First) algorithm and the SRT (Shortest Remaining Time) algorithm in a single-wire CPU environment using the C language, and then the same algorithms will be implemented on the GPU using the CUDA C language, in order to compare the different performances of the implementation of the two algorithms on GPU and CPU processors and to verify the efficiency of this study.

Large-scale terrain-adaptive LOD control based on GPU tessellation

The real-time rendering of large-scale terrain scenes has been a challenge and is a popular research topic in the fields of 3D games and virtual reality. To fully utilize GPU features, this paper proposes a real-time rendering algorithm for large-scale regular grid terrain based on GPU Tessellation. The CPU processes a coarse-grained quadtree to generate terrain patches and then passes the patches to the GPU after view culling. Then, the GPU refines the terrain by using GPU Tessellation and displacement mapping. The most important advantage of our method is that during the tessellation stage, a new rule that the distance, screen space projection error and variance of the height, as the standard of terrain roughness, is designed. During the tessellation stage, the distance, screen space projection error and variance of the height, as the standard of terrain roughness, are considered. The experimental results show that our algorithm can greatly reduce the CPU processing time and main memory space requirement, and fully utilize the new features of the GPU; In conclusion, the proposed approach can render large-scale terrain with high-precision in real-time.

Fusion Chain: A Decentralized Lightweight Blockchain for IoT Security and Privacy

As the use of internet of things (IoT) devices increases, the importance of security has increased, because personal and private data such as biometrics, images, photos, and voices can be collected. However, there is a possibility of data leakage or manipulation by monopolizing the authority of the data, since such data are stored in a central server by the centralized structure of IoT devices. Furthermore, such a structure has a potential security problem, caused by an attack on the server due to single point vulnerability. Blockchain’s, through their decentralized structure, effectively solve the single point vulnerability, and their consensus algorithm allows network participants to verify data without any monopolizing. Therefore, blockchain technology becomes an effective solution for solving the security problem of the IoT’s centralized method. However, current blockchain technology is not suitable for IoT devices. Blockchain technology requires large storage space for the endless append-only block storing, and high CPU processing power for performing consensus algorithms, while its opened block access policy exposes private data to the public. In this paper, we propose a decentralized lightweight blockchain, named Fusion Chain, to support IoT devices. First, it solves the storage size issue of the blockchain by using the interplanetary file system (IPFS). Second, it does not require high computational power by using the practical Byzantine fault tolerance (PBFT) consensus algorithm. Third, data privacy is ensured by allowing only authorized users to access data through public key encryption using PKI. Fusion Chain was implemented from scratch written using Node.js and golang. The results show that the proposed Fusion Chain is suitable for IoT devices. According to our experiments, the size of the blockchain dramatically decreased, and only 6% of CPU on an ARM core, and 49 MB of memory, is used on average for the consensus process. It also effectively protects privacy data by using a public key infrastructure (PKI).