Photomask Cost Research Articles

Mask-less Laser Direct Imaging & Adaptive Patterning for Fan-Out Heterogeneous Integration

Mask-less Laser Direct Imaging & Adaptive Patterning for Fan-Out Heterogeneous Integration

Optical head alignment method using serial manipulators for maskless lithography system

As the cost of photomasks for lithography processes becomes prohibitive especially for large size panel displays, researchers have been developing maskless alternatives using various physical wave sources. Despite the prominent overall manufacturing cost reduction benefit, the maskless lithography system has drawbacks in some respects. These issues include productivity, size of the system, and lithography hardware cost efficiency. One of the well accepted solutions is massive parallel exposure using multioptical heads. In order to implement the multi heads option, securing accurate alignment of the heads is essential. In this paper, an alignment algorithm of a spot array manipulated with serial mechanism is suggested. The suggested method enables to reduce the overall error using the genetic algorithm. Defining spot array error as fitness function of the algorithm is introduced. And correlation with kinematics of the optical system and spot array error will be represented. In addition, 4 DOF serial manipulator design and its kinematic analysis is presented. Finally, the developed system is tested and evaluated. The suggested algorithm allows spot array error to be reduced about 80 % with regards to random error. This paper contributes to accurate alignment of the heads by suggesting an alignment algorithm of a spot array manipulated with a serial mechanism.

Femtosecond laser lithography technique for submicron <inline-formula><math display="inline" overflow="scroll"><mrow><mi>T</mi></mrow></math></inline-formula>-gate fabrication on positive photoresist

Yan-Dong DuWei-Hua HanWei YanXiao-Na XuYan-Bo ZhangXiao-dong WangFu-Hua YangChinese Academy of SciencesInstitute of SemiconductorsEngineering Research Center for SemiconductorIntegrated TechnologyBeijing 100083, ChinaE-mail: weihua@semi.ac.cnHong-Zhong CaoFeng JinXian-Zi DongZhen-Sheng ZhaoXuan-Ming DuanChinese Academy of SciencesTechnical Institute of Physics and ChemistryLaboratory of Organic NanoPhotonics and keyLaboratory of Functional Crystals and LaserTechnologyBeijing 100080, ChinaYang LiuSun Yat-sen UniversitySchool of Physics and EngineeringXin-Guang-Xi Road 135Guangzhou 510275, ChinaAbstract. Femtosecond lasers have been found suitable for masklessphotolithographywithsubmicronresolution,whichisveryattractiveforsol-ving the problem of high photomask cost. Direct femtosecond laser writingof lithographic patterns is reported with submicron feature width on thinpositive photoresist film. We use a scanning electron microscope toinvestigate the feature sizes of femtosecond laser lithography, whichare determined by the incident laser power, the number of scan timesand the substrate materials. Submicron T-shaped gates have beenfabricated using a two-step process of femtosecond laser lithographywhere the gate foot and head can be separately defined on positiveAZ4620 photoresist film. This work has led to the stable fabrication ofsub-300 nm T-gates on the samples of GaN on sapphire substrate andAlGaN/GaN on Si substrate.

ECOS: Stable Matching Based Metal-Only ECO Synthesis

To ease the time-to-market pressure and save the photomask cost, metal-only ECO realizes the last-minute design changes by revising the photomasks of metal layers only. This task is challenging because the pre-injected spare cells are limited in number and in cell types. Metal-only ECO has to implement these functional and/or timing changes using available spare cells. In this paper, we propose a stable matching based metal-only ECO synthesizer, named ECOS, that can implement the incremental design changes correctly without sacrificing timing and routability. The experiments are conducted on nine industrial testcases. These testcases reflect the real difficulties faced by designers and our results show that ECOS is promising for all of them.

A Metal-Only-ECO Solver for Input-Slew and Output-Loading Violations

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> To reduce the time-to-market and photomask cost for advanced process technologies, metal-only economic cooperation organization (ECO) has become a practical and attractive solution to handle incremental design changes. Due to limited spare cells in metal-only ECO, the new added netlist may often violate the input-slew and output-loading constraints and, in turn, delay or even fail the timing closure. This paper presents a framework, named metal-only ECO slew/cap solver (MOESS), to resolve the input-slew and output-loading violations by connecting spare cells onto the violated nets as buffers. MOESS performs two buffer-insertion schemes in a sequential manner to first minimize the number of inserted buffers and then resolve timing violations, if any. The experimental results based on industrial designs demonstrate that MOESS can resolve more violations with fewer inserted buffers and less central processing unit runtime compared to an electronic design automation vendor's solution. </para>

Direct femtosecond laser lithography for photoresist patterning

Development of maskless lithography techniques may solve the problem of photomask cost. Furthermore, it could open a market for small-scale manufacturing applications. Since femtosecond lasers have been found suitable for processing of a wide range of materials with submicrometer resolution, it is attractive to use this technique for maskless lithography. In this paper, we report direct laser writing of lithographic patterns with submicron feature width on thin photoresist film by a femtosecond laser. The patterns were analyzed with a scanning electron microscope. The effects of laser energy and number of pulses on the feature size were investigated. Finally, we present various results on submicron photoresist patterning, which show great potential for future application.

Regular Fabric of Via Programmable Logic Device Using EXclusive-or Array (VPEX) for EB Direct Writing

The photo-mask cost of standard-cell-based ASICs has been increased so prohibitively that low-volume production LSIs are difficult to fabricate due to high non-recurring engineering (NRE) cost including mask cost. Recently, user-programmable devices, such as FPGAs are started to be used for low-volume consumer products. However, FPGAs cannot be replaced for general purpose because of its lower speed-performance and higher power consumption. In this paper, we propose the user-programmable architecture called VPEX (Via Programmable logic device using EXclusive-or array), in which the hardware logic can be programmed by changing layout patterns on 2 via-layers. The logic element (LE) of VPEX consists of complex-gate-type EXclusive OR (EXOR) and Inverter (NOT) gates. The single LE can output 12 logics which include NOT, Buffer (BUF), all 2-inputs logic functions, 3-inputs AOI21 and inverted-output multiplexer (MUXI) by changing via-1 layout pattern. Furthermore, via-1 layout is optimized for high-throughput EB direct writing, so mask-less programming will be realized in VPEX. We compared the performance of area, speed, and power consumption of VPEX with that of standard-cell-based ASICs and FPGAs. As a result, the speed performance of VPEX was much better than FPGAs and about 1.3-1.6 times worse than standard-cells. We believe that the combination of VPEX architecture and EB direct writing is the best solution for low-volume production LSIs.

Wire Sizing and Spacing for Lithographic Printability and Timing Optimization

As the VLSI feature size has already decreased below lithographic wavelength, the printability problem, due to strong diffraction effects, poses a serious threat to the progress of VLSI technology. A circuit layout with poor printability implies that it is difficult to make the printed features on wafers follow designed shapes without distortions. The development of resolution enhancement techniques (RET) can alleviate the printability problem but cannot reverse the trend of deterioration. Moreover, over-usage of RET may dramatically increase photo-mask cost and increase the cycle time for volume production. Thus, there is a strong demand to consider the subwavelength printability problem in circuit layout designs. However, layout printability optimization should not degrade circuit timing performance. In this paper, we introduce a wire sizing and spacing method to improve wire printability with minimal adverse impact on interconnect timing performance. A new printability model is proposed to handle partially coherent illuminations. The complex printability and timing optimization problem is solved in a two-phase approach. The difficulty of the printability optimization due to its multimodal nature is handled with a sensitivity-based heuristic. A coupling aware timing driven continuous wire sizing algorithm is also provided. Lithographic simulation results show that our approach can improve the printability in term of edge placement error (EPE) by 20%-40% without violating timing, wire width, and spacing constraints.

Maskless nonlinear lithography with femtosecond laser pulses

Development of maskless lithography techniques can provide a potential solution for the photomask cost issue. Furthermore, it could open a market for small-scale manufacturing applications. Since femtosecond lasers have been found suitable for processing of a wide range of materials with sub-micrometer resolution – whereas the limit of achievable structure sizes is predicted to be below 100 nm – it is attractive to use this technique for maskless lithography. In this paper, we present the first results on super-resolution femtosecond laser lithography, which show great potential for future applications.

Maskless lithography

The high and rising cost of photomasks (largely driven by writing times exceeding 24 h) is driving the exploration of maskless lithography for applications requiring throughput about 1 cm 2/s which is about one tenth that of an optical projection exposure system. Achieving this throughput with charged particle lithography requires currents 10,000 times larger than those presently used and hence sets up the need for charged particle optics radically different from those being used today. Achieving this throughput with optical maskless lithography at the required minimum features sizes of 65 nm and below is a serious engineering challenge for the spatial light modulator. Meeting 10% or even 1% of the throughput requirement might still result in mask writing and inspection technologies that would lead to significantly less expensive masks. Furthermore, relaxing the requirements on control of individual edge positions (i.e., a fixed-shape projector) would significantly ease the above challenges.

Optimization of sub-100-nm designs for mask cost reduction

For sub-100 nm integrated circuit (IC) technologies, many of the factors that affect the cost of photomasks, the cost of material, of the writing process, of the develop/etch process, and of inspection, are increasing by an order of magnitude per generation. In order to mitigate the impact of that increase on the return on investment of new IC products, mask shop deliverables such as yield or alignment with technology requirements need to reach new quality. This work focuses on cost containment of the mask by optimally utilizing existing reticle technology to meet device requirements at the product level. We first compare the increase of mask cost with that of other manufacturing equipment categories, and discuss their dependence on layer properties and how to control increasing costs. We then propose use of a new procedure called integrated simulation (optical combined with electrical) to estimate the impact of the mask critical dimension (CD) budget on transistor performance on the local scale (cell level) and global scale (die level). In the process, at the cell level, simulated aerial images of metal-oxide-semiconductor field-effect transistor channels are used to evaluate the parametric data dependence on the optical proximity effects and correction features at the mask grade assumed. At the die level, statistical distribution of device parameters in the die is derived to estimate the parametric yield impacted by mask CD variation. We also discuss how integrated simulation can help in resolving other challenges of advanced reticle manufacturing such as qualification of masks or the generation of dummy patterns.