Terms Of Hardware Cost Research Articles

Multiplierless Multiple-Stage Cascaded FIR Filter Design

It is well known that multiplierless finite impulse response (FIR) filters in multiple-stage cascade form can achieve lower hardware cost and lower coefficient sensitivity than that of single stage design. In this work, a novel algorithm is proposed for the design of multiplierless multiple-stage cascaded FIR filters. Unlike to the conventional algorithms in which the number of stages is fixed and usually is fixed to two, the number of stage in the proposed algorithm is automatically determined. The design examples show that the proposed algorithm significantly outperforms the best existing algorithm in terms of hardware cost and the design time is also saved.

An approach for FIR filter coefficient optimization using differential evolution algorithm

In this paper, we present a hardware efficient finite impulse response (FIR) filter design using differential evolution (DE) and common sub expression (CSE) elimination algorithm. With the DE algorithm, we first found a set of filter coefficients with reduced number of signed-power-of-two (SPT) terms without compromising on quality of the filter response. After obtaining coefficients, we applied CSE elimination algorithm, and determined the hardware cost in terms of adders. The filters were designed using DE for various word lengths, and the same were implemented in transposed direct form (TDF) structure. The implemented filters were synthesized in Cadence RTL compiler using UMC 90nm technology. We compared the performances of our filters with recently best published works in terms of area, delay, power and power-delay-product (PDP). One of the proposed filters found to improve a PDP gain of 29% compared to Remez algorithm. The proposed approach showed improvements in filter design for the given specifications.

WCET analysis with MRU cache

Most previous work on cache analysis for WCET estimation assumes a particular replacement policy called LRU. In contrast, much less work has been done for non-LRU policies, since they are generally considered to be very unpredictable. However, most commercial processors are actually equipped with these non-LRU policies, since they are more efficient in terms of hardware cost, power consumption and thermal output, while still maintaining almost as good average-case performance as LRU. In this work, we study the analysis of MRU, a non-LRU replacement policy employed in mainstream processor architectures like Intel Nehalem. Our work shows that the predictability of MRU has been significantly underestimated before, mainly because the existing cache analysis techniques and metrics do not match MRU well. As our main technical contribution, we propose a new cache hit/miss classification, k -Miss, to better capture the MRU behavior, and develop formal conditions and efficient techniques to decide k -Miss memory accesses. A remarkable feature of our analysis is that the k -Miss classifications under MRU are derived by the analysis result of the same program under LRU. Therefore, our approach inherits the advantages in efficiency and precision of the state-of-the-art LRU analysis techniques based on abstract interpretation. Experiments with instruction caches show that our proposed MRU analysis has both good precision and high efficiency, and the obtained estimated WCET is rather close to (typically 1%∼8% more than) that obtained by the state-of-the-art LRU analysis, which indicates that MRU is also a good candidate for cache replacement policies in real-time systems.

Role of thermal intensity on operational characteristics of ultra-low emission colorless distributed combustion

This paper examines the development of ultra-low emission colorless distributed combustion (CDC) for gas turbines, operating at thermal intensity in the range of 5–453MW/m3atm. Higher thermal intensity combustors are desirable for increased performance with minimal increase in hardware costs in terms of both weight and volume of gas turbine combustors. Most land based gas turbine combustors operate at thermal intensity of about 15MW/m3atm but operation at higher intensity can provide increased performance. Design of high thermal intensity CDC combustor requires control of critical parameters, such as gas recirculation, fuel/oxidizer mixing, air preheats, and residence time distribution characteristics via proper selection of different air and fuel injection configurations to achieve desirable combustion characteristics. Initially, various flow field configurations were investigated at a low thermal intensity of 5MW/m3atm. This effort was followed by investigations at higher thermal intensity ranges of 20–40MW/m3atm by reducing the combustor volume for a forward flow configuration under more favorable novel non-premixed conditions. Further investigations were performed for a simpler combustor having single injection ports for air and fuel with detailed investigation of various flow field configurations performed at a thermal intensity of 28MW/m3atm. Further reduction in combustion volume resulted in thermal intensity of 57MW/m3atm. For the flow configurations investigated, reverse cross-flow configuration was found to give more favorable results with air injected from exit end and fuel injected in a cross-flow direction to the air flow. This reverse cross-flow geometry was investigated in detail by further reducing the combustor volume. Air injection diameter was increased to reduce the pressure drop across the combustor. The combustor was investigated at thermal intensity in the range of 53–85MW/m3atm. This geometry resulted in 4ppm NO emission and CO emissions of about 27ppm under novel non-premixed flow conditions at thermal intensity of 53MW/m3atm. The pressure drop at this operational point was less than 5% to meet the conventional combustor requirements. Further reduction in combustor volume resulted in very high thermal intensity in the range of 156–198MW/m3atm and at the most desirable operational point NO and CO emissions were 8ppm and 82ppm, respectively under novel non-premixed mode at a thermal intensity of 170MW/m3atm. Even further reduction in combustor volume resulted in combustor operation at ultra-high thermal intensity of 283–453MW/m3atm and at the desirable operating point the NO and CO emissions were 4ppm and 115ppm respectively at a thermal intensity of 340MW/m3atm. The sequential efforts reveal the possibility of significantly increasing the thermal intensity while still achieving desirable emission levels.

FPGA-based embedded Linux technology in fusion: The MAST microwave imaging system

A cutting-edge standalone data acquisition system has been developed using Field Programmable Gate Arrays (FPGAs). It has 16 ADC channels operating at 250 MSPS, at 14-bit resolution acquiring continuously at 8GB/s for 0.5s. The system uses the Virtex 6 FPGA running embedded Linux on the MicroBlazeTM soft processor. We propose the development of a standard FPGA architecture, based on a methodology which has enabled us to develop this system using commercial-off-the-shelf (COTS) components. This architecture can easily be modified for a variety of applications, both high and low performance at a competitive cost in terms of hardware, engineering and development.

DAPSCO

Many-core tiled CMP proposals often assume a partially shared last level cache (LLC) since this provides a good compromise between access latency and cache utilization. In this paper, we propose a novel way to map memory addresses to LLC banks that takes into account the average distance between the banks and the tiles that access them. Contrary to traditional approaches, our mapping does not group the tiles in clusters within which all the cores access the same bank for the same addresses. Instead, two neighboring cores access different sets of banks minimizing the average distance travelled by the cache requests. Results for a 64-core CMP show that our proposal improves both execution time and the energy consumed by the network by 13% when compared to a traditional mapping. Moreover, our proposal comes at a negligible cost in terms of hardware and its benefits in both energy and execution time increase with the number of cores.

Optimization and implementation of scaling-free CORDIC-based direct digital frequency synthesizer for body care area network systems.

Coordinate rotation digital computer (CORDIC) is an efficient algorithm for computations of trigonometric functions. Scaling-free-CORDIC is one of the famous CORDIC implementations with advantages of speed and area. In this paper, a novel direct digital frequency synthesizer (DDFS) based on scaling-free CORDIC is presented. The proposed multiplier-less architecture with small ROM and pipeline data path has advantages of high data rate, high precision, high performance, and less hardware cost. The design procedure with performance and hardware analysis for optimization has also been given. It is verified by Matlab simulations and then implemented with field programmable gate array (FPGA) by Verilog. The spurious-free dynamic range (SFDR) is over 86.85 dBc, and the signal-to-noise ratio (SNR) is more than 81.12 dB. The scaling-free CORDIC-based architecture is suitable for VLSI implementations for the DDFS applications in terms of hardware cost, power consumption, SNR, and SFDR. The proposed DDFS is very suitable for medical instruments and body care area network systems.

Low power architecture design and hardware implementations of deblocking filter in H.264/AVC

An adaptive in-loop deblocking filter (DF) is standardized in H.264/AVC to reduce blocking artifacts and improve compression efficiency. This paper proposes a low power DF architecture with hybrid and intelligent edge skip filtering order. We further adopt a four-stage pipeline to boost the speed of DF process and the proposed Horizontal Edge Skip Processing Architecture (HESPA) offers an edge skip aware mechanism for filtering the horizontal edges that not only reduces power consumption but also reduces the filtering processes down to 100 clock cycles per macroblock (MB). In addition, the architecture utilizes the buffers efficiently to store the temporary data without affecting the standarddefined data dependency by a reasonable strategy of edge filtering order to enhance the reusability of the intermediate data. The system throughput can then be improved and the power consumption can also be reduced. Simulation results show that more than 34% of logic power measured in FPGA can be saved when the proposed HESPA is enabled. Furthermore, the proposed architecture is implemented on a 0.18μm standard cell library, which consumes 19.8K gates at a clock frequency of 200 MHz, which compares competitively with other state-of-the-art works in terms of hardware cost.

Low Complexity and Fast Computation for Recursive MDCT and IMDCT Algorithms

Fast algorithms are derived for modified discrete cosine transform (MDCT) and inverse MDCT (IMDCT) in this brief. The proposed algorithms based on type II discrete cosine transform and type II discrete sine transform not only adopt a unified architecture for both MDCT and IMDCT computations but also take only N/8 + 1 computational cycles for each output sequence. Compared with previous IMDCT approaches, the number of preprocessing multiplications of the proposed IMDCT algorithm is reduced by 87.5%. In addition, the coefficient requirements for preprocessing in the proposed IMDCT algorithm can be reduced by 50%, and the number of multiplications for the recursive kernel is greatly decreased by up to 87.5%. The proposed algorithms in terms of hardware costs take two fewer multipliers and six fewer adders than some well-known recursive algorithms. Therefore, the proposed architecture is better suited for various audio codecs.

Upper Bound on Blocking Probability for Vertically Stacked Optical Banyan Networks with Link Failures and Given Crosstalk Constraint

Vertical stacking of multiple copies of an optical banyan network is a novel scheme for building nonblocking optical switching networks. The resulting network, namely vertically stacked optical banyan (VSOB) network, preserves all the properties of the banyan network, but increases the hardware cost significantly under first order crosstalk-free constraint. However, stringent crosstalk constraint may not always be necessary. Considering the fact that some designer may want to compromise the blocking probability and crosstalk constraint to a certain degree with the hardware cost, blocking behaviour of such VSOB networks have been analyzed to studying network performance and finding a graceful compromise between hardware costs and blocking probability under or without crosstalk constraint. In this paper, we present the simulation results for upper bound on blocking probability of VSOB networks with link failures and given degree of crosstalk constraint. We show how crosstalk adds a new dimension to the performance analysis on a VSOB networks. The simulation results presented in this paper can guide network designer in finding the trade-off among the blocking probability, the degree of crosstalk and the hardware cost in terms of vertical copies of banyan network in the presence of link failures.Keywords: Banyan networks; Blocking probability; Vertical stacking; Link-failures; Crosstalk.© 2009 JSR Publications. ISSN: 2070-0237 (Print); 2070-0245 (Online). All rights reserved.DOI: 10.3329/jsr.v1i3.1191 J. Sci. Res. 1 (3), 484-494 (2009)

Optimization of Linear Phase FIR Filters in Dynamically Expanding Subexpression Space

The most advanced techniques in the design of multiplierless finite impulse response (FIR) filters explore common subexpression sharing when the filter coefficients are optimized. Existing techniques, however, either suffer from a heavy computational overhead, or have no guarantees on the minimal hardware cost in terms of the number of adders. A recent technique capable of designing long filters optimizes filter coefficients in pre-specified subexpression spaces. The pre-specified subexpression spaces determine if a filter with fewer adders may be achieved. Unfortunately, there is no known technique that can find subexpression spaces that can guarantee the solution with the minimum number of adders in the implementation. In this paper, a tree search algorithm is proposed to update and expand the subexpression spaces dynamically, and thus, to achieve the maximum subexpression sharing during the optimization. Numerical examples show that the proposed algorithm generates filters using fewer adders than other non-optimum algorithms. On the other hand, as a consequence of its efficiency, our proposed technique is able to design longer filters than the global optimum algorithm.

A Novel High Performance Architecture for H.264/AVC Deblocking Filtering

This letter presents an architecture based on a new double-filter strategy to perform the adaptive in-loop filtering process specified by the H.264/AVC standard. The proposed architecture shows considerable advantages, both in terms of hardware cost and latency, when compared with the approaches found in the most recent literature.

Implementation of Wireless Communications Systems on FPGA-Based Platforms

Wireless communications are a very popular application domain. The efficient implementation of their components (access points and mobile terminals/network interface cards) in terms of hardware cost and design time is of great importance. This paper describes the design and implementation of the HIPERLAN/2 WLAN system on a platform including general purpose microprocessors and FPGAs. Detailed implementation results (performance, code size, and FPGA resources utilization) are presented. The main goal of the design case presented is to provide insight into the design aspects of a complex system based on FPGAs. The results prove that an implementation based on microprocessors and FPGAs is adequate for the access point part of the system where the expected volumes are rather small. At the same time, such an implementation serves as a prototyping of an integrated implementation (System-on-Chip), which is necessary for the mobile terminals of a HIPERLAN/2 system. Finally, firmware upgrades were developed allowing the implementation of an outdoor wireless communication system on the same platform.

Energy-Efficient Channel Estimation in MIMO Systems

The emergence of MIMO communications systems as practical high-data-rate wireless communications systems has created several technical challenges to be met. On the one hand, there is potential for enhancing system performance in terms of capacity and diversity. On the other hand, the presence of multiple transceivers at both ends has created additional cost in terms of hardware and energy consumption. For coherent detection as well as to do optimization such as water filling and beamforming, it is essential that the MIMO channel is known. However, due to the presence of multiple transceivers at both the transmitter and receiver, the channel estimation problem is more complicated and costly compared to a SISO system. Several solutions have been proposed to minimize the computational cost, and hence the energy spent in channel estimation of MIMO systems. We present a novel method of minimizing the overall energy consumption. Unlike existing methods, we consider the energy spent during the channel estimation phase which includes transmission of training symbols, storage of those symbols at the receiver, and also channel estimation at the receiver. We develop a model that is independent of the hardware or software used for channel estimation, and use a divide-and-conquer strategy to minimize the overall energy consumption.

Performance modeling for all-optical photonic switches based on the vertical stacking of banyan network structures

The scheme of vertical stacking has caught much interest in the design of ultra high-speed communication switches for the past a few years. In particular, the scheme can greatly facilitate the effort of constructing all-optical photonic switches in the event that a banyan network structure is adopted. A vertically stacked photonic banyan (VSPB) network can preserve the good properties of the banyan network structures, such as the small depth and absolute loss uniformity; on the other hand, it introduces a significant increase in the hardware cost. Extensive research efforts have been addressed in determining the minimum number of stacked copies (planes) required for a nonblocking VSPB network. However, very few of them focused on the performance of the VSPB networks in terms of blocking probability. Therefore, in this paper, we study the blocking behavior of the VSPB networks and propose a corresponding analytical model under the random routing strategy. The proposed analytical model is designed to fully explore the property of symmetry in banyan network structures, and can calculate the blocking probability of a VSPB network stage by stage in a recursive manner such that the combinatorial explosion problem is avoided. To verify the proposed model, we conduct extensive simulations, in which the results indicate that our model can accurately describe the blocking behavior of VSPB networks under the random routing strategy and it agrees with the conditions of strictly nonblocking VSPB networks. We find that the proposed analytical model can deeply investigate into the inherent relationship between blocking probability and network hardware cost in terms of the number of planes; as a result, a quantitative guidance for initiating a graceful compromise between blocking probability and hardware cost can be developed based on the analytical model. Our analysis results also show that the hardware cost of a VSPB network can be dramatically reduced by simply allowing a negligible nonzero blocking probability in most of the practical cases. This fact will solidly contribute to the network switch architecture design and enable more practical applications of VSPB networks.

Designing WDM optical interconnects with full connectivity by using limited wavelength conversion

Optical communication, in particular, wavelength-division-multiplexing (WDM) technique, has become a promising networking choice to meet ever-increasing demands on bandwidth from emerging bandwidth-intensive computing/networking applications. A major challenge in designing WDM optical interconnects is how to provide maximum connectivity while keeping minimum hardware cost. The overall hardware cost of a WDM optical interconnect includes not only the cost of switching elements, but also the cost of wavelength conversion. Previous work mainly focused on minimizing hardware cost without taking into consideration the type of wavelength converters used. In this paper, we design WDM optical interconnects with full connectivity by using the low cost limited wavelength converters. We present optimal WDM optical interconnects for both permutation and multicast in single stage and multistage implementations. We also discuss the impact of the relationship between the number of fibers and the number of wavelengths per fiber on the optimal design. As can be seen, the newly designed WDM optical interconnects have minimum hardware cost in terms of the number of crosspoints and wavelength conversion cost.

Blocking behaviors of crosstalk-free optical banyan networks on vertical stacking

Banyan networks are attractive for constructing directional coupler (DC)-based optical switching networks for their small depth and self-routing capability. Crosstalk between optical signals passing through the same DC is an intrinsic drawback in DC-based optical networks. Vertical stacking of multiple copies of an optical banyan network is a novel scheme for building nonblocking (crosstalk-free) optical switching networks. The resulting network, namely vertically stacked optical banyan (VSOB) network, preserves all the properties of the banyan network, but increases the hardware cost significantly. Though much work has been done for determining the minimum number of stacked copies (planes) required for a nonblocking VSOB network, little is known on analyzing the blocking probabilities of VSOB networks that do not meet the nonblocking condition (i.e., with fewer stacked copies than required by the nonblocking condition). In this paper, we analyze the blocking probabilities of VSOB networks and develop their upper and lower bounds with respect to the number of planes in the networks. These bounds depict accurately the overall blocking behaviors of VSOB networks and agree with the conditions of strictly nonblocking and rearrangeably nonblocking VSOB networks respectively. Extensive simulation on a network simulator with both random routing and packing strategy has shown that the blocking probabilities of both strategies fall nicely within our bounds, and the blocking probability of packing strategy actually matches the lower bound. The proposed bounds are significant because they reveal the inherent relationships between blocking probability and network hardware cost in terms of the number of planes, and provide network developers a quantitative guidance to trade blocking probability for hardware cost. In particular, our bounds provide network designers an effective tool to estimate the minimum and maximum blocking probabilities of VSOB networks in which different routing strategies may be applied. An interesting conclusion drawn from our work that has practical applications is that the hardware cost of a VSOB network can be reduced dramatically if a predictable and almost negligible nonzero blocking probability is allowed.

Run-length coding extensions for high performance hardware data compression

The optimal placement of a run-length coding extension to a dictionary-based lossless data compression algorithm is investigated. A hardware implementation of the proposed extension is completed and integrated into an existing design. The new hardware is benchmarked against commercially available software and hardware compression methods. Run-length coding replaces repetitive, identical sequences of a symbol with a pair formed by a code indicating the repeating symbol plus a code indicating the length or number of repetitions that occurred. This method of coding is of limited use for general compression due to its relatively poor performance. However, good results can be achieved when used as an extension to a general lossless data compression algorithm where it can improve compression, targeting the coding of repetitive data formats such as zeroes in memory or fax pages or a uniform colour in image backgrounds. It is shown that the run-length coding method can be extended to support more complex repeating patterns with little extra cost in terms of hardware or speed but providing significant superior compression performance.

A new conference network for group communication

A conference refers to a group of members in a network which communicate with each other within the group. In this paper, we propose a novel design for a conference network which supports multiple disjoint conferences. The major component of the network is a multistage network composed of switch modules with fan-in and fan-out capability. A fast self-routing algorithm is developed for setting up routing paths in the conference network. For an n/spl times/n conference network we design, the hardware cost is O(n log n), and the routing time and communication delay vary from O(1) to O(log n) depending on where the conference is allocated in the network. As can be seen, the new conference network is superior to existing designs in terms of hardware cost, routing time and communication delay. The conference network proposed is rearrangeable nonblocking in general, and is strictly nonblocking under some conference service policy. It can be used in applications that require efficient or real-time group communication.

ATPG for combinational circuits on configurable hardware

In this paper, a new approach for generating test vectors that detects faults in combinational circuits is introduced. The approach is based on automatically designing a circuit which implements the D-algorithm, an automatic test pattern generation (ATPG) algorithm, specialized for the combinational circuit. Our approach exploits fine-grain parallelism by performing the following in three clock cycles: direct backward/forward implications, conflict checking, selecting next gate to propagate fault or to justify a line, decisions on gate inputs, and loading the state of the circuit after backup. In this paper, we show the feasibility of this approach in terms of hardware cost and speed and how it compares with software-based techniques.