Abstract

Coordinate rotation digital computer (CORDIC) is an efficient algorithm for computations of trigonometric functions. Scaling-free-CORDIC is one of the famous CORDIC implementations with advantages of speed and area. In this paper, a novel direct digital frequency synthesizer (DDFS) based on scaling-free CORDIC is presented. The proposed multiplier-less architecture with small ROM and pipeline data path has advantages of high data rate, high precision, high performance, and less hardware cost. The design procedure with performance and hardware analysis for optimization has also been given. It is verified by Matlab simulations and then implemented with field programmable gate array (FPGA) by Verilog. The spurious-free dynamic range (SFDR) is over 86.85 dBc, and the signal-to-noise ratio (SNR) is more than 81.12 dB. The scaling-free CORDIC-based architecture is suitable for VLSI implementations for the DDFS applications in terms of hardware cost, power consumption, SNR, and SFDR. The proposed DDFS is very suitable for medical instruments and body care area network systems.

Highlights

  • Direct digital frequency synthesizer (DDFS) has been widely used in the modern communication systems

  • direct digital frequency synthesizer (DDFS) is preferable to the classical phase-locked-loop- (PLL-) based synthesizer in terms of switching speed, frequency resolution, and phase noise, which are beneficial to the high-performance communication systems

  • Let the output resolution be of 16 bits, for the sine/cosine generator consisting of a cascade of w processors, each of which performs the sub-rotation by a fixed angle of 2−i radian as follows: x(i + 1) = 1 − σ(i)2−(2i+1) x(i) + σ(i)2−i y(i), (14)

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Summary

Introduction

Direct digital frequency synthesizer (DDFS) has been widely used in the modern communication systems. The sine/cosine generator is implemented digitally, and followed by digital-to-analog conversion and low-pass filtering for analogue outputs. Such systems can be applied in many fields, especially in industrial, biological, and medical applications [2,3,4]. A novel DDFS architecture based on the scaling-free CORDIC algorithm [34] with ROM mapping is presented.

The CORDIC Algorithm
Design and Optimization of the Scaling-Free CORDIC-Based DDFS Architecture
16 CORDIC processor B array
Hardware Implementation of the Scaling-Free CORDIC-Based DDFS
Findings
Conclusion
Full Text
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