Cortex M3 Research Articles

Timing Speculation With Optimal In Situ Monitoring Placement and Within-Cycle Error Prevention

In this paper, a timing speculation technique with low-overhead in situ delay monitors placed along critical paths is presented. The proposed insertion of monitors enables timing error prevention within the same clock cycle. Compared to other techniques, the design cost per monitor in our technique is low because no additional gates for the guard banding, inspection window generation, and short path extension are required. We benchmarked our approach on an ARM Cortex M0. The insertion strategy reduces the number of monitors by up to $\sim 23\times $ , power by $\sim 5.5\times $ , and area by $\sim 2.8\times $ compared to the traditional in situ monitoring techniques that insert monitors at the flip-flops. The timing error correction uses a global clock stretching unit to prevent errors within one cycle. With the proposed error prevention technique, ~22% more delay variation is tolerated with a negligible energy overhead of less than ~1%.

CAD-Base

Fabless semiconductor companies design system-on-chips (SoC) by using third-party intellectual property (IP) cores and fabricate them in offshore, potentially untrustworthy foundries. Owing to the globally distributed electronics supply chain, security has emerged as a serious concern. In this article, we explore electronics computer-aided design (CAD) software as a threat vector that can be exploited to introduce vulnerabilities into the SoC. We show that all electronics CAD tools—high-level synthesis, logic synthesis, physical design, verification, test, and post-silicon validation—are potential threat vectors to different degrees. We have demonstrated CAD-based attacks on several benchmarks, including the commercial ARM Cortex M0 processor [1].

AuCPace: Efficient verifier-based PAKE protocol tailored for the IIoT

Increasingly connectivity becomes integrated in products and devices that previously operated in a stand-alone setting. This observation holds for many consumer applications in the so-called "Internet of Things" (IoT) as well as for corresponding industry applications (IIoT), such as industrial process sensors. Often the only practicable means for authentication of human users is a password. The security of password-based authentication schemes frequently forms the weakest point of the security infrastructure. In this paper we first explain why a tailored protocol designed for the IIoT use case is considered necessary. The differences between IIoT and the conventional Internet use-cases result in largely modified threats and require special procedures for allowing both, convenient and secure use in the highly constrained industrial setting. Specifically the use of a verifier-based password-authenticated key-exchange (V-PAKE) protocol as a hedge against public-key-infrastructure (PKI) failures is considered important. Availability concerns for the case of failures of (part of) the communication infrastructure makes local storage of access credentials mandatory. The larger threat of physical attacks makes it important to use memory-hard password hashing. This paper presents a corresponding tailored protocol, AuCPace, together with a security proof within the Universal Composability (UC) framework considering fully adaptive adversaries. We also introduce a new security notion of partially augmented PAKE that provides specific performance advantages and makes them suitable for a larger set of IIoT applications. We also present an actual instantiation of our protocol, AuCPace25519, and present performance results on ARM Cortex-M0 and Cortex-M4 microcontrollers. Our implementation realizes new speed-records for PAKE and X25519 Diffie-Hellman for the ARM Cortex M4 architecture.

Instruction Level Energy Consumption Estimation of Embedded Processor

Embedded systems are portable battery powered devices that have limited power resource. Hence, most of embedded systems need to meet energy constraint. Performance and energy consumption are the most important metrics for embedded system design. Estimation of performance, energy utilization and its validation are essential for embedded system design. Attempt has been made to precisely measure software energy consumption by three methods on ARM Cortex M4 processor. The results are validated with five benchmark programs. Tedious calculation of inter instruction cost has been minimized by taking it as certain percent of total energy. Percentage error between actual and estimated energy is found to be less than 5%.

Instruction Level Energy Consumption Estimation of Embedded Processor

Embedded systems are portable battery powered devices that have limited power resource. Hence, most of embedded systems need to meet energy constraint. Performance and energy consumption are the most important metrics for embedded system design. Estimation of performance, energy utilization and its validation are essential for embedded system design. Attempt has been made to precisely measure software energy consumption by three methods on ARM Cortex M4 processor. The results are validated with five benchmark programs. Tedious calculation of inter instruction cost has been minimized by taking it as certain percent of total energy. Percentage error between actual and estimated energy is found to be less than 5%.

An IMU-based traffic and road condition monitoring system

Abstract This paper presents a new type of wireless platform designed for real-time traffic estimation and road surface monitoring. The sensor platform is built around a 32-bit ARM Cortex M4 micro-controller and a LSM9DS0 Inertial Measurement Unit module. This platform is mainly designed for probe vehicles and can be easily installed in a vehicle equipped with a USB charger. The hardware architecture design and software programming system of the proposed platform are introduced as well as its cost evaluation from the first generation to the third generation. The article then demonstrates some applications of such a platform in smart cities, including trajectory estimation and road condition monitoring. All design files have been uploaded and shared in an open science framework, and can be accessed from https://osf.io/524y9/?view_only=85859a345a7b429fbb8fe194966daa5b . It is licensed under the GNU General Public License v3.0.

DEVICE DRIVER FOR 3-AXIS ACCELEROMETER BASED ON ARM CORTEX-M0+ PROCESSOR

The use of accelerometers in aerial vehicles is crucial for measuring tilt (inclination) in order to control hovering. In this work, the driver software for 3-axis accelerometer device is developed based on the platform of ARM cortex M0+ processor. This driver software reads the values of acceleration of all 3 axes and computes roll, pitch and yaw tilt angles. This driver software is then integrated to open source freeRTOS operating system and then complete system using freeRTOS is tested by making system call from application software. Article DOI: https://dx.doi.org/10.20319/mijst.2018.42.200206 This work is licensed under the Creative Commons Attribution-Non-commercial 4.0 International License. To view a copy of this license, visit http://creativecommons.org/licenses/by-nc/4.0/ or send a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA.

Margin Elimination Through Timing Error Detection in a Near-Threshold Enabled 32-bit Microcontroller in 40-nm CMOS

This paper presents a near-threshold operating voltage timing error detecting 32-bit microcontroller system. The lightweight in situ error detection and correction technique uses a soft-edge flip-flop combined with in-latch transition detection and a set-dominant error latch to detect data path transitions after the clock edge. Inherent error correction is achieved through time borrowing in soft-edge flip-flops. The technique is implemented in an ARM Cortex M0 microcontroller system in 40-nm CMOS, rendering the microcontroller “timing error aware.” Automatic critical path analysis results in an optimized timing error detection window and sparse flip-flop replacement. An autonomous dynamic voltage scaling (DVS) loop facilitates automatic operation at the point of first failure. The M0 system operates down to 290 mV and achieves 11-18 pJ/cycle core energy consumption in a 5-30 MHz frequency ranges. The architecture profits optimally from ULV operation at frequencies <;10 MHz, where intra-die variations are significant.

An Ultralow-Power On-Die PMU in a 28-nm CMOS SoC With Direct Li-Ion Battery-Attach Capability

This paper introduces an on-die power management unit (PMU) within Blackghost 1.0—a test chip for Qualcomm’s newest Blackghost ultralow-power mixed-signal system-on-chip product family. Specifically targeted at battery-powered Internet-of-Things, wearables, and e-medical applications, Blackghost delivers unparalleled power efficiency through low-power innovations from software, architecture, and circuit design [Y. Pu et al., Proc. IEEE Symp. Low-Power High-Speed Chips (COOL CHIPS) , Apr. 2017, pp. 1–3]. It integrates a small footprint sensor/control processor based on ARM Cortex M0, an on-die PMU with direct Li-ion battery-attach capability, a computer vision classifier processor, a programmable DSP hardware accelerator, and an ultralow-power analog front end on a $3 \times 3$ mm2 die in the TSMC 28LP CMOS process technology. The on-die PMU consists of a bandgap reference, a low-frequency RC clock, a high-frequency RC clock, a low drop-out linear regulator, and two switch mode power supply (SMPS) buck regulators. It supports direct Li-ion battery-attach by accepting input voltages up to 5 V. The total quiescent current of the entire PMU is only $9~\mu \text{A}$ . Its SMPS maintains high efficiencies (around 80%) with load currents as low as $10~\mu \text{A}$ .

Opcode vector: An efficient scheme to detect soft errors in instructions

Bit flips on instructions may affect the execution of the processor depending on the Instruction Set Architecture (ISA) and the location of the flipped bits. Intrinsically, ISAs may detect bit upsets if the errors on the instructions produce exceptions that halt the execution. In this paper, we explore a dynamic checking of the instructions to detect errors before execution. The scheme is based on loading an approximate representation of the instructions based on a vector that identifies the opcodes used in the program in a special purpose register. During execution, instructions are first checked on the register and on a negative an error is detected as the instruction has an opcode that does not correspond to any of the ones used in the program. Since we use an approximate representation, a small number of false positives can occur for erroneous instructions which may still be detected if they lead to a system crash. The proposed opcode vector scheme is compared with the use of a Bloom filter (BF) that has been previously proposed to detect errors on instructions. In both cases, a check can produce false positives but not false negatives. The Bloom filter is built using all the bits in the instruction. On the other hand, the opcode vector uses only a few bits of the instruction. In both cases, the check is combined with a previous error propagation scheme. In the opcode case, this ensures that all errors corrupt the opcode bits while for the BF, the error propagation reduces the number of false positives. The proposed approach has two main benefits. The first one is an increase in the error detection rate as the set of valid instructions is restricted to those used in the program allowing the detection of invalid instructions even if they do not lead to a system crash. The second one is that errors are detected before the crash. This is done at the cost of adding a small register for the vector of opcodes and some control logic. This is significantly simpler than in the case of the BF that needs to compute several hash functions and access several bits on the register to perform the check. We evaluated this approach on binary files of the ARM Cortex M0 core. According to our findings, the proposed vector of opcodes is more effective to detect errors than the BF and its detection rate is less dependent on the program size. Based on those results, it seems that the proposed method can be an interesting option to detect errors in instructions for systems on which a small overhead can be introduced if it improves reliability.

Tracking Misplaced Objects Using Bluetooth and GPS with Arm Cortex M3 Development Board

Tracking Misplaced Objects Using Bluetooth and GPS with Arm Cortex M3 Development Board

Smart Grid System Architecture over Embedded System using Internet of Things

This paper refers advanced smart Grid architecture executed with the help of internet of things. Internet of things contains a set for Web administrations have highest priority over internet enabled embedded devices. The Web program on computer could go an interface over service provided by this web of things. Those Embedded devices such as ARM Cortex M3 Processor built gadgets with Ethernet abilities. CMSIS Real time embedded systems will be utilized to transform control on each on these electronic gadgets. LwIP Protocol stack may be actualized on highest priority on each of these units along with the IP connectivity. Those Web interfaces gatherings give us constant majority of the data for each of the energy meters that are introduced with respect to webpage and communicate with web units utilizing MODBUS correspondence protocol. Constant real time energy source scheduling and selection, energy association and separation are some of the administrations that would be given with a on-line verifed client. The inserted embedded systems lab framework at the TIFAC center to 3G/4G correspondence toward national institute of science and technology might have been utilized for that equipment testing of the embedded modules. We were mostly helped by the product developers during NIST innovation consultancy administrations over outlining those web provisions and also interface for our Web of things construction modeling.

Performance Evaluation of SHA-3 Final Round Candidate Algorithms on ARM Cortex–M4 Processor

SHA-3 was an open competition initiated by NIST to design new generation of hash functions. This competition was a necessity to overcome the challenges imposed by multiple attacks on MDx family of hash functions including SHA-0 and SHA-1. For this competition, NIST announced a reference platform which did not cover Embedded and Mobile machines. This paper compares the performance of SHA-3 final round candidate algorithms on ARM Cortex-M4 processor (embedded processor) and presents the results. Cycles per Byte is used as performance metric. Cortex-M4 based Stellaris® LM4F232 Evaluation Board (EK-LM4F232) from Texas Instruments is used for performance evaluation.

Implementation of Brushless DC motor speed control on STM32F407 Cortex M4

Implementation of Brushless DC motor speed control on STM32F407 Cortex M4

SOFTWARE BASED EXPERIMENTAL SYSTEM FOR ELECTRICAL POWER QUALITY MEASUREMENT USING THE WIRELESS SENSOR NETWORK MODULES

Experimental system for measurement of standard electrical power quality (PQ) parameters, based on wireless sensor network (WSN), is presented in this paper. System includes generator of reference voltage waveforms, software application for measurement of standard PQ parameters and two microcontroller based wireless sensor modules for transmitting and receiving of measurement results. Reference voltage signals are provided using signal generator with possibility for simulation of typical network disturbances, presented in some previously published papers. This PQ signal generator is functionally supported by the virtual instrumentation software and data acquisition card. Measurements of basic quality parameters for reference test signals are performed using the LabVIEW software application. Time interval for each measurement cycle is 1 s. For communication is used wireless sensor network based on communication standard IEEE 802.15.4 (Zigbee). Hardware configuration includes two wireless sensor modules SPaRCMosquito v.2, based on the microcontroller with Cortex M3 architecture. Transfer of measurement results, between computer and wireless sensor modules on transmitter and receiver points, are provided using standard USB interface.

A Low Power Consumption Algorithm for Efficient Energy Consumption in ZigBee Motes

Wireless Sensor Networks (WSNs) are becoming increasingly popular since they can gather information from different locations without wires. This advantage is exploited in applications such as robotic systems, telecare, domotic or smart cities, among others. To gain independence from the electricity grid, WSNs devices are equipped with batteries, therefore their operational time is determined by the time that the batteries can power on the device. As a consequence, engineers must consider low energy consumption as a critical objective to design WSNs. Several approaches can be taken to make efficient use of energy in WSNs, for instance low-duty-cycling sensor networks (LDC-WSN). Based on the LDC-WSNs, we present LOKA, a LOw power Konsumption Algorithm to minimize WSNs energy consumption using different power modes in a sensor mote. The contribution of the work is a novel algorithm called LOKA that implements two duty-cycling mechanisms using the end-device of the ZigBee protocol (of the Application Support Sublayer) and an external microcontroller (Cortex M0+) in order to minimize the energy consumption of a delay tolerant networking. Experiments show that using LOKA, the energy required by the sensor device is reduced to half with respect to the same sensor device without using LOKA.

Connecting Things to the IoT by Using Virtual Peripherals on a Dynamically Multithreaded Cortex M3

The Internet of Things communicates with the world by using a wide range of different sensors and actuators. These interfaces are based on a wide range of various protocols, such as I2C, SPI, RS232, 1-wire, and so on. There are two conceptional different solutions to provide these interfaces. One is to use dedicated hardware for it. An example would be to use a peripheral on a system-on-a-chip (SoC). All SoC providers offer the families of SoC solutions with different kind of hardware peripheral combinations. The alternative concept it to run virtual peripherals as a software routine on a CPU, preferable on a multithreaded CPU. C-Slow Retiming (CSR) is a known design transformation to generate multithreaded CPUs. This paper argues, that system hyper pipelining overcomes the limitations of CSR by adding thread stalling, bypassing, and reordering techniques to better cope with the challenges of multithreading. This dynamic multithreaded environment is ideal for running virtual peripheral. The benefits of using system hyper pipelining for virtual peripherals are demonstrated on a Cortex M3-based system.

Circuit and System Designs of Ultra-Low Power Sensor Nodes With Illustration in a Miniaturized GNSS Logger for Position Tracking: Part II—Data Communication, Energy Harvesting, Power Management, and Digital Circuits

This two-part paper reviews recent innovations in circuit design that have accelerated the miniaturization of sensor nodes. In this second part of the paper, we focus on key building blocks of miniaturized sensor nodes, such as data transceivers, energy harvesters, power management units, and digital logic circuits. System level design considerations are also discussed to provide guidelines for the design of a miniaturized system. As an example prototype design, a 2.7-cm3 global navigation satellite system (GNSS) logger is proposed. This paper includes a die-stacked sensor platform composed of an ARM cortex M0 processor, energy harvester, power management unit, solar cell, optical receiver, sensor layer, and RF transmitter that exploits the discussed design techniques for ultra-low power operation. The GNSS logger can store GNSS signals of >1 k positions on a single battery charging without additional energy harvesting.

Formal modeling of biomedical signal acquisition systems: source of evidence for certification

Biomedical signal acquisition systems are software-intensive medical systems composed of processors, transducers, amplifiers, filters, and converters. We present in this article a formal modeling methodology of biomedical signal acquisition systems using Colored Petri Nets (CPN) and based on a frequency-domain approach. In the methodology, a reference model represents the main features of these medium risk systems. We argue that this kind of model is useful to assist manufacturers to reduce the number of defects in systems and to generate safety and effectiveness evidence throughout certification. Therefore, we describe two main contributions in this article. We provide a reference model of biomedical signal acquisition systems and show how manufacturers can generate evidence by means of an electrocardiography (ECG) case study. We carried out the case study by extending the reference model to represent the behavior of an ECG system using a basic cardiac monitor configuration based on the single-lead, heart rate monitor front end (AD8232) and the low power precision analog microcontroller, ARM cortex M3 with dual sigma-delta converters (ADUCM360). We verified the model against safety requirements with the model checking technique (safety evidence) and validated it by comparing output signals with a filtered ECG record available on the PHYSIONET ECG-ID database in the frequency and time domains (effectiveness evidence). This methodology enables manufacturers to identify defects in systems earlier in the development process aiming to decrease costs and development time.

A Scheme to Improve the Intrinsic Error Detection of the Instruction Set Architecture

The Instruction Set Architecture (ISA) determines the effect that a soft error on an instruction can have on the processor. Previous works have shown that the ISA has some intrinsic capability of detecting errors. For example, errors that change a valid instruction into an invalid instruction encoding or into an instruction that causes an exception. The percentage of detectable errors varies widely for each bit in the ISA. For example, errors on bits that are used for immediate or register values are unlikely to be detected while those that are used for the opcode are more likely to lead to an exception. In this paper, this is exploited by introducing a simple encoding of the instructions that does not require additional bits. The idea is that the decoding propagates the error so that it affects the most sensitive bit of the ISA and therefore it is more likely to be detected. As no additional bits are required, no changes or overheads are needed in the memory. The proposed scheme is useful when the memory is not protected with parity or Error Correction Codes. The only cost of implementing the technique are simple encoder and decoder circuits that are similar to a parity computation. This technique is applicable to any ISA, no matter the length of the opcodes or their location in the instruction encoding. The effectiveness of the proposed scheme has been evaluated on the ARM Cortex M0 ISA resulting in an increase in the error detection capability of up to 1.64x.