Margin Elimination Through Timing Error Detection in a Near-Threshold Enabled 32-bit Microcontroller in 40-nm CMOS

Abstract

This paper presents a near-threshold operating voltage timing error detecting 32-bit microcontroller system. The lightweight in situ error detection and correction technique uses a soft-edge flip-flop combined with in-latch transition detection and a set-dominant error latch to detect data path transitions after the clock edge. Inherent error correction is achieved through time borrowing in soft-edge flip-flops. The technique is implemented in an ARM Cortex M0 microcontroller system in 40-nm CMOS, rendering the microcontroller “timing error aware.” Automatic critical path analysis results in an optimized timing error detection window and sparse flip-flop replacement. An autonomous dynamic voltage scaling (DVS) loop facilitates automatic operation at the point of first failure. The M0 system operates down to 290 mV and achieves 11-18 pJ/cycle core energy consumption in a 5-30 MHz frequency ranges. The architecture profits optimally from ULV operation at frequencies <;10 MHz, where intra-die variations are significant.