Cortex-M3 Processor Research Articles

Energy-Efficient Sleep Apnea Detection Using a Hyperdimensional Computing Framework Based on Wearable Bracelet Photoplethysmography.

Sleep apnea syndrome (SAS) is a common sleep disorder, which has been shown to be an important contributor to major neurocognitive and cardiovascular sequelae. Considering current diagnostic strategies are limited with bulky medical devices and high examination expenses, a large number of cases go undiagnosed. To enable large-scale screening for SAS, wearable photoplethysmography (PPG) technologies have been used as an early detection tool. However, existing algorithms are energy-intensive and require large amounts of memory resources, which are believed to be the major drawbacks for further promotion of wearable devices for SAS detection. In this paper, an energy-efficient method of SAS detection based on hyperdimensional computing (HDC) is proposed. Inspired by the phenomenon of chunking in cognitive psychology as a memory mechanism for improving working memory efficiency, we proposed a one-dimensional block local binary pattern (1D-BlockLBP) encoding scheme combined with HDC to preserve dominant dynamical and temporal characteristics of pulse rate signals from wearable PPG devices. Our method achieved 70.17 % accuracy in sleep apnea segment detection, which is comparable with traditional machine learning methods. Additionally, our method achieves up to 67× lower memory footprint, 68× latency reduction, and 93× energy saving on the ARM Cortex-M4 processor. The simplicity of hypervector operations in HDC and the novel 1D-BlockLBP encoding effectively preserve pulse rate signal characteristics with high computational efficiency. This work provides a scalable solution for long-term home-based monitoring of sleep apnea, enhancing the feasibility of consistent patient care.

Improved RSA with Enhanced Security on STM32 @ 84MHz

Enhanced computations resulted in the evolution of cyber-physical systems (CPS). These systems are highly vulnerable to security threats. This work addresses the security concerns for a reliable CPS in the Internet of Things (IoT) through an improvised RSA with enhanced security features. The proposed method renders data throughput encryption at 11.67[Formula: see text]Kbps with an overall average execution time of 0.02[Formula: see text]s. The proposed algorithm exhibits the unique feature of being asymmetric, lightweight & enhanced security owing to randomization (average entropy of 0.98). The performance metrics of the proposed method are compared with other state-of-art techniques. This algorithm is implemented on commercially competent architecture STM32F401RET6 with cortex M4 processor running @ 84[Formula: see text]MHz. The proposed encryption method exhibits great features thus making it a potential real-world solution.

ЗАСТОСУВАННЯ BBC MICRO:BIT ДЛЯ НАВЧАННЯ ПРОГРАМУВАННЮ

Considers the use of the BBC Microbit educational microcomputer to introduce the basics of programming to pupils and students in non-technical majors. The paper presents a comparison of the use of single-board computers. The available visual programming environment, as well as a large number of input and output devices on a single-board computer board, makes it much easier to interact with the environment. It is noted that the board can be programmed using visual block programming language, javascript or using Python. If you wish, you can load other systems into Micro:bit, for example, mbed OS and write in C++, but these are already opportunities for students of initial courses of technical specialties. It was determined that the board has an ARM Cortex-M0 processor, 256KB Flash ROM, 16KB RAM, 16MHz clock frequency. There is also BTLE support, a 2.4GHz peer-to-peer transmitter (101 channels), an accelerometer, a compass, a thermometer, and a line of GPIO pins. Even if there is no fee, there is a full-fledged simulator right in the browser, in which you can test all the functions of the program. Ready-made "blocks" are available to the student with many different functions: from simple input-output to sound reproduction or machine control. The board can be programmed using visual block programming language, javascript or Python. The Python programming language has a very simple, but simple editor, and the student can write the code independently. The work shows that the BBC Microbit microcomputer allows to simplify the process of learning program algorithms through the use of a visual programming environment. And the use of functional extensions with the use of third-party modules provides additional opportunities for creating powerful software applications.

Masking Floating-Point Number Multiplication and Addition of Falcon

In this paper, we provide the first masking scheme for floating-point number multiplication and addition to defend against recent side-channel attacks on Falcon’s pre-image vector computation. Our approach involves a masked nonzero check gadget that securely identifies whether a shared value is zero. This gadget can be utilized for various computations such as rounding the mantissa, computing the sticky bit, checking the equality of two values, and normalizing a number. To support the masked floating-point number addition, we also developed a masked shift and a masked normalization gadget. Our masking design provides both first- and higherorder mask protection, and we demonstrate the theoretical security by proving the (Strong)-Non-Interference properties in the probing model. To evaluate the performance of our approach, we implemented unmasked, first-order, and second-order algorithms on an Arm Cortex-M4 processor, providing cycle counts and the number of random bytes used. We also report the time for one complete signing process with our countermeasure on an Intel-Core CPU. In addition, we assessed the practical security of our approach by conducting the test vector leakage assessment (TVLA) to validate the effectiveness of our protection. Specifically, our TVLA experiment results for second-order masking passed the test in 100,000 measured traces.

Fractional-order-induced symmetric multi-scroll chaotic attractors and double bubble bifurcations in a memristive coupled Hopfield neural networks

The multi-state memristor is a type of memristor capable of memorizing multiple conductance states. This special feature is successfully used to mimic the behavior of neural synapses and simulate the influences of electromagnetic induction and radiation in artificial neural networks such as Hopfield neural networks. This paper introduces and examines a novel fractional-order Hopfield neural network model consisting of two non-identical sub-Hopfield neural networks coupled by a multi-stable flux controlled memristor (MCFHNN). The pinched hysteresis loops of the multi-stable flux controlled memristor are analyzed via numerical simulations. The equilibrium points of MCFHNN model and their stability are investigated. The introduced MCFHNN model is solved by using Adomian Decomposition Method (ADM). By using some examination methods such as spectral entropy complexity, bifurcation diagrams, phase portraits, maximum Lyapunov exponent and basins of attraction, we analyze the dynamic behaviors of MCFHNN model associated with coupling strength, fractional-order and initial states. Numerical results demonstrate that the proposed MCFHNN model is capable to develop abundant and complicated dynamics including, chaos, multiple transient transition behaviors, double bubble bifurcations, initial-boosted behavior and symmetric multi-scroll chaotic attractors. It is found that the complexity results are in agreement with those obtained from the bifurcation diagrams. This proves that the complexity can well reflect the dynamic behaviors of MCFHNN model. In order to support theoretical and numerical results, the designed MCFHNN model is implemented with the help of an Arduino-Due microcontroller board based on the Atmel SAM3X8E ARM Cortex-M3 processor. The results are in very good agreement with those obtained from computational simulations.

Laser Voltage Probing Attack Detection With 100% Area/Time Coverage at Above/Below the Bandgap Wavelength and Fully-Automated Design

In this work, a detection scheme signaling the occurrence of laser voltage probing (LVP) attacks in digital designs (e.g., cryptographic circuits) is introduced. The scheme comprises a standard cell-based photosensor fabric and distributed detectors. By construction, the scheme conforms the standard cell design discipline, restricted layout design rules, and commercial place and route tools. This allows seamless integration with automated design flows, and immediate adoption in a design-agnostic fashion. Hundred percentage time and area coverage is achieved for full protection against LVP attacks, while not requiring any calibration. Extensive attacks with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim $</tex-math> </inline-formula> 150 h of characterization with a state-of-the-art LVP equipment on a 28-nm testchip demonstrate laser detection at both above-and below-bandgap wavelengths and, hence, even at the very low electron-hole pair generation rate of the former ones. Attacks to an advanced encryption standard (AES) core are shown to be flagged at any practical laser intensity and best-in-class true 220-nm laser spot. Low circuit activity confines its power to leakage, amounting to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt;$</tex-math> </inline-formula> 0.1% of the AES power. At the worst case, 150% area overhead is substantially lower in practical cases where the information-sensitive blocks are a portion of it (e.g., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt;$</tex-math> </inline-formula> 20% in an advanced reduced instruction set computer machines (ARM) Cortex-M4 processor with a secure AES accelerator). To the best of the authors’ knowledge, this is the first demonstration of a design-agnostic on-chip protection against LVP attacks with full-area coverage under unmodified manufacturing/packaging process.

MorpheusNet: Resource efficient sleep stage classifier for embedded on-line systems.

Sleep Stage Classification (SSC) is a labor-intensive task, requiring experts to examine hours of electrophysiological recordings for manual classification. This is a limiting factor when it comes to leveraging sleep stages for therapeutic purposes. With increasing affordability and expansion of wearable devices, automating SSC may enable deployment of sleep-based therapies at scale. Deep Learning has gained increasing attention as a potential method to automate this process. Previous research has shown accuracy comparable to manual expert scores. However, previous approaches require sizable amount of memory and computational resources. This constrains the ability to classify in real time and deploy models on the edge. To address this gap, we aim to provide a model capable of predicting sleep stages in real-time, without requiring access to external computational sources (e.g., mobile phone, cloud). The algorithm is power efficient to enable use on embedded battery powered systems. Our compact sleep stage classifier can be deployed on most off-the-shelf microcontrollers (MCU) with constrained hardware settings. This is due to the memory footprint of our approach requiring significantly fewer operations. The model was tested on three publicly available data bases and achieved performance comparable to the state of the art, whilst reducing model complexity by orders of magnitude (up to 280 times smaller compared to state of the art). We further optimized the model with quantization of parameters to 8 bits with only an average drop of 0.95% in accuracy. When implemented in firmware, the quantized model achieves a latency of 1.6 seconds on an Arm Cortex-M4 processor, allowing its use for on-line SSC-based therapies.

Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems

Embedded systems confront two opposite goals: low-power operation and high performance. The current trend to reach these goals is toward heterogeneous platforms, including multi-core architectures with heterogeneous cores and hardware accelerators. The latter can be divided into custom accelerators (e.g., ASICs) and programmable domain-specific cores (e.g., DSIPs). VWR2A [1] is a programmable architecture that integrates high computational density and low power memory structures. The flexibility of VWR2A allows a large portion of applications to be covered, resulting in better performance and energy efficiency than ASICs and general-purpose processors. However, while this has been well studied for data-intensive kernels, this is not the case for control-intensive kernels —code with complex if-else and nested loop structures. Traditionally, control-intensive code is left to be executed by the host processor. This situation unnecessarily restricts the potential impact of energy-efficient acceleration, especially at the application level. In this paper, we evaluate the performance and energy consumption of VWR2A for control-intensive code and compare it with an ARM Cortex-M4 processor and a RISC-V Ibex processor. The performance and energy consumption are evaluated at the kernel and application levels. Our results confirm that VWR2A is faster and more energy-efficient than the two considered general-purpose processors also for control-intensive code.

GridNetOpt: Fast Full-Chip EM-Aware Power Grid Optimization Accelerated by Deep Neural Networks

This article presents a fast full-chip electromigration (EM) aware IR drop constrained optimization framework, named GridNetOpt, for on-chip power grid networks accelerated by deep neural networks (DNN). Compared to the existing linear programming-based methods, the new method employs more flexible conjugate gradient-based optimization to size the wire width of the power grids. To mitigate the high cost of sensitivity calculation of the adjoint network using full-chip IR drop analysis at every iteration step, the sensitivity is computed via a trained conditional generative adversarial network (CGAN). The new method exploits the differentiable characteristics of DNNs for fast sensitivity computation. The sensitivity, which is the node voltage with respect to wire resistance, will guide the search direction during the optimization process. In order to consider more accurate EM failure effects, the training data is obtained from the power grids under different wire widths and current loads analyzed by a state-of-the-art full-chip multi-physics-based coupled EM-IR drop analysis tool. This is in contrast with the existing linear programming-based methods, in which only immortal wires or wires with non-zero resistance can be dealt with. Numerical results on a number of synthesized power grid benchmarks from ARM Cortex-M0 processor designs show that the proposed GridNetOpt can lead to at least an order of magnitude speedup over the conjugate gradient-based method using the traditional adjoint network method. Compared to the previous localized power grid fixing work with GridNet, GridNetOpt leads to smaller area overhead for all the benchmarks we tested. It can also reduce IR drops for power grid circuits with immortal wires, which is not possible with the localized GridNet method.

A Sub-mW Cortex-M4 Microcontroller Design for IoT Software-Defined Radios

We present an Internet-of-Things (IoT) software-defined radio platform based on an ultra low-power microcontroller. Whereas conventional wireless IoT radios often implement a single protocol, we demonstrate that general-purpose microcontrollers running software implementations of wireless physical layers are a promising solution to increase interoperability of IoT devices. Yet, since IoT devices are often energy-constrained, the underlying challenge is to implement the digital signal processing of the radio in software while maintaining an overall very low power consumption. To overcome this problem, we propose an ultra low-power microcontroller architecture with an ARM Cortex-M4 processor for the protocol-specific computations and a hardware digital front-end for the generic signal processing. The proposed architecture has been prototyped in 28nm FDSOI and the physical layers of the well-known LoRa and Sigfox protocols have been implemented in software. Thanks to the efficient hardware/software partitioning and an ultra-low power digital implementation, experimental evaluations of the microcontroller prototype show sub-mW power consumptions (32 – 332 μW) for the digital signal processing of the software-defined radios.

Practical Public Template Attacks on CRYSTALS-Dilithium With Randomness Leakages

Side-channel security has become a significant concern in the NIST post-quantum cryptography standardization process. The lattice-based CRYSTALS-Dilithium (abbr. Dilithium) becomes the primary signature standard algorithm recommended by NIST for most use cases in July 2022 due to its excellent performance in security and efficiency. Compared to Dilithium’s rich theoretical security analysis results, the side-channel security of its physical implementations needs to be further explored. In 2021, Liu et al. proposed a two-stage randomness leakage attack against Dilithium, in which only one randomness bit with a probability <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt; 0.5$ </tex-math></inline-formula> per signature is enough to recover the private key. However, they only carried out proof-of-concept experiments on “research-oriented” reference implementation of polynomial addition. Whether this method applies to complete real-world implementations of Dilithium is unknown. In this paper, we put this randomness leakage attack into real-world and recover the private key of unprotected and masked Dilithium on Arm Cortex-M4 processor using non-profiled power analysis attacks. Since randomness is introduced in the signing process, it is challenging to recover the randomness bit of Dilithium with high success rate in only one trace. Inspired by Liu et al., we propose a new non-profiled attack called Public Template Attack (PTA), a template-attack-like method that builds templates using public information. With PTA, we recover the randomness bit of unprotected and masked Dilithium with a success rate of 95% and 62% in one power trace, respectively. To demonstrate practicality, we perform practical power analysis attacks against different security levels of round 3 unprotected and masked Dilithium on STM32F405 microprocessor. Using 10,000 traces, the private key of unprotected Dilithium2 is recovered in 0.5 hours with an ordinary PC desktop. Our attack is 240 times faster than the state-of-the-art non-profiled attack. Moreover, the private key of masked Dilithium2 is recovered using 680,000 traces in 38 hours. To the best of our knowledge, we are the first to successfully attack masked Dilithium using non-profiled attacks.

Vertical Jump Data from Inertial and Optical Motion Tracking Systems

Motion capture (MOCAP) is a widely used technique to record human, animal, and object movement for various applications such as animation, biomechanical assessment, and control systems. Different systems have been proposed based on diverse technologies, such as visible light cameras, infrared cameras with passive or active markers, inertial systems, or goniometer-based systems. Each system has pros and cons that make it usable in different scenarios. This paper presents a dataset that combines Optical Motion and Inertial Systems, capturing a well-known sports movement as the vertical jump. As a reference system, the optical motion capture consists of six Flex 3 Optitrack cameras with 100 FPS. On the other hand, we developed an inertial system consisting of seven custom-made devices based on the IMU MPU-9250, which includes a three-axis magnetometer, accelerometer and gyroscope, and an embedded Digital Motion Processor (DMP) attached to a microcontroller mounted on a Teensy 3.2 with an ARM Cortex-M4 processor with wireless operation using Bluetooth. The purpose of taking IMU data with a low-cost and customized system is the deployment of applications that can be performed with similar hardware and can be adjusted to different areas. The developed measurement system is flexible, and the acquisition format and enclosure can be customized. The proposed dataset comprises eight jumps recorded from four healthy humans using both systems. Experimental results on the dataset show two usage examples for measuring joint angles and COM position. The proposed dataset is publicly available online and can be used in comparative algorithms, biomechanical studies, skeleton reconstruction, sensor fusion techniques, or machine learning models.

Type-1 and type-2 fuzzy logic-based space vector modulation for two-level inverter fed induction motor

Two-level inverter control with type-1 and type-2 fuzzy logic-based space vector pulse-width modulation (PWM) method for induction motor drive (IMD) is presented in this paper. A new sampling time independent strategy with type-1 and type-2 fuzzy based methods are used in generating three phase duty ratios which are directly obtained without mathematical equations. The conventional method of space vector modulation (SVM) produces the duty ratios for the inverter which are sampling time dependent. However, in type-1 and type-2 fuzzy based space vector PWM algorithms, the three phases duty ratios generated are sampling time independent and with a new integrated dead-time insertion in SVM itself, can be implemented practically for any switching frequency. As the rule-base for Mamdani non-singleton interval type-1 and type-2 fuzzy inference systems are designed manually, with the expert knowledge of conventional space vector PWM, the duty ratios of the inverter are generated such that the performance of the IMD is improved. The simulation studies for aforementioned cases is performed in matrix laboratory (MATLAB) and experimental validation for the proposed space vector PWM algorithms is validated using real-time sacraetheologiae magister (STM) hardware with STM32F429I Cortex M4 processor for a 1 hp IMD.

Three-phase inverter with a variable control algorithm

The paper presents the construction of a three-phase frequency converter with the possibility of choosing the type of PWM modulation and a smooth change of the frequency of the modulated signal. In a practical way, various inverter control algorithms were implemented in the same hardware system using the STM ARM Cortex M3 processor. The use of THIPWM modulation allowed to reduce the harmonic content in the output signal and effectively use the possibilities of the power source. The system can choose one of two scalar control algorithms, with the option of compensation for the influence of the stator resistance on the motor shaft torque in the initial range of the linear control characteristic at a constant voltage to frequency ratio. The research confirmed that the most advantageous type of PWM in this system is unipolar double-edge modulation. The use of the THIPWM method resulted in a gain in the amplitude of the fundamental harmonic of the output voltage for the three-phase inverter operation mode compared to the SPWM method. The appropriate precision of the frequency control step was also obtained, and the test results confirmed the functionality of the converter.

Conducted EMI susceptibility analysis of a COTS processor as function of thermal cycling and overvoltage stresses

As technology evolves, processors are increasingly used in critical applications while the operating environment has become more unfavorable, with greater electromagnetic interference (EMI) detrimental to the proper functioning of the component. In this context, EMI represents one of the most critical problems for assessing the reliability and robustness of electronic systems, worsening when associated with the natural aging effect of circuits. This paper investigates the electromagnetic susceptibility (EMS) of a Cortex-M4 processor to conducted EMI in the power supply lines as function of accelerated aging. The component's reliability assessment was performed according to the IEC 61000-4-4 and IEC 61000-4-6 standards as function of the accelerated aging by means of stress combination of temperature variations and overvoltage. Test results demonstrated an increased processor susceptibility to conducted EMI after accelerated aging process. In this context, after aging it was observed a 13,166% increase in the number of observed faults, while current consumption raised by 5.63%.

A Digital-Analog Hybrid System-on-Chip for Capacitive Sensor Measurement and Control.

Sensors based on capacitance detection are common in the field of inertial measurement and have the potential for miniaturization and low power consumption. In order to control and process such sensors, a novel digital-analog hybrid system-on-chip (SoC) is designed and implemented. The system includes a capacitor to voltage (C/V) conversion circuit and a band-pass sigma-delta modulator (BPSDM) as the analog-to-digital converter (ADC). The digital signal is processed by the dedicated circuit module based on the least mean square error demodulation (LMSD) algorithm on the chip. The low-power Cortex-M3 processor supports software implementation of control algorithms and circuit parameter configuration. The control signal is output through a digital BPSDM. The chip was taped out under SMIC 180 nm Complementary Metal Oxide Semiconductor (CMOS) technology and tested for performance. The result shows that the maximum operating frequency of the chip is 105 MHz. The total area is 77.43 mm2. When the system clock is set to 51.2 MHz, the static power consumption and dynamic power consumption of the digital system are 18 mW and 54 mW respectively.

A blockchain-based architecture for secure and trustworthy operations in the industrial Internet of Things

The industrial Internet of Things (IIoT) plays an important role in the industrial sector, where secure, scalable, and easily adopted technologies are being implemented for the smart industry. The traditional IIoT architectures are generally based on centralized architectures that are vulnerable to a single point of failure and to several cyber-attacks. Blockchain technology is frequently adopted in the modern industry because of its security and decentralization. This paper proposes a blockchain-based architecture that ensures secure and trustworthy industrial operations. A private and lightweight blockchain architecture is proposed to regulate access to valuable sensor and actuator data. To enhance the computational performance of the proposed architecture, real-time cryptographic algorithms are processed using a low-power ARM Cortex-M4 processor, and a highly scalable, fast, and energy-efficient consensus mechanism proof of authentication (PoAh) is deployed in the blockchain network. Extensive experiments and analysis proved the effectiveness of the proposed framework for smart industrial environments. Finally, we transform a conventional fruit processing plant into a secure and smart industrial platform by implementing the proposed architecture.

Conducted EMI susceptibility analysis of a COTS processor as function of aging

This work analyses the conducted electromagnetic interference (EMI) immunity of the Cortex-M4 processor as function of aging. With this purpose, voltage dips were injected in the VDD input power pins of the processor as ruled by the IEC 61000–4-29 standard, whereas aging test was performed by means of the 1015.9 Burn-In Part of the Method MIL-STD-833E. After 456 h of burn-in at 125 °C, the processor presented a current increase in excess of 2.36% and conducted EMI immunity degradation in the order of 158% for the processor operating at extremely low voltage. If the processor is running in the manufacturer's recommended operating voltage range, then such degradation turns into 38%. Moreover, it was measured negligible performance degradation according to the Dhrystone V2.1a benchmark.

Processor Energy–Performance Range Extension Beyond Voltage Scaling via Drop-In Methodologies

This work introduces reconfiguration for energy–performance adaptation beyond conventional voltage scaling in microcontroller-based systems. Coordinated thread-level processor and row-level memory reconfiguration are enabled by an architecture-agnostic methodology. The latter requires low design and integration effort while reusing existing macros, including third-party intellectual properties (IPs) in an obfuscated or encrypted form. The methodology represents a drop-in solution that is applicable to extend the energy–performance tradeoff in existing designs. The proposed approach was demonstrated with a testchip implementing an ARM Cortex-M0 processor with 16-KB SRAM in 40 nm. The system demonstrates 1.8X throughput boost at nominal voltage (1.1 V) and 1.3X energy reduction at the minimum energy point (0.51 V) compared to voltage scaling with no reconfiguration. Such energy–performance range extension is achieved at 10.3% area overhead, which is mostly due to processor reconfiguration. Overall, the proposed approach reduces energy in the common case and increases performance when demanded, surpassing the capabilities of conventional voltage scaling, while reusing existing IPs and retaining the original software stack.

A pure hardware implementation of CRYSTALS-KYBER PQC algorithm through resource reuse

This paper presents a pure hardware implementation of CRYSTALS-KYBER algorithm on Xilinx FPGAs. CRYSTALS-KYBER is one of 26 candidate algorithms in Round 2 of NIST Post-Quantum Cryptography (PQC) standardization process. The proposed design focuses on maximizing resource utilization by reusing most of the functional modules in the encapsulation and decapsulation processes of the algorithm. For instance, the hash module integrates several different hash functions in one module. Efficient parallel and pipelined computations are applied in the NTT module. Through the analysis of simulation and synthesis results, it is found that the proposed work has the advantages of higher frequencies and lower execution times. The scheme operates at 155 MHz and 192 MHz frequencies on Xilinx Artix-7 and Virtex-7 FPGAs, respectively. Compared with the performance of an embedded Cortex-M4 processor, the hardware implementation can achieve a maximum speedup of 129 times for encryption/decryption.