Processor Energy–Performance Range Extension Beyond Voltage Scaling via Drop-In Methodologies

Abstract

This work introduces reconfiguration for energy–performance adaptation beyond conventional voltage scaling in microcontroller-based systems. Coordinated thread-level processor and row-level memory reconfiguration are enabled by an architecture-agnostic methodology. The latter requires low design and integration effort while reusing existing macros, including third-party intellectual properties (IPs) in an obfuscated or encrypted form. The methodology represents a drop-in solution that is applicable to extend the energy–performance tradeoff in existing designs. The proposed approach was demonstrated with a testchip implementing an ARM Cortex-M0 processor with 16-KB SRAM in 40 nm. The system demonstrates 1.8X throughput boost at nominal voltage (1.1 V) and 1.3X energy reduction at the minimum energy point (0.51 V) compared to voltage scaling with no reconfiguration. Such energy–performance range extension is achieved at 10.3% area overhead, which is mostly due to processor reconfiguration. Overall, the proposed approach reduces energy in the common case and increases performance when demanded, surpassing the capabilities of conventional voltage scaling, while reusing existing IPs and retaining the original software stack.