Correlated Level Shifting Research Articles

A 2-2 MASH ΔΣ ADC with fast-charge CLS input buffer and dual double sampling achieving 103.3-dB SNDR and ±2.5-ppm/FSR INL

This paper presents a 2-2 multi-stage-noise-shaping (MASH) ΔΣ analog-to-digital converter (ADC), in which an integrator with dual double sampling (DDS) technique and stability compensation is proposed to save the area of capacitors without increasing the thermal noise. In addition, a fast-charge correlated-level-shifting (CLS) input buffer is also proposed to improve the linearity with acceptable power consumption. The buffer and the ADC are fabricated in a 0.18-μm CMOS process with an active area of 2.41 mm2, with 3∼5V supply voltage for the input buffer and 1.8-V power supply for the ADC, the overall ADC chip achieves a signal-to-noise-and-distortion ratio (SNDR) of 103.3 dB, a spurious-free dynamic range (SFDR) of 113.2 dB and an integral nonlinearity (INL) of ±2.5 ppm/full-scale range (FSR). The overall power consumption is 14.88 mW.

A 5 kHz-BW 18-bit zoom ADC with gain-enhanced CLS-assisted FIA

This paper presents a 5 kHz-BW 18-bit fully dynamic zoom ADC for low-power and high-resolution applications. A gain-enhanced cascode floating inverter amplifier (FIA) with correlated level shifting (CLS) assisted is proposed to achieve 68.5 dB effective gain with high energy efficiency. The data-weighted averaging (DWA) technique is implemented to suppress the nonlinearity caused by feedback DAC mismatch. Meanwhile, the coefficients of ΔΣ modulator are optimized for low power consumption. The proposed zoom ADC is designed in a 0.18 μm CMOS process. The post-layout simulation results show a peak SNDR of 110.4 dB and a peak SFDR of 114.8 dB with a 5 kHz-BW at an oversampling ratio (OSR) of 256. The power consumption of the proposed ADC is 342 μW at 2.56 MHz sampling frequency with 1.8 V supply, and the Schreier figure-of-merit (FoMSNDR) is 182.05 dB.

An Energy-Efficient Inverter-Based Voltage Reference Scheme with Wide Output Range Using Correlated Level Shifting Technique

A voltage reference is indispensable in Integrated Circuits. To improve the limited linear output voltage range and energy efficiency of a voltage reference, we innovatively propose a switched-capacitor-based programmable voltage reference scheme employing inverter-based OTAs to reduce the power consumption, simultaneously using a novel Correlated Level Shifting (CLS) technique (without active overhead) to enhance the OTA’s DC gain and integral gain. Experimented with SMIC 180 nm CMOS technology, a scheme-based voltage reference realizes a programable output voltage range from 266 to 995 mV at −30 to 120 °C, and the corresponding temperature coefficient (TC) ranges from 82.4 to 99.5 ppm/°C. The power consumption is 976 nW. Furthermore, comparative experiments and evaluations with other schemes have unequivocally verified the superiority of our proposed scheme, characterized by its high energy efficiency and wide output voltage range. The scheme can be suitably deployed in a multitude of novel edge-data processing systems.

A 79.2-μW 19.5-kHz-BW 94.8-dB-SNDR Fully Dynamic DT ΔΣ ADC Using CLS-Assisted FIA With Sampling Noise Cancellation

This brief proposes a fully dynamic discrete-time (DT) Σ ADC using a correlated level shifting (CLS)-assisted floating inverter amplifier (FIA) with a sampling noise cancellation (SNC) technique. The CLS-assisted FIA improves amplifier gain with a single-stage configuration, which has lower input-referred noise than the cascaded one. In combination with the proposed SNC, the noise contribution of the 1st-stage integrator can be minimized. We also propose a novel passive integrator cascaded with a passive adder that avoids unwanted inter-stage loading without a speed penalty. The prototype of the proposed ADC fabricated in a 65 nm bulk CMOS process realizes a fully dynamic operation and achieves 94.8 dB SNDR with an OSR of 256 for 19.5 kHz bandwidth while consuming 79.2 W from a 1.2V supply at a 10 MHz sampling frequency. The Schreier and Walden FoMs are respectively 178.7 dB and 45.2 fJ/conv.-step, which are the best among recent fully dynamic DT Σ ADCs with similar bandwidth.

Fully Dynamic Zoom-ADC Based on Improved Swing-Enhanced FIAs Using CLS Technique With 1250× Bandwidth/Power Scalability

This brief proposes a fully dynamic zoom ADC based on improved swing-enhanced floating-inverter amplifiers (SEFIAs) using the correlated-level-shifting (CLS) technique with 1250× bandwidth/power scalability, by only changing the clock frequency. The improved SEFIA with CLS uses a reused capacitor to replace the dynamic biasing capacitor and input coupling capacitor, which simultaneously achieves both high gain and high output swing. Fabricated in a 55nm CMOS process, the prototype ADC with near-constant energy efficiency, which scales power from 453nW to 122μW, achieves high resolution (> 95.2 dB) and high DR (> 96.7 dB) during the scalable bandwidth. At 5kHz BW, it achieves 97.3dB DR, 96.3dB SNDR, and 112.2dB SFDR, leading to FoMDR of 177.1dB and FoMSNDR of 176.1dB.

Noise-Shaping SAR ADC Using a Two-Capacitor Digitally Calibrated DAC With 82.6-dB SNDR and 90.9-dB SFDR

A novel active noise-shaping SAR ADC with on- chip digital DAC calibration is presented. To relax the design of the single op-amp used as an integrator, correlated double sampling (CDS) and correlated level shifting (CLS) were implemented. CDS minimizes the offset of the integrator and reduces the flicker noise, while CLS boosts the gain of the op-amp and reduces the power consumption. Also, a two-step incremental ADC based digital DAC calibration scheme was implemented to cancel the DAC mismatch errors and parasitics effects. The ADC was fabricated in 0.13 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology. It achieved 85.1 dB DR, 82.6 dB SNDR and 90.9 dB SFDR within a 2 kHz signal bandwidth with an oversampling ratio OSR = 32. It consumes 40.8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power using a 1.6 V power supply.

A Novel Offset and Finite-Gain Compensated Switched-Capacitor Amplifier with Input Correlated Level Shifting

A novel offset and finite-gain compensated differential switched-capacitor(SC) amplifier is presented. Incorporating the correlated double sampling (CDS) technique and input correlated level shifting (CLS) technique together, the DC offset and DC gain error of SC amplifier are further reduced by a factor of op-amp DC gain compared with the conventional offset and finite-gain compensated SC amplifier. The effectiveness of the new scheme has been analyzed and verified by extensive simulations. An SC amplifier with the proposed scheme is designed in 130 nm CMOS technology. Simulated results show that with an op-amp having a low DC gain of 30 dB and an input offset of 10 mV, the proposed SC amplifier achieves an output offset and DC-gain error of 154 µV and 0.05%, respectively, which are significantly improved compared with 1.155 mV and 0.42% achieved in the conventional SC amplifier.

A 75.3-dB SNDR 24-MS/s Ring Amplifier-Based Pipelined ADC Using Averaging Correlated Level Shifting and Reference Swapping for Reducing Errors From Finite Opamp Gain and Capacitor Mismatch

This paper proposes averaging correlated level shifting (ACLS) and reference swapping (RS) techniques for simultaneously reducing errors from the finite opamp gain and capacitor mismatch in a pipelined analog-to-digital converter (ADC). The ACLS technique reduces the sensitivity of ADC accuracy to the opamp gain by averaging the finite opamp gain errors in two amplifying phases, where the error in the second amplifying phase is designed to have the opposite polarity to the one in the first amplifying phase. Meanwhile, ACLS also decreases the opamp’s thermal noise. In addition, the RS utilizes the averaging operation to reduce capacitor random mismatch error and combines a simple capacitor layout arrangement to decrease capacitor gradient mismatch error. Using the ACLS and RS techniques, a 16-bit ring amplifier-based pipelined ADC without calibration is realized in a 90-nm CMOS technology. Operating at 24 MS/s for a 10-MHz sine wave input, the proposed ADC achieves a 74.3-dB signal-to-noise-and-distortion ratio (SNDR) and 85.5-dB spurious free dynamic range (SFDR), and consumes 5.1 mW, yielding Walden and Schreier figure of merits of 50.1 fJ/conversion-step and 168 dB, respectively.

A 5-V 290- $\mu\hbox{W}$ Low-Noise Chopper-Stabilized Capacitive-Sensor Readout Circuit in 0.8- $\mu\hbox{m}$ CMOS Using a Correlated-Level-Shifting Technique

In this brief, a low-power high-resolution readout front end intended for capacitive sensors is presented, in which the circuit uses correlated-level-shifting (CLS) and chopperstabilization (CS) techniques. CLS is a relatively new switchedcapacitor (SC) technique that is used to reduce errors from finite operational amplifier (op-amp) gain, whereas CS is a classic technique that is used to reduce the adverse effects of dc offset and low-frequency noise associated with the op-amp. In this brief, the capacitive sensor is physically emulated by a pair of on-chip differential variable capacitors that are in the femtofarad range. The proposed front end is designed in a 0.8-μm CMOS technology and consumes 290 μW from a single 5-V supply. The readout circuit achieves a capacitance noise floor of 0.018 aF/√Hz at 400 Hz with a sensitivity of 50 mV/fF.

Sequential Correlated Level Shifting: A Switched-Capacitor Approach for High-Accuracy Systems

Analog circuit accuracy is severely limited by finite and nonlinear opamp gain. For switched-capacitor circuits, correlated level shifting (CLS) is an effective technique to improve system accuracy with negligible additive noise. A modification of this method, called sequential CLS, is introduced in this brief, which provides dramatic increases in the effective accuracy of a switched-capacitor structure. Measurements of prototype sample-and-hold structures utilizing simple single-stage opamps in an LP 90-nm CMOS technology show that at the same power and area consumption, the proposed modification can improve the settling accuracy of simple CLS from 5.8 to 8.8 bits with two additional sequential steps.

Design of a Split-CLS Pipelined ADC With Full Signal Swing Using an Accurate But Fractional Signal Swing Opamp

Building on the technique of correlated level shifting (CLS), Split-CLS is introduced as a viable way to enable the design of high performance, high resolution A/D converters in deep submicron CMOS processes. One possible implementation of Split-CLS is presented, which achieves very high effective gain, and combines the fast, high efficiency charging of a zero-crossing based circuit (ZCBC) with the high-accuracy, low power settling of a double-cascode telescopic opamp. A dynamic zero-crossing detector (ZCD) conserves power in the ZCBC by only creating high bandwidth in the ZCD near the zero-crossing instant. Measured results are presented from a pipelined A/D converter fabricated in 0.18 m CMOS. Using the Split-CLS structure, an opamp with 300 mV output swing is used to produce a pipeline stage output swing of 1.4 V. The proof-of-concept test chip achieves 68.3 dB SNDR (11.1b ENOB) and 76.3dB SFDR while sampling at 20 MHz, and consumes 17.2 mW at 1.8 V supply.

An Over-60 dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp With Only 30 dB Loop Gain

Correlated level shifting (CLS) is introduced as a new switched-capacitor technique to provide true rail-to-rail performance while reducing errors from finite opamp gain. There is negligible kT/C noise increase and in many cases a speed advantage compared to using a high gain opamp. The gain enhancement is quantified with formulas and the general technique is compared to correlated double sampling (CDS). Results are presented from a 0.18 mum CMOS testchip of a 20 MHz, 12-bit pipelined A/D converter using CLS to reduce errors from finite opamp dc gain and limited opamp swing. It achieves 10.5 ENOB operating beyond the supply rails using an opamp circuit with 30 dB loop gain and 0.9 V supply.