Single Error Correction Research Articles

Modelling the Dynamics of Exchange Rates and GDP in Nigeria: A Single Equation Error Correction Model (ECM) Analysis

This study eval_uates the effect of exchange rates on Nigeria's economic growth between 1990 and 2020 was examined. The exchange rate was limited to the nominal exchange rate, and real gross domestic product was used as a proxy for the growth of the economy. Secondary data were collected from the Central Bank of Nigeria statistical bulletin for the period of the study. The OLS regression and Granger Causality test were used for analysis in the study. The findings demonstrated that one of the two explanatory variables, exchange rate, has a substantial significant effect on economic growth. The causality test also showed that there is two-way causality between exchange rate and the economic growth. The study concludes that increase when there is increase in exchange rate, the economic growth (GDP) will increase in Nigeria since exchange rate is and essential and significant predictor of economic growth.

Error mitigation in LPWAN systems: A study on the efficacy of Hamming-coded RPW.

Rotating Polarization Wave (RPW) is a novel Low Power Wide Area Networks (LPWAN) technology for robust connectivity and extended coverage area as compared to other LPWAN technologies such as LoRa and Sigfox when no error detection and correction is employed. Since, IoT and Machine-to-Machine (M2M) communication demand high reliability, RPW with error correction can significantly enhance the communication reliability for critical IoT and M2M applications. Therefore, this study investigates the performance of RPW with single bit error detection and correction using Hamming codes to avoid substantial overhead. Hamming (7,4) coded RPW shows a remarkable improvement of more than 40% in error performance compared to uncoded RPW thereby making it a suitable candidate for IoT and M2M applications. Error performance of coded RPW outperforms coded Chirp Spread Spectrum (CSS) modulation used in LoRa under multipath conditions by 51%, demonstrating superior adaptability and robustness under dynamic channel conditions. These findings provide valuable insights into the ongoing developments in wireless communication systems whilst reporting Q-RPW model as a new and effective method to address the needs of developing LPWAN and IoT ecosystems.

An efficient high throughput BCH module for multi-bits error correction mechanism on hardware platform

The bose-chaudhuri-hocquenghem (BCH) codes are a cyclic error correction codes (ECC) class. The BCH is constructed by using a polynomial over the Galois field. The BCH codes can detect and correct the multi-bits with an easy decoding mechanism. The BCH codes are used in most of the storage device's cryptography, disk drives, and satellite applications. This manuscript presents an efficient high-throughput BCH module with an encoding and decoding mechanism for multi-bit corrections. The BCH code of (15, k) is used to construct the encoder and decoder architectures. The BCH encoder decoder (ED) module with single error correction (SEC), double error correction (DEC), and triple-error correction (TEC) are discussed in detail. The BCH encoder module uses a linear feedback shift register (LFSR). The BCH decoder with SEC and DEC is constructed using the syndrome generator module (SGM) and chien search module (CSM). The BCH decoder with TEC is designed using SGM, inversion-based berlekamp-massey-algorithm (BMA), and CSMs. The BCH-ED module with SEC, DEC, and TEC utilizes <1 % chip area on Artix-7 FPGA. The BCH-ED with SEC, DEC, and TEC achieves a throughput of 7.13 Gbps, 1.2 Gbps, and 0.803 Gbps, respectively. Lastly, the BCH module is compared with existing BCH approaches with better improvement in chip area, frequency, and throughput parameters.

ПОБУДОВА КОДІВ ХЕММІНГА В СКІНЧЕННИХ ПОЛЯХ ГАЛУА

Hamming codes and their modifications are key in numerous technological processes and systems, where minimizing errors is crucial for enhancing reliability and efficiency in data transmission or storage. They allow for the detection and automatic correction of single errors in each data block. Their relative simplicity to implement at the hardware and software levels, renders them useful in systems demanding high reliability. Moreover, they optimize transmission channel use due to their minimal redundancy. At work is the task of applying the properties of modular arithmetic to develop codes that can effectively correct errors in systems with higher bit rates than binary has been considered. Conducted research confirms that such codes can be tailored to meet specific data transmission system requirements, showcasing adaptability. The use of Hamming codes within finite Galois fields, leveraging modular arithmetic, further enhances correction capabilities and efficiency, streamlining implementation and computation processes. Error correction codes in finite Galois fields use the same principles applied in Hamming codes but take into account the mathematical properties of these fields for effective encoding, detection, and correction of errors.The proposed error correction method, through integration with modular arithmetic, opens possibilities for optimizing encoding and decoding processes, allowing for a higher level of data transmission reliability with minimal redundancy, which was previously limited by the properties of traditional codes. The proposed solution demonstrates the potential for using modular arithmetic for error correction but can provide a basis for further research in this area, opening new possibilities for improving information processing and transmission technologies.

Two-Dimensional Protection Code for Virtual Page Information in Translation Lookaside Buffers

Severe conditions such as high-energy particle strikes may induce soft errors in on-chip memory, like cache and translation lookaside buffers (TLBs). As the key component of virtual-to-physical address translation, TLB directly affects processor performance. To protect the virtual page information stored in TLB, several studies have introduced error detection or correction codes. However, most schemes proposed for data TLB cannot support the detection of multi-bit upsets, which is reported as a serious issue in modern fault-tolerant processors due to the downscaling of CMOS process technology. In this paper, we propose a new two-dimensional protection technique, called the matrix protection tag (MaP-Tag), to provide stronger error detection and correction capability to TLB virtual page information. Our proposal reorganizes virtual page information into a matrix and employs adjacent check bits and interleaved check bits for error detection. The two-dimensional design offers one-bit error detection, burst multi-bit error detection, and even multi-bit error correction in some cases. The simulation results show that our proposal can detect almost all error patterns when injected with up to eight bit-flips. Furthermore, the technique provides a better error correction rate than conventional single error correction (SEC) codes. The reliability calculation shows that our proposal is powerful in both error detection and correction with affordable storage overhead.

CHOICE OF CODE FOR DETECTING ERRORS IN BACKUP CHANNELS OF A DUPLICATED COMPUTER

An analysis of operation and selection of reliability indicators for specialized computers (SEVMs) of aerospace equipment was carried out. The requirements for the methods of redundant computer systems are formulated. A comparative evaluation of the detecting ability and hardware costs in the implementation of the majority method of redundancy, the method of duplication and the use of corrective codes is carried out. The expediency of using the duplication method to increase the probability of failure-free operation and survivability of self-healing digital computers, using algebraic linear codes, to identify a faulty backup channel is substantiated. Unlike the known codes, it is proposed to use an algebraic linear code, in which the values of the check bits correspond to the direct and inverse values of the information bits, which makes it possible to detect errors when reading information from the inverse outputs of the memory, correct single errors, detect double errors and control the logical operation of inverting required to represent a negative number in an additional code, which makes it possible to adapt the code to control the arithmetic and logical operations of the computer processor. The evaluation of the probability of failure-free operation of a duplicated computer, with its general redundancy, with the detection and correction of single errors in the backup memory channels and the detection of errors in the backup channels of the processor ALU based on the proposed code, and the assessment of the probability of failure-free operation of the computer, with its separate redundancy, with error detection in the backup channels of the duplicated memory based on the Hamming code and error correction in the backup channels of the processor ALU based on the majority method. As a result of comparing the probabilities of failure-free operation, it has been established that the total reservation of the computer based on the proposed code, in comparison with the separate reservation of the memory and ALU of the processor of the computer, makes it possible to provide a gain in the probability of failure-free operation of the computer and its functional units throughout the entire period of operation.

Use of information redundancy to increase the reliability of devices for storing, processing and transmitting information

In modern information transmission systems, a special place is occupied by telecommunication systems (TS), which include digital data transmission systems (DSTS) containing specialized computers (SEVMs). The systems under consideration must ensure fast and reliable transmission of discrete data over communication lines. In this case, the loss of even one transmitted character is unacceptable; therefore, the main indicator of the reliability of a computer is the probability of failure-free operation. To increase the probability of failure-free operation of a storage device (MS), corrective codes and duplication are used, and to increase the probability of failure-free operation of the arithmetic-logical unit (ALU) of a computer, majority redundancy is used. The disadvantage of the majority method is the high hardware costs for redundancy, which reduces the efficiency of its use. The disadvantages of using correction codes include: as a rule, they are used for separate redundancy (detection and correction of errors that occur in storage devices; majority redundancy is used to detect and correct errors in the ALU); not all arithmetic and logical operations can be controlled based on existing correcting codes; a sharp increase in hardware costs when using algebraic linear codes to detect and correct multiple errors. Detection of errors in the ALU of a computer processor can be achieved on the basis of duplication in a loaded mode with replacement, however, this is associated with solving the main problem of computer duplication: - selection of monitoring tools for determining a failed channel (detection of errors in storage and information processing devices). The purpose of the research is to develop a scientific and methodological apparatus for computer backup using the duplication method with error detection in backup channels based on the use of an algebraic linear code, which makes it possible to detect errors not only in storage devices, but also adapted for detecting errors when performing arithmetic and logical operations. Results. An analysis of operation and selection of reliability indicators for specialized computers (SEVMs) of telecommunication systems was carried out. Requirements for computer backup methods are formulated. A comparative assessment of the detecting ability and hardware costs was carried out when implementing the majority redundancy method, the duplication method and the use of correcting codes. The expediency of using the duplication method is substantiated to increase the probability of failure-free operation and survivability of self-healing digital computers, using algebraic linear codes to determine the faulty channel, which allows to significantly reduce hardware costs for constructing monitoring equipment and use 10-30% of backup equipment for these purposes. It is proposed to use an algebraic linear code, in which, unlike well-known codes, the values of the check bits correspond to the direct and inverse values of the information bits, which makes it possible to detect errors when reading information from the inverse outputs of the memory, correct single errors, detect double errors and control the logical inversion operation , necessary to represent a negative number in two's complement code, which makes it possible to adapt the code to control arithmetic and logical operations of the computer processor. An assessment was made of the probability of failure-free operation of a duplicated computer, with its general redundancy, with detection and correction of single errors in the backup memory channels and detection of errors in the backup channels of the processor ALU based on the proposed code, and an assessment of the probability of failure-free operation of the computer, with its separate redundancy, with error detection in the backup channels of the duplicated memory based on the Hamming code and error correction in the backup channels of the processor ALU based on the majority method. A comparative assessment of the probabilities of failure-free operation allows us to conclude that the general redundancy of the computer based on the proposed code, in comparison with the separate redundancy of the memory and ALU of the computer processor, allows for a gain in the probability of failure-free operation of the computer and its functional devices throughout the entire period of operation. The practical significance lies in the fact that the proposed scientific and methodological apparatus provides: reduction of hardware costs for identifying a faulty channel when organizing duplication; detection of errors in the memory and ALU of the computer processor with time costs not exceeding the time of error detection when using standard methods of monitoring the computer system.

Notes on the Cambridge translation of Kant’s Religion within the Boundaries of Mere Reason

This article mainly discusses translation issues in the two Cambridge editions of Kant’s Religion, while engaging in a briefer discussion of Pluhar’s translation of the same work. The aim is to correct single errors as well as patterns of questionable translation, and to do so guided by criteria of consistency in relation to Kant’s use of key terms. I argue that the English translations have contributed to misinterpretations of Kant’s philosophy of religion, although I make only passing references to the secondary scholarship.

INTEGER SINGLE-ERROR-CORRECTING CODES AS AN ALTERNATIVE TO THE INTERNET CHECKSUM

The paper considers the possibility of using integer single-error-correcting (SEC) codes instead of the Internet checksum (IC). It is shown that such a replacement can be easily carried out, since the integer SEC codes are a generalization of the IC.

A unified multi-step wind speed forecasting framework based on numerical weather prediction grids and wind farm monitoring data

Wind speed forecasting is the basis of wind farm operation, which provides a reference for the future operation status evaluation of wind farms. For the wind speed forecast of wind turbines in the whole wind farm, a strategy combining unified forecast and single site error correction is proposed in this paper. The unified forecast framework is composed of a unified forecast model and multiple single site error correction models, which combines the forecasted grids of numerical weather prediction (NWP) with the monitoring data of wind farms. The proposed unified forecast model is called spatiotemporal conversion deep predictive network (STC-DPN), which is composed of temporal convolution network (TCN) and 2D convolution long short-term memory network (ConvLSTM). Firstly, the NWP forecasted grids are interpolated to the fan location, and the sequence matrix is composed of the NWP data and the monitored data of each wind turbine according to the time series, which is entered into the TCN network for time sequence feature extraction. Then, the output of the TCN network is converted into a regular spatio-temporal data matrix, which is entered into the ConvLSTM network for joint learning of spatio-temporal features to obtain the wind speed sequence forecasted in the whole wind farm. Finally, an independent TCN-LSTM error correction model is added for each site. Variational modal decomposition (VMD) is used to process data series, and different processing methods are adopted in unified forecast and single site error correction. In the 96 steps forecast test of a wind farm from Jining City, China, the proposed method is superior to several baseline methods and has important practical application value.

Implementation of SEC-DED-DAEC Codes using Mentor Graphics

Correction of a single error Double Error Detection (SEC-DED) and Double Adjacent Error Correction (DAEC) are prominent error correction algorithms used in computer memory systems to detect and fix errors that arise during data transfer. In this research, we want to put these ideas into practice and assess how well they work through simulations and experiments. We will research the trade-offs between these strategies' efficiency and reliability and contrast them with other error correction techniques. Our research will involve designing and putting error detection and correction procedures into circuits and algorithms for DAEC and SEC-DED. We will also investigate other methods, including parallel processing and error checking mechanisms, to enhance the performance of these strategies. Our findings may also have applications in other domains where error correction is important, such as communication systems and medical equipment. They will help us understand and enhance error correction techniques used in computer memory systems.

Impact of Petroleum Energy Price Volatility on Commodity Prices in Ghana

The purpose of this article is to demonstrate the relationship between petroleum energy volatility and commodity prices in Ghana, which are indexed (energy grains, meat, and cooking oil), as well as to provide an empirical specification of the impact's direction. With reference to time series literature, the paper examined energy and commodity price connection models such as augmented dickey fuller, granger causality, co-integration, vector autoregressive and the vector error correction models used in estimating the association among petroleum energy volatility and the three selected commodity variables. The paper found that, there is a long run relationship between petroleum energy volatility and commodity prices in Ghana from 2011 to 2022. A single equation error correction model suggested that, petroleum energy shocks increase prices of grains, meat and cooking oil in both the short and long run. Impulse response function and variance decomposition conducted on the variables also suggested that there is both short and long run association between the variables.

On the Positional Single Error Correction and Double Error Detection in Racetrack Memories

In the era of non-volatile memories, the racetrack memory is a promising technology to pack hundreds of bits in a magnetic nanowire. A solid-state read head is grown alongside the nanowire to sense individual bits which are pushed across the head by a shifting force. However, the probabilistic nature of this shifting movement inflicts positional errors. Therefore, robust and low-cost error correcting codes are essential for a reliable alternative in on-chip memories and storage applications. Recent works focus on Varshamov-Tenengolts (VT) codes which can correct all single bit insertions and deletions. However, VT codes are incapable of detecting multiple deletions/insertions. Because a positional error corrupts multiple data words, multi-bit positional error detection is critical for racetrack memories. In this article, we propose a novel positional single error correction and double error detection (P-SECDED) code in the context of racetrack memories with a single read head. In particular, we adopt a postamble-based approach where a VT-encoded codeword appends a carefully selected bit-pattern, stored on the racetrack. We rigorously analyze the limitations of the postamble method, and deduce a criterion for postamble selection. We further provide a methodology to optimize this postamble selection in order to correct all single-bit errors and as much of two-bit errors as possible. Finally, we prove that all incurable two-bit errors are successfully detected. To the best of our knowledge, this work is the first attempt to provide P-SECDED fault-tolerance to three-dimensional racetrack memories which cannot afford multiple read heads.

Multiple errors correction for position-limited DNA sequences with GC balance and no homopolymer for DNA-based data storage.

Deoxyribonucleic acid (DNA) is an attractive medium for long-term digital data storage due to its extremely high storage density, low maintenance cost and longevity. However, during the process of synthesis, amplification and sequencing of DNA sequences with homopolymers of large run-length, three different types of errors, namely, insertion, deletion and substitution errors frequently occur. Meanwhile, DNA sequences with large imbalances between GC and AT content exhibit high dropout rates and are prone to errors. These limitations severely hinder the widespread use of DNA-based data storage. In order to reduce and correct these errors in DNA storage, this paper proposes a novel coding schema called DNA-LC, which converts binary sequences into DNA base sequences that satisfy both the GC balance and run-length constraints. Furthermore, our coding mode is able to detect and correct multiple errors with a higher error correction capability than the other methods targeting single error correction within a single strand. The decoding algorithm has been implemented in practice. Simulation results indicate that our proposed coding scheme can offer outstanding error protection to DNA sequences. The source code is freely accessible at https://github.com/XiayangLi2301/DNA.

New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application

Multiple cell upset (MCU) caused by cosmic radiation is a serious issue related to the reliability of static random access memories (SRAMs) in space application. Due to radiation, single cell or multiple cells of a memory are corrupted. The chances of errors in more than one memory cells are also increasing due to continuous down scaling of technology. Single error, double or triple adjacent errors are most common in this case. Several error correction codes are already introduced for protecting the memories. But many existing error correcting codes have either higher delay and/or power consumption and/or decoder error rate. In this paper, we have introduced 16-bit, 32-bit and 64-bit information length, uniquely decodable single error correction-double adjacent error correction (SEC-DAEC) and single error correction-double adjacent error correction-triple adjacent error correction (SEC-DAEC-TAEC) codes with lower power consumption and delay. In our design, same H-matrix is used for implementing both SEC-DAEC and SEC-DAEC-TAEC codes. Both FPGA and ASIC based synthesis results show that proposed SEC-DAEC and SEC-DAEC-TAEC codes with dimensions (24, 16), (41, 32) and (75, 64) are better compared to existing same dimension codes with respect to area, power and delay. Since, the proposed SEC-DAEC and SEC-DAEC-TAEC codes have low encoder and decoder delay which corresponds to low writing and reading time, consume significantly low power and have zero decoder error rate, so proposed codec can be used for memories in space application.

Employment to output elasticities and reforms towards flexicurity: Evidence from OECD countries

AbstractLabor market reforms in the direction of “flexicurity” have been widely endorsed as a means to increase an economy's ability to adjust to negative shocks while offering adequate social safety nets. This paper empirically examines how such reforms influence employment's responsiveness to output fluctuations (employment–output elasticity). To address this question, we employ a single equation error correction model with policy interactions on a panel of OECD countries, which also incorporates the period of the Great Recession, and distinguish between passive and active labor market policy types. Flexicurity is represented by three policy measures: unemployment benefit generosity, the flexibility of hiring and firing rules, and spending on active labor market policies. We find that the effects of any single policy change are shaped by the broader existing policy mix within which it takes place. A hypothetical flexicurity reform towards the policy mix of Denmark, a well‐known example of the flexicurity regime, is found to increase or leave unchanged countries' short‐run employment–output elasticities, depending on the initial policy mix. These results are robust to accounting for a large set of additional labor market institutions.

Modified single error correction orthogonal Latin square scheme to reduce parity check bits

Single-error correction (SEC) codes play a critical role in ensuring cache reliability. In ultra-high-speed caches, decoding delay is a key element to consider when selecting an SEC code. Single error correction orthogonal Latin square (SEC OLS) codes have the fastest decoding method. However, these codes impose a higher number of parity check bits compared to other SEC codes. These extra parity bits need to be stored with each data word in cache data array, which increased cache overheads. This may limit their adoption only to applications that can handle such overheads. In this paper, a modified SEC OLS coding scheme is proposed to reduce the number of stored parity check bits. Compared to the original SEC OLS codes, the proposed coding scheme reduces 25% and 31.3% of the stored parity bits when implemented to protect 16-bit and 64-bit data words, respectively. The results of FPGA and ASIC simulation and synthesis show that using the modified SEC to protect 16-bit words can be an attractive solution because it saves a significant amount of parities storage area, while running at a speed comparable to the original SEC OLS code. The implementation of the proposed SEC code to protect 64-bit words may still be suitable for area-sensitive cache applications that can cope with the slightly increased decoding delay.

Design of a 32-Bit, Dual Pipeline Superscalar RISC-V Processor on FPGA: A Review

Abstract: A 40 MHz with 32-bit and 5-stage dual-pipeline superscalar processor based on RISC-V Instruction Set Architecture is presented. It supports integer, multiply-divide and atomic read-modify-write operations. The proposed system implements inorder issuing of instructions. The design includes a dynamic branch prediction unit, memory subsystem with virtual memory, separate instruction cache and data cache, integer and floating-point execution units, interrupt controller, error control module, and a UART peripheral. Individual interrupts can have up to four levels of primary priority set in the interrupt controller. For the main memory, the error control module provides single error correction and double error detection. For on-chip communication, the Wishbone B.3 bus standard is used. On a Virtex-7 XC7VX485T FFG 1761-2 FPGA-based board, the processor is implemented. The architecture has CoreMark and Dhrystone benchmark ratings of 3.84/MHz and 1.0603 DMIPS/MHz, respectively

Two-Dimensional Error Correction Code for Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) Caches

Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) is an emerging nonvolatile memory (NVM) technology that can replace conventional cache memory in computer systems. STT-RAM has many desirable properties such as high writing and reading speed, non-volatility, and low power consumption. Since the cache requires a high speed of writing and reading speed, a single-error correction and double error detection (SEC - DED) are applicable to improve the reliability of the cache. However, the process variation and thermal fluctuation of STT-MRAM cause errors. For example, writing ‘1’ bits has more errors than writing ‘0’ bits. We then design the weight reduction code to reduce the error caused by writing ‘1’ bits. Moreover, the performance of an SEC-DED code is improved by constructing an SED-DED code as the product code. The simulation results demonstrate that the two-dimensional error correction code consisting of product code and weight reduction code is roughly 5.67 × 10−4 lower than the SEC-DED code when the error rate of writing ‘1’ bits is equal to 6 × 10−3.

Bidirectional wireless power/data transfer via magnetic field

Recently, inductive power transfer (IPT) system has been used for wireless charging of electric vehicles (EVs). However, most of them only treat the issue of single directional wireless power transfer (WPT). This research proposes a novel bi-directional IPT (BD-IPT) scheme EVs, which can simultaneously transmit power/data via magnetic field when the mutual inductance changes. For power transmission, resonant inverters with phase-shift pulse width modulation (PSPWM) are used to generate carrier waves and alternating current. As for data transmission, a dedicated communication method with the accompanied protocol is proposed. Binary phase shift keying (BPSK) is used to simulate the two-quadrature amplitude modulation (QAM), which generates digital signals for data transmission without the need of extra communication links. Hamming codes are combined with single-error correction and double-error detection (SECDED) to ensure communication quality.