CORDIC Rotation Research Articles

Enhanced CORDIC Based Rotator Design for Sinusoidal Transforms

Transforms play an important role in conversion of information from one domain to the other. To be more specific transforms like Discrete Fourier transform (DFT) and Discrete Cosine transform (DCT) helps us to migrate from one time domain to frequency domain based on the basis function selected. The basis function of the every sinusoidal transform carries out a circular rotation to convert information from one domain to the other. There are applications related to communication which requires this rotation into the hyperbolic trajectory as well. Multiplierless algorithm like CORDIC improves the latency of the transforms by eliminating the number of multipliers in the basis function. In this paper we have designed and implemented enhanced version of CORDIC based Rotator design. The Enhanced version is simulated for order 1 to order 36 to emphasize on the results of the proposed algorithm. Results shows that the enhanced CORDIC rotator design surpasses the Mean square error after the order 18 compared to standard CORDIC. Unified CORDIC also can be implemented using the said algorithm to implement different three trajectories.

A 1-V to 0.29-V sub-100-pJ/operation ultra-low power fast-convergence CORDIC processor in 0.18-μm CMOS

In this paper, an ultra-low power fast-convergence CORDIC processor is proposed for power-constrained applications. Existing fast-convergence CORDIC methods are reviewed. Effective design techniques are proposed to maximize the energy efficiency of the proposed CORDIC processor from algorithm, architecture, to circuit levels. At the algorithm level, an efficient Pipeline Angle Recoding method is proposed to not only significantly reduce the redundant iterations by more than 50%, but also balance the computation load between the optimum angle selection and elementary angle rotation. At the architecture level, efficient pipeline operation is implemented to achieve near 100% hardware utilization and scaling operation during rotations, by scheduling and balancing the pipeline operations between the optimum angle selection unit and the main CORDIC rotation unit with in-rotation scaling logic. The optimum angle selection enable fast-convergence computation and reduce dynamic energy significantly, while the balanced pipeline operation maximize the hardware utilization and also minimize the leakage energy especially at ultra-low voltages in sub/near-threshold regions. Silicon measurement results show that the proposed CORDIC processor fabricated in 0.18-μm CMOS technology can operate from 1 V down to 0.25 V and achieve ultra-low energy consumption at sub-100 pJ when operating in the near/sub-threshold region from 0.57 V to 0.25 V, which is suitable for middle- and low-data rate power-constrained applications. Compared with the conventional design at 1.8 V, the proposed ultra-low voltage CORDIC processor design achieves a 30× reduction in energy consumption and only consumes 35 pJ per CORDIC operating at the minimum energy point of 30 kHz and 0.29 V, making it very suitable for stringently power-constrained applications including wearable healthcare and remote environmental monitoring applications.

Highly-Flexible and Optimized, Area: and Energy-Efficient Matrix Decomposition Accelerators based on Givens Algorithms and CORDIC Rotations

Matrix decomposition accelerators are attractive SoC components for many applications with a wide range of specifications. In this work, a new family of highly area- and energy-efficient modular matrix decomposition architectures based on the givens-algorithms and CORDIC rotations are elaborated. Accurate algebraic cost models enable for early cost estimation as well as for cross-level optimization over architecture, micro-architecture and circuit-level using a rich set of parameters. Quantitative results for an exemplary QRD application, implemented in 40-nm CMOS technology, are presented.

Reconfigurable data parallel constant geometry fast Fourier transform architectures on Network-on-Chip

This paper reports the design and development of reconfigurable (up to 8192-point), data parallel, constant geometry fast Fourier transform (CG-FFT) architectures based on Network-on-Chip (NoC) paradigm. Twiddle factor multiplications have been realized using pipelined CORDIC rotators in the proposed architecture in order to ensure its high throughput. Mapping of FFT functions to cores has been done by considering the proposed signal flow graph (SFG) for CG-FFT architecture, which helps in optimizing the design of network components (routers and network interfaces) and reducing the latency of FFT computation. The proposed input-size aware architecture can withstand faults in other processing elements (PEs) as it can accomplish the entire FFT computation using only one PE as well. When mapped onto mesh based NoC, the proposed architectures could achieve reduction in latency by 5×, compared to several existing FFT architectures on NoC. Hardware realization of the PE and the network components of the proposed architectures have been done using Xilinx Kintex-7 family field-programmable gate array (FPGA) device. The maximum operating frequency of a PE in the proposed architecture has been found to be 184.010 MHz, which meets the timing specifications of several application standards, such as DVB-T/H, DAB, 802.11a/n and UWB. In addition to the FPGA-prototype, the proposed architectures have also been synthesized in ASIC design flow to obtain area and power results.

A Family of Modular QRD-Accelerator Architectures and Circuits Cross-Layer Optimized for High Area- and Energy-Efficiency

QR-decomposition accelerators are attractive SoC components for many applications with a wide range of specifications. A new family of highly area- and energy-efficient, modular two-way linear-array QRD architectures based on the Givens algorithm and CORDIC rotations is proposed. The template architecture allows for implementations of real-/complex-valued and integer/floating-point QRDs. An accurate algebraic cost model enables cross-layer optimization over architecture, micro-architecture and circuit level using a rich set of parameters. Quantitative results for exemplary applications are presented for implementations in 40-nm CMOS, proving the significant improvement of efficiency.

Effective Processor Architecture for Matrix Decomposition

The singular value decomposition (SVD) and the QR decomposition (QRD) are two prominent matrix decomposition algorithms used in various signal and image processing applications. In this paper, new CORDIC-like algorithms for fast SVD and QRD have been proposed to speed up those processes. The proposed algorithms are based on the Kronecker (tensor) product (KP) of rotation matrices. This product allows implementing multi-angular transformations simultaneously as integrated macro-operation with execution time similar to the CORDIC rotation. The proposed algorithms lead to appreciable improvements in terms of processor area–time.

FPGA IMPLEMENTATION OF CORDIC ALGORITHM FOR FINGER PRINT RECOGNITION APPLICATIONS

Finger print recognition process involves many trigonometric evolutions. CORDIC based evolution of trigonometric functions is possible. In this paper CORDIC based architecture is proposed to evaluate the trigonometric or inverse trigonometric functions like sinθ, cosθ. Proposed architecture is partitioned into two main blocks: Magnitude generator and CORDIC processor. Magnitude generator outputs the value of the trigonometric function by driving the CORDIC processor. CORDIC processor executes the CORDIC rotations. Architecture Proposed in this paper is implemented using XILINX 13.2. Performance of the architecture is analyzed by calculating the relative error and resource utilization summery is reported.

Low Cost CORDIC-Based Configurable FFT/IFFT Processor for OFDM Systems

High-performance FFT processor is indispensable for real-time OFDM communication systems. This paper presents a CORDIC based design of variable-length FFT processor which can perform various FFT lengths of 64/128/256/512/1024/2048/4096/8192-point. The proposed FFT processor employs memory based architecture in which mixed radix 4/2 algorithm, pipelined CORDIC, and conflict-free parallel memory access scheme are exploited. Besides, the CORDIC rotation angles are generated internally based on the transform of butterfly counter, which eliminates the need of ROM making it memory-efficient. The proposed architecture has a lower hardware complexity because it is ROM-free and with no dedicated complex multiplier. We implemented the proposed FFT processor and verified it on FPGA development platform. Additionally, the processor is also synthesized in 0.18μm technology, the core area of the processor is 3.47mm2 and the maximum operating frequency can be up to 500MHz. The proposed FFT processor is better trade off performance and hardware overhead, and it can meet the speed requirement of most modern OFDM system, such as IEEE 802.11n, WiMax, 3GPP-LTE and DVB-T/H.

FPGA Implementation of SDR Based CFO Estimation and Compensation Circuit for OFDM System

Based on software defined radio (SDR) architecture, this paper develops a reconfigurable CORDIC vectoring module (CVM) and CORDIC rotation module (CRM) in FPGA to implement the carrier frequency offset (CFO) estimation and compensation circuits of an orthogonal frequency division multiplexing (OFDM) system. The experimental results show that the proposed SDR-pipelined architecture can save power and hardware resource compared with conventional pipelined architecture, because the designed CVM and CRM modules can be reused in the processing modules of CFO estimation and compensation circuit. The performance trade-off for CVM and CRM implemented with different quantized float number in FPGA is presented. Furthermore, the hardware reconfiguration function of CVM and CRM is also validated.

A Two-Step CORDIC Rotation Algorithm with Pre-Coded Scale Factors

CORDIC algorithm has been widely used for efficient implementation of vector rotation operations in hardware.However,it's hard to achieve small iteration numbers while not compromising the ease of scale factor computing and compensation.This paper proposes a novel table-driven CORDIC rotation algorithm with predictable scale factors and short pipelines.It maps the input angle during into and generates signals to modify the initial iteration value and control the rotation direction.The rotation process is composed of two steps.The coefficients and scale factors of step1 are acquired through lookup table indexed by the MSB(Most Significant Bits) of the mapped angle.After large-angle rotations of step1,the residual angle is brought into the convergence region of step2.The iteration of step2 is scaling-free,with the coefficients directly gotten from the binary representation of the residual angle.During such two processes,no further arithmetic computation in the angle approximation(z datapath) and scale factor computing datapath is required.The coefficients of step1 are generated by our angle decomposition algorithm,with two coefficients in one group,at most one non-zero value each group,and the scale factors are pre-computed and coded with radix-4 Booth recoding algorithm.In addition,some adjacent simple micro rotations are combined into one.All these techniques effectively reduce the iteration number,which is also beneficial to high accuracy due to less rounding errors.Moreover,the algorithm uses carry-save adders to accumulate three operands and omits expressions of machine zero,which reduces the latency and complexity of the system greatly.The MSB indexed lookup table gets over the poor scalability of full-word indexed lookup table,and entries grow slowly with accuracy.When using 28-bit datapath,the algorithm requires 38% less pipeline stages and 27.9% less area consumption compared to those of the conventional CORDIC,while achieving 3 more bits accuracy,which shows great performance superiority.

Decimal CORDIC Rotation based on Selection by Rounding: Algorithm and Architecture

Hardware implementation of decimal floating-point arithmetic is a topic of great interest among the researchers in computer arithmetic and also the digital processor industry. Software packages for decimal arithmetic are actually being challenged by decimal hardware units. This spreading trend seems to include hardware implementation of elementary functions. The (Coordinate Rotation Digital Computer) CORDIC algorithm, due to its simplicity, is one of the most efficient methods for computing elementary functions. In this work, we develop a decimal CORDIC scheme with almost half number of equally long cycles with respect to the best previous design. This is achieved via retiming of the conventional CORDIC architecture and selection of the microrotation factors by rounding. However, the proposed design does not lead to a predetermined constant scaling factor. The solution that we use is to iteratively compute the logarithm of the scaling factor followed by a decimal exponentiation. The same CORDIC hardware is reused for performing the latter. The proposed CORDIC method requires 2n + 3 cycles for n-digit decimal operands vs. 4n cycles of the previous methods. Evaluations with 16-digit operands based on logical effort analysis conclude that the proposed architecture shows 82% speed advantage, at the cost of 60% more area and 2.5Â KB more ROM.

Implementation of the Trigonometric LMS Algorithm using original CORDIC ROTATION

The LMS algorithm is one of the most successful adaptive filtering algorithms. It uses the instantaneous value of the square of the error signal as an estimate of the mean-square error (MSE). The LMS algorithm changes (adapts) the filter tap weights so that the error signal is minimized in the mean square sense. In Trigonometric LMS (TLMS) and Hyperbolic LMS (HLMS), two new versions of LMS algorithms, same formulations are performed as in the LMS algorithm with the exception that filter tap weights are now expressed using trigonometric and hyperbolic formulations, in cases for TLMS and HLMS respectively. Hence appears the CORDIC algorithm as it can efficiently perform trigonometric, hyperbolic, linear and logarithmic functions. While hardware-efficient algorithms often exist, the dominance of the software systems has kept those algorithms out of the spotlight. Among these hardware- efficient algorithms, CORDIC is an iterative solution for trigonometric and other transcendental functions. Former researches worked on CORDIC algorithm to observe the convergence behavior of Trigonometric LMS (TLMS) algorithm and obtained a satisfactory result in the context of convergence performance of TLMS algorithm. But revious researches directly used the CORDIC block output in their simulation ignoring the internal step-by-step rotations of the CORDIC processor. This gives rise to a need for verification of the convergence performance of the TLMS algorithm to investigate if it actually performs satisfactorily if implemented with step-by-step CORDIC rotation. This research work has done this job. It focuses on the internal operations of the CORDIC hardware, implements the Trigonometric LMS (TLMS) and Hyperbolic LMS (HLMS) algorithms using actual CORDIC rotations. The obtained simulation results are highly satisfactory and also it shows that convergence behavior of HLMS is much better than TLMS.

Convolution-Based Trigonometric Interpolation of Band-Limited Signals

This paper presents a method to obtain a trigonometric polynomial that accurately interpolates a given band-limited signal from a finite sequence of samples. The polynomial delivers accurate approximations in the range covered by the sequence, except for a short frame close to the range limits. Besides, its accuracy increases exponentially with the frame width. The method is based on using a band-limited window in order to reduce the truncation error of a convolution series. It is shown that the polynomial can be efficiently constructed and evaluated using algorithms designed for the discrete Fourier transform (DFT). Specifically, two basic procedures are presented, one based on the fast Fourier transform (FFT), and another based on a recursive update algorithm for the short-time FFT. The paper contains three applications. The first is a variable fractional delay (VFD) filter, which consists of a short-time FFT combined with the evaluation of a trigonometric polynomial. This filter has low complexity and can be implemented using CORDIC rotations. The second is the interpolation of nonuniform Fourier summations, where the proposed method eliminates the need to interpolate any kernel sample. Finally, the third can be viewed as a generalization of the FFT convolution algorithm and makes it possible to interpolate the output of an finite-impulse-response (FIR) filter efficiently.

A 380 MHz Direct Digital Synthesizer/Mixer With Hybrid CORDIC Architecture in 0.25 $\mu{\hbox {m}}$ CMOS

The paper describes the implementation of a 380 MHz, 13 bit, direct digital synthesizer/mixer IC in 0.25mum CMOS technology. The circuit employs an innovative architecture which divides the pi/4 rotation operation required in the quadrature synthesizer/mixers, in three rotations. The first two rotations are implemented by using a CORDIC datapath completely realized in carry-save arithmetic. The directions of the CORDIC rotations are computed in parallel by using a little lookup table, for the first rotation, and a multiply by constant and addition circuit for the second rotation. The final (third) rotation is multiplier-based, in order to reduce the circuit latency and increase the circuit performances. The CORDIC datapath is implemented with a novel approach both at the algorithmic level and at the transistor level. At the algorithmic level the combined employ of sign-extension prevention, overflow prevention and a novel rounding scheme are presented. At the transistor level a design style that jointly uses full-CMOS and DPL to improve the circuit latency is described. The overall circuit performances are very interesting. The synthesizer/mixer IC, realized in a 0.25 mum CMOS technology, has an area occupation of 0.22 mm2 and dissipates 152 mW at 380 MHz with a supply voltage of 2.5 V

Memory-efficient and high-speed split-radix FFT/IFFT processor based on pipelined CORDIC rotations

The author presents a CORDIC-based split-radix fast Fourier transform (FFT)/inverse FFT (IFFT) processor dedicated to the computation of 2048/4096/8192-point discrete Fourier transforms (DFTs). The arithmetic unit of a butterfly processor and a twiddle factor generator are based on a CORDIC algorithm. An efficient implementation of the CORDIC-based split-radix FFT algorithm is demonstrated. The chip of 2048/4096/8192-point FFT/IFFT core processor is fabricated in a 0.18 µm CMOS technology. The core size is 4860×7883 µm2 and contains about 200 822 gates for logic and memory, and the power dissipation is 350 mW with a clock rate of 150 MHz at 1.8 V. All control signals are generated internally on-chip. The processor performs 8192-point FFT/IFFT every 138 µs and 2048-point FFT/IFFT every 34.5 µs, respectively, which exceeds orthogonal frequency division multiplexer symbol rates. The modified-pipelining CORDIC arithmetic unit is employed for complex multiplication. A CORDIC twiddle factor generator is proposed and implemented for reducing the size of ROM required for storing the twiddle factors. Compared with conventional FFT implementations, the power consumption is reduced by 25%.

A trigonometric formulation of the LMS algorithm for realization on pipelined CORDIC

This paper presents an alternate formulation of the least mean square (LMS) algorithm by using a set of angle variables monotonically related to the filter coefficients. The algorithm updates the angles directly instead of the filter coefficients and relies on quantities that can be realized by simple CORDIC rotations. Two architectures based on pipelined CORDIC unit are proposed which achieve efficiency either in time or in area. Further simplifications result from extending the approach to the sign-sign LMS algorithm. An approximate convergence analysis of the proposed algorithm, along with simulation results showing its convergence characteristics are presented.

Very-High Radix CORDIC Rotation Based on Selection by Rounding

A very-high radix algorithm and implementation for CORDIC rotation in circular and hyperbolic coordinates is presented. The selection function consists of rounding the residual. It is shown that this assures convergence from the second iteration on. For the first iteration, the selection is done by table, using a lower radix than for the remaining iterations. The compensation of the variable scale factor is done by computing the logarithm of the scale factor and performing the compensation by an exponential. Estimations of the delay for 32-bit and 64-bit precision show a substantial speed up when compared to low radix implementations. The proposed algorithm is also compared with previously proposed very-high radix ones, and significant advantages are identified.

Application Specific Efficient VLSI Architectures for Orthogonal Single- and Multiwavelet Transforms

In this paper, efficient VLSI architectures for orthogonal wavelet transforms with respect to common applications are presented. One class of orthogonal wavelet transforms is the singlewavelet transform which is based on one scaling and one wavelet function. An important application of this transform is signal denoising for which an efficient VLSI implementation and layout is derived in this paper. Contrary to singlewavelets, orthogonal multiwavelets are based on several scaling and wavelet functions. Since they allow properties like compact support, regularity, orthogonality and symmetry, simultaneously, being impossible in the singlewavelet case, multiwavelets are well suited bases for image compression applications. With respect to an efficient implementation of these orthogonal wavelet transforms, approximations of the exact rotation angles of the corresponding wavelet lattice filters are used. The approximations are realized by elementary CORDIC rotations. This method reduces the number of shift and add operations significantly with no influence on the good performance of the transforms. VLSI architectures for the computationally cheap transforms and related implementation aspects are discussed and design examples from architectural level down to layout are given.

Double step branching CORDIC: a new algorithm for fast sine and cosine generation

Duprat and Muller (1993) introduced the ingenious "Branching CORDIC" algorithm. It enables a fast implementation of CORDIC algorithm using signed digits and requires a constant normalization factor. The speedup is achieved by performing two basic CORDIC rotations in parallel in two separate modules. In their method, both modules perform identical computation except when the algorithm is in a "branching" [1]. We have improved the algorithm and show that it is possible to perform two circular mode rotations in a single step, with little additional hardware. In our method, both modules perform distinct computations at each step which leads to a better utilization of the hardware and the possibility of further speedup over the original method. Architectures for VLSI implementation of our algorithm are discussed.

VLSI systolic arrays for adaptive nulling [radar

Presents a case study of the design of a computationally intensive system to do adaptive nulling of interfering signals for a phased-array radar with many antenna elements. The goal of the design was to increase the computational horsepower available for this problem by about three orders of magnitude under the tight constraints of size, weight and power which are typical of an orbiting satellite. By combining the CORDIC rotation algorithm, systolic array concepts, Givens transformations, and restructurable VLSI, we built a system as small as a package of cigarettes, but capable of the equivalent of almost three billion operations per second. Our work was motivated by the severe limitations of size, weight and power which apply to computation aboard a spacecraft, although the same factors impose costs which are worth reducing in other circumstances. For an array of N antennas, the cost of the adaptive nulling computation grows as N/sup 3/, so simply using more resources when N is large is not practical. The architecture developed, called MUSE (matrix update systolic experiment) determines the nulling weights for N=64 antenna elements in a sidelobe cancelling configuration. After explaining the antenna nulling system, we discuss another DSP computation that might benefit from similar architecture, technology, or algorithms: the solution of Toeplitz linear equations.