CORDIC Processor Research Articles

A NewSpeed Power Area and Accuracy (SPAA) Aware Cordic Processing Unit By Vedic Mathematics For The Application of Computer Vision

we are living in the era of fast processing applications like 3D, 5G, 9D. These types of application need a processing unit which have separate arithmetic unit & separate trigonometric unit which is well known as CORDIC processing unit. As we know Graphics processing unit is the brain of any graphics systems now a days there is Gaming specific systems are available which require ultra-high-speed GPU on those GPU there is separate trigonometric calculation processing unit is there which is called CORDIC. So, in this paper basically we proposed a novel architecture of CORDIC unit which is able to give the output in very less time. In this paper we also try to do the justice with the speed power area and accuracy Metrix.

Scale Factor and Latency Analysis in CORDIC Processing Unit

Virtual laptop, cordic or synchronized, is a fast, quick, environmentally friendly algorithm for many applications used for the processing of digital signs. It typically uses an exquisite computing technique for the fixation of the trigonometrically relationships worried aboutrotation around plane coordinates and rectangular to polar shapeconversion, developed for actual airborne calculations. It contains a one-of-a-kind serial mathematics unit having 3 shift registers, 3 adders/sub tractors, appearance-up table and remarkable interconnections.

WITHDRAWN: Image processing by CORDIC processing unit: A computer vision perspective

Abstract As we know, the world today is based on 5G and 3D technology, where everyone needs a fast processing unit for mobile applications. CORDIC is an approach that is capable of performing trigonometric calculations in a fraction of time. As for the old processing unit, they have only a computing unit which contains only ALU, but which is not sufficient for the rapid processing of the trigonometric function, so that the CORDIC algorithm is converted into a CORDIC processor which is capable of fast processing. In this paper, we conducted a comparative detailed study of the previous existing CORDIC algorithm and the CORDIC processing unit. In this we also did a comparative analysis of the system level and a comparative assessment based entirely on algorithm and structure level, primarily based on the parameters.

Generation scheme of chirp scaling phase functions based on floating‐point CORDIC processor

This study presents a chirp scaling (CS) phase function generation scheme based on CORDIC algorithm, it adopts single precision floating-point CORDIC processor to implement a variety of non-linear operations which are involved in CS synthetic aperture radar (SAR) imaging algorithm. We extend the range of convergence of CORDIC algorithm and reduce the data width in rotation unit module by adopting a hardware resource reduction scheme. We also adopt a unified CORDIC processor to achieve square root, multiplication, and division operation, which can substitute multiple single-function processors and simplify the complicate arithmetic in CS algorithm. As a proof of concept, we verify the performance of the proposed design scheme on Xilinx XC7VX690T FPGA platform, it is also applied to 16384 × 16384 points target SAR imaging system, the FPGA resource occupancy of the CS phase function generation module demonstrates that the usage of CORDIC processor can effectively save the consumption of hardware resources, and the maximum operating frequency is acceptable. The accuracy of phase functions can satisfy the engineering requirements.

A 1-V to 0.29-V sub-100-pJ/operation ultra-low power fast-convergence CORDIC processor in 0.18-μm CMOS

In this paper, an ultra-low power fast-convergence CORDIC processor is proposed for power-constrained applications. Existing fast-convergence CORDIC methods are reviewed. Effective design techniques are proposed to maximize the energy efficiency of the proposed CORDIC processor from algorithm, architecture, to circuit levels. At the algorithm level, an efficient Pipeline Angle Recoding method is proposed to not only significantly reduce the redundant iterations by more than 50%, but also balance the computation load between the optimum angle selection and elementary angle rotation. At the architecture level, efficient pipeline operation is implemented to achieve near 100% hardware utilization and scaling operation during rotations, by scheduling and balancing the pipeline operations between the optimum angle selection unit and the main CORDIC rotation unit with in-rotation scaling logic. The optimum angle selection enable fast-convergence computation and reduce dynamic energy significantly, while the balanced pipeline operation maximize the hardware utilization and also minimize the leakage energy especially at ultra-low voltages in sub/near-threshold regions. Silicon measurement results show that the proposed CORDIC processor fabricated in 0.18-μm CMOS technology can operate from 1 V down to 0.25 V and achieve ultra-low energy consumption at sub-100 pJ when operating in the near/sub-threshold region from 0.57 V to 0.25 V, which is suitable for middle- and low-data rate power-constrained applications. Compared with the conventional design at 1.8 V, the proposed ultra-low voltage CORDIC processor design achieves a 30× reduction in energy consumption and only consumes 35 pJ per CORDIC operating at the minimum energy point of 30 kHz and 0.29 V, making it very suitable for stringently power-constrained applications including wearable healthcare and remote environmental monitoring applications.

Implementation of Fingerprint Based Biometric System Using Optimized 5/3 DWT Architecture and Modified CORDIC Based FFT

The real-time biometric systems are used to authenticate persons for wide range of security applications. In this paper, we propose implementation of fingerprint-based biometric system using Optimized 5/3 DWT architecture and Modified CORDIC-based Fast Fourier Transform (FFT). The Optimized 2D-DWT architecture is designed using Optimized 1D-DWT architectures, Memory Units and novel Controller Unit which is used to scan rows and columns of an image. The database fingerprint image is applied to the proposed Optimized 2D-DWT architecture to obtain four sub-bands of LL, LH, HL and HH. The efficient architecture of FFT is designed by using Modified CORDIC processor which generates twiddle factor angles of range $$0^{\circ }$$ – $$360^{\circ }$$ using Pre-processing Unit and Comparator Block. Further, the LL sub-band coefficients are applied to the Modified CORDIC based FFT to generate final fingerprint features. The test fingerprint features are obtained by repeating the same procedure and are used to match the database fingerprint image features using Euclidean Distance. The performance parameters of proposed architecture in terms of area utilization, speed and accuracy is compared with existing architecture to validate the obtained results.

Hardware‐efficient frequency offset and phase noise mitigation in coherent optical quadrature amplitude modulation systems

A hardware-efficient adaptive algorithm for frequency offset and phase noise mitigation in coherent optical quadrature amplitude modulation systems is presented and analysed. Hardware efficiency for the mitigation of imperfections is achieved by computing directly the complex exponential, thus avoiding a CORDIC processor in the phase recovery loop. The design includes a square-root- and trigonometry-free update. Simulation results substantiate the theoretical findings.

Parallel Jacobi EVD Methods on Integrated Circuits

Design strategies for parallel iterative algorithms are presented. In order to further study different tradeoff strategies in design criteria for integrated circuits, A 10 × 10 Jacobi Brent-Luk-EVD array with the simplified μ-CORDIC processor is used as an example. The experimental results show that using the μ-CORDIC processor is beneficial for the design criteria as it yields a smaller area, faster overall computation time, and less energy consumption than the regular CORDIC processor. It is worth to notice that the proposed parallel EVD method can be applied to real-time and low-power array signal processing algorithms performing beamforming or DOA estimation.

Design of High Performance Fixed Point CORDIC Processor

To meet the demand for aerospace applications, high-speed computing transcendental functions such as trigonometric functions, we design a high-speed full-parallel CORDIC processor. On this basis,combining the optimized algorithm of simplifing pathway and adding-bits high-precision method , the original design has been improved. The experimental results show that improved design reduces hardware overhead compared to adding-bits high-precision design,and improves accuracy compared to fully parallel design. This high-speed fixed-point CORDIC has high precision and is suitable for high-speed applications in computing trigonometric and inverse trigonometric functions.

DESIGNING OF CORDIC PROCESSOR IN VERILOG USING XILINX ISE SIMULATOR

In this paper, designing of CORDIC Processor in Verilog to determine the sine and cosine of a given argument, and extending this code to determine the Cartesian co-ordinates of a complex number represented in Euler’s form. The inputs given are the Cartesian vector and the input angle in 17- bit signed number representation. The outputs obtained are sine and cosine of the input angle. To determine the Cartesian co-ordinates of the complex number, the magnitude of the complex number is given as input along with the input angle. The language used for the designing of CORDIC Processor is Verilog. The software used for the simulation is Xilinx ISE Simulator.

Singular value decomposition using an array of CORDIC processors

This paper describes a novel mode of operation of an array of CORDIC processors whereby a pair of complex vectors is made orthogonal using a simple, direct procedure in which rotation angles do not need to be evaluated. By this means, singular value decomposition (SVD) of a complex matrix can be achieved using the one-sided Jacobi method described by Hestenes. The procedure provides an efficient and economical implementation of SVD for use in MIMO precoding and other real-time signal processing tasks involving small matrices of complex elements.

A Modified CORDIC Processor for Specific Angle Rotation based Applications

A Modified CORDIC Processor for Specific Angle Rotation based Applications

64-Channel UWB Wireless Neural Vector Analyzer SOC With a Closed-Loop Phase Synchrony-Triggered Neurostimulator

An ultra wideband (UWB) 64-channel responsive neural stimulator system-on-chip (SoC) is presented. It demonstrates the first on-chip neural vector analyzer capable of wirelessly monitoring magnitude, phase and phase synchronization of neural signals. In a closed-loop, abnormal phase synchrony triggers the programmable-waveform biphasic current-mode neural stimulator. To implement these functionalities, the SoC integrates 64 neural recording amplifiers with tunable switched-capacitor (SC) bandpass filters, 64 multiplying 8-bit SAR ADCs, 64 programmable 16-tap FIR filters, a tri-core CORDIC processor, 64 biphasic current stimulation channels, and a 3.1-10.6 GHz UWB wireless transmitter onto a 4 mm × 3 mm 0.13 μm CMOS die. To minimize both the area and power dissipation of the SoC, the SAR ADC is re-used as a multiplier for FIR filtering and as a DAC and duty cycle controller for the biphasic neural stimulator. The SoC has been validated in the early detection and abortion of seizures in freely moving rodents on-line and in early seizure detection in humans off-line.

FPGA IMPLEMENTATION OF CORDIC ALGORITHM FOR FINGER PRINT RECOGNITION APPLICATIONS

Finger print recognition process involves many trigonometric evolutions. CORDIC based evolution of trigonometric functions is possible. In this paper CORDIC based architecture is proposed to evaluate the trigonometric or inverse trigonometric functions like sinθ, cosθ. Proposed architecture is partitioned into two main blocks: Magnitude generator and CORDIC processor. Magnitude generator outputs the value of the trigonometric function by driving the CORDIC processor. CORDIC processor executes the CORDIC rotations. Architecture Proposed in this paper is implemented using XILINX 13.2. Performance of the architecture is analyzed by calculating the relative error and resource utilization summery is reported.

A Low-Latency Low-Power QR-Decomposition ASIC Implementation in 0.13 $\mu{\rm m}$ CMOS

This paper presents a hybrid QR decomposition (QRD) design that reduces the number of computations and increases their execution parallelism by using a unique combination of Multi-dimensional Givens rotations, Householder transformations and conventional 2-D Givens rotations. A semi-pipelined semi-iterative architecture is presented for the QRD core, that uses innovative design ideas to develop 2-D, Householder 3-D and 4-D/2-D configurable CORDIC processors, such that they can perform the maximum possible number of vectoring and rotation operations within the given number of cycles, while minimizing gate count and maximizing the resource utilization. Test results for the 0.3 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm mm}^{2}$</tex></formula> QRD chip, fabricated in 0.13 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\mu{\rm m}$</tex></formula> 1P8M CMOS technology, demonstrate that the proposed design for 4 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,\times\,$</tex> </formula> 4 complex matrices attains the lowest reported processing latency of 40 clock cycles (144 ns) at 278 MHz and dissipates 48.2 mW at 1.3 V supply and 25 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{\circ}{\rm C}$</tex> </formula> . It outperforms all of the previously published QRD designs by offering the highest QR processing efficiency.

Scale-Free Hyperbolic CORDIC Processor and Its Application to Waveform Generation

This paper presents a novel completely scaling-free CORDIC algorithm in rotation mode for hyperbolic trajectory. We use most-significant-1 bit detection technique for micro-rotation sequence generation to reduce the number of iterations. By storing the sinh/cosh hyperbolic values at octant boundaries in a ROM, we can extend the range of convergence to the entire coordinate space. Based on this, we propose a pipeline hyperbolic CORDIC processor to implement a direct digital synthesizer (DDS). The DDS is further used to derive an efficient arbitrary waveform generator (AWG), where a pseudo-random number generator modulates the linear increments of phase to produce random phase-modulated waveform. The proposed waveform generator requires only one DDS for generating variety of modulated waveforms, while existing designs require separate DDS units for different type of waveforms, and multiple DDS units are required to generate composite waveforms. Therefore, area complexity of existing designs gets multiplied with the number of different types waveforms they generate, while in case of proposed design that remains unchanged. The proposed AWG when mapped on Xilinx Spartan 2E device, consumes 1076 slices and 2016 4-input LUTs. The proposed AWG involves significantly less area and lower latency, with nearly the same throughput compared to the existing CORDIC-based designs.

A New Memory Reduced Radix-4 CORDIC Processor For FFT Operation

A New Memory Reduced Radix-4 CORDIC Processor For FFT Operation

Low complexity VLSI implementation of CORDIC-based exponent calculation for neural networks

This article presents a low hardware complexity for exponent calculations based on CORDIC. The proposed CORDIC algorithm is designed to overcome major drawbacks (scale-factor compensation, low range of convergence and optimal selection of micro-rotations) of the conventional CORDIC in hyperbolic mode of operation. The micro-rotations are identified using leading-one bit detection with uni-direction rotations to eliminate redundant iterations and improve throughput. The efficiency and performance of the processor are independent of the probability of rotation angles being known prior to implementation. The eight-staged pipelined architecture implementation requires an 8 × N ROM in the pre-processing unit for storing the initial coordinate values; it no longer requires the ROM for storing the elementary angles. It provides an area-time efficient design for VLSI implementation for calculating exponents in activation functions and Gaussain Potential Functions (GPF) in neural networks. The proposed CORDIC processor requires 32.68% less adders and 72.23% less registers compared to that of the conventional design. The proposed design when implemented on Virtex 2P (2vp50ff1148-6) device, dissipates 55.58% less power and has 45.09% less total gate count and 16.91% less delay as compared to Xilinx CORDIC Core. The detailed algorithm design along with FPGA implementation and area and time complexities is presented.

Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection

This paper presents an area-time efficient CORDIC algorithm that completely eliminates the scale-factor. By suitable selection of the order of approximation of Taylor series the proposed CORDIC circuit meets the accuracy requirement, and attains the desired range of convergence. Besides we have proposed an algorithm to redefine the elementary angles for reducing the number of CORDIC iterations. A generalized micro-rotation selection technique based on high speed most-significant-1-detection obviates the complex search algorithms for identifying the micro-rotations. The proposed CORDIC processor provides the flexibility to manipulate the number of iterations depending on the accuracy, area and latency requirements. Compared to the existing recursive architectures the proposed one has 17% lower slice-delay product on Xilinx Spartan XC2S200E device.

Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency

One of the most important steps in spectral analysis is filtering, where window functions are generally used to design filters. In this paper, we modify the existing architecture for realizing the window functions using CORDIC processor. Firstly, we modify the conventional CORDIC algorithm to reduce its latency and area. The proposed CORDIC algorithm is completely scale-free for the range of convergence that spans the entire coordinate space. Secondly, we realize the window functions using a single CORDIC processor as against two serially connected CORDIC processors in existing technique, thus optimizing it for area and latency. The linear CORDIC processor is replaced by a shift-add network which drastically reduces the number of pipelining stages required in the existing design. The proposed design on an average requires approximately 64% less pipeline stages and saves up to 44.2% area. Currently, the processor is designed to implement Blackman windowing architecture, which with slight modifications can be extended to other widow functions as well. The details of the proposed architecture are discussed in the paper.