Copper Dual Damascene Structure Research Articles

Silica Nano-particle Anneal Treatment and Its Effect on Chemical Mechanical Polishing

Introduction Chemical mechanical polishing is the only one technology to obtain global planarization, which is widely applied to polish silicon, copper dual damascene structure, high/low K dielectric materials, tungsten plugs, poly-silicon gates and shallow trench isolation structure. SiO2 is widely used as abrasive for its superior properties like stability, suspension property and low viscosity There are lots of studies on silica properties. However, the detailed silica surface, inner characteristic and its effect on polishing performance are still unclear. we must also explore the silica nano-particle tiny structure difference, so we designed an experiment that we anneal the colloid silica and re-dispersed it to analyze the variety of particles properties and its influences on CMP performance.

Non-Contact, Sub-Surface Detection of Alloy Segregation in Back-End of Line Copper Dual-Damascene Structures

Alloy seedlayers for copper back-end of line interconnects have become common at technology groundrules of 45 nm and below, due to reliability requirements. The key requirement of the minority alloy component (e.g., Al or manganese, also referred to as the “dopant”) is that it segregates to the copper (Cu)/dielectric cap layer interface in order to promote adhesion between the Cu in the line and the dielectric capping layer. The segregation beneath the dielectric cap has a complex dependence on many process parameters and needs to be monitored across the wafer. In this paper, we present a contactless, in-line, fast, and reliable Kelvin probe technique for the sub-surface detection of alloy segregation in Cu interconnects for sub-22 nm technologies.

Electromigration failure in a copper dual-damascene structure with a through silicon via

Electromigration induced failure development in a copper dual-damascene structure with a through silicon via (TSV) located at the cathode end of the line is studied. The resistance change caused by void growth under the TSV and the interconnect lifetime estimation are modeled based on analytical expressions and also investigated with the help of numerical simulations of fully three-dimensional structures. It is shown that, in addition to the high resistance increase caused by a large void, a small void under the TSV can also lead to a significant resistance increase, particularly in the presence of imperfections at the TSV bottom introduced during the fabrication process. As a consequence, electromigration failure in such structures is likely to have bimodal characteristics. The simulation results have indicated that both modes are important to be considered in order to obtain a more precise description of the interconnect lifetime distribution.

Cu Dendrite Formation in Post Trench Etch Cleaning

Copper has been widely used as the interconnect material for integrated circuits because of the good electrical conductivity and electron migration resistance. Copper dual damascene structure has been adapted due to the impossibility of etching the copper. For via first dual damascene (VFDD) integration, via is opened after trench etch. Generally, diluted HF cleaning after trench etch is used to remove both etch residues and carbon depletion layer of low-k material. In this study, we investigated the characteristics of copper dendritic formation occurred in post trench etch cleaning with single wafer spin tool (SWST).

Electromigration characteristics in dual-damascene copper interconnects by difference of via structures

In order to improve the interconnect performance, copper has been used as the interconnect material instead of aluminum. One of the advantages of using copper interconnects instead of aluminum is better electromigration (EM) performance and lower resistance for ultralarge-scale integrated (ULSI) circuits. Dual-damascene processes use different approaches at the via bottom for lowering the via resistance. In this study, the effect of a Ta/TaN diffusion barrier on the reliability and on the electrical performance of copper dual-damascene interconnects was investigated. A higher EM performance in copper dual-damascene structures was obtained in barrier contact via (BCV) interconnect structures with a Ta/TaN barrier layer, while a lower EM performance was observed in direct contact via (DCV) interconnect structures with a bottomless process, although DCV structures had lower via resistance compared to BCV structures. The EM failures in BCV interconnect structures were formed at the via, while those in DCV interconnect structures were formed in the copper line. The existence of a barrier layer at the via bottom was related to the difference of EM failure modes. It was confirmed that the difference in EM characteristics was explained to be due to the fact that the barrier layer at the via bottom enhanced the back stress in the copper line.

Review of trench and via plasma etch issues for copper dual damascene in undoped and fluorine-doped silicate glass oxide

Dual damascene dielectric etch technology is emerging as a key enabler for advanced integration schemes. Early implementations of copper dual damascene processes favored the trench-first approach. This approach has now been largely superseded by the via-first scheme for technology nodes below 250 nm. Several etch issues typically arise when implementing either of these approaches. The via-first approach can lead to either via veils or excessive faceting problems when the trench is etched. The traditional trench-first approach requires long via overetches and very high selectivity to the underlayer so that allowance can be made for vias that are misaligned or placed outside the trenches. Trench-first lithography employing organic resists often requires patterning over nonplanar surfaces, which can result in narrow process windows. Both the via-first and trench-first approaches increasingly require etching the trench without a stop layer. This places exacting demands on etch uniformity, etch front control, and sidewall profile angle control. Control of these issues is enhanced when the etch mechanisms responsible for driving them are understood. These and other issues as well as the current understanding of the relevant mechanisms are discussed for implementing copper dual damascene structures in plasma enhanced chemical vapor deposition undoped silicate glass or fluorinated silicate glass oxide films.

Diffusion Barrier Deposition on a Copper Surface by Atomic Layer Deposition

Diffusion barrier materials, TiN and WN, were deposited by atomic layer deposition (ALD). The chlorine concentration of the TiN film was as low as 1.2 at.-%, and resistivity was below 200 μΩ cm. Ultra high aspect ratio (AR=85) trenches were used to assess step coverage. Tungsten nitride film, deposited from WF 6 and ammonia, was found to have high resistivity, although the residue content was low. The barrier deposition compatibility was studied using the copper surface exposed on the bottom of vias in the copper dual-damascene structure. The deposition on copper of both TiN and WN was found to be very challenging.