I. INTRODUCTION and BACKGROUND 3D integration technologies have emerged less than 10 years ago as viable solutions for meeting IC requirements such as higher performance, increased functionality, lower power consumption, and a smaller footprint. Some examples of 3D integration in products are CMOS Image Sensors (CIS), memories and interposers. Through-Silicon-Vias (TSVs) are integrated in most of these products, because they allow die-level assembly, and simplify some aspects of test and packaging. However, TSVs disadvantage is the silicon device keep out zones combined with a Cu pillar pitch typically limited to ~40 µm. For some applications, such as CMOS image sensors and memories, smaller pitches (< 10 µm) are required for the vertical die-to-die connections; direct hybrid bonding (HB) is the solution of interest. While the first HB products are put on the market [1] few detailed studies are published from the robustness/reliability point of view. This paper reviews the robustness/reliability achievements and include previously published data related to the HB module (Wafer-to-Wafer [W2W] or Die-to-Wafer [D2W]). II. RESULTS Compared to standard microelectronics processes, the main difference of 3D integration consists in the addition of a wafer-bonding step. Due to the bonding tool alignment accuracy, from 200 nm to 1 µm respectively for W2W and D2W, misalignment could lead to an electrical yield loss. W2W-based studies demonstrated 100 %-yield [2, 3] where D2W ones still show lower yield (>90 %) [4] mainly due to more recent developments.Silicon dioxide can be hydrophilic, this tends to highlight a potential risk of moisture sensitivity of the HB module. By means of uHAST, Beillard and Gambino did not evidence any issue [3, 5].Because different materials are assembled, thermomechanical stress issue could arise. ST/CEA-LETI works demonstrated [2, 6] no particular impact at 7.2 and 1.44 µm-interconnect pitches after thermal cycling tests. For larger pitches, Gambino and Gao reached a similar conclusion [3, 7].Electromigration (EM)-induced degradation is another potential reliability issue. As demonstrated by ST/CEA-LETI [8], for a pitch of 7.2 µm, HB integration is immune to EM whatever the electron flow. The failure always occurs in the BEoL layers. For a smaller pitch (3.24 µm), IMEC highlights a potential risk to the HB module itself [9].Cu diffusion in silicon and silicon dioxide is a well-known issue in microelectronics and is solved by using diffusion barriers (TaN/Ta, Ti/TiN...). Despite the lack of a diffusion barrier at the bonding interface in their integration, ST/CEA-LETI [10, 11] demonstrated by electrical and chemical characterization (TVS/BTS, ToF-SIMS/TEM-EELS) that no copper diffusion is nevertheless detectable. Gambino and Kagawa, with different integrations, reached the same conclusion [3, 12].To conclude, in the light of the published works, even if HB module could raise specific robustness/reliability issues, all the lights are green for mass production with micrometric pitches, which is consistent with the fact that this approach, at these pitches, is found in some products [1]. On the contrary, for sub-micrometric pitches some questions remain topical (IMD reliability, Cu diffusion, electromigration). Acknowledgment This work was supported by the French National Research Agency (ANR) under the ”Investissements d’avenir” programs: ANR 10-AIRT-0005 (IRT NANO-ELEC).