CORDIC Research Articles

Coordinate Rotation-Based Design Methodology for Square Root and Division Computation

In this brief, we propose a low-complexity design methodology to compute square-root and division using circular coordinate rotation digital computer (CORDIC). Unlike the state of the art methods, the proposed methodology eliminates the requirement of a separate hardware for square root and division computation in the CORDIC-based applications without compromising the computational speed, throughput and accuracy. The ASIC implementation of the proposed architecture has been performed using UMC 90 nm Technology node with 1.08 V @1 MHz and subsequently Xilinx Virtex-6 (XC6v1x240t)-based FPGA-prototyping has been done. The performance of the proposed methodology has been compared with the reported literature and significant power consumption improvement was observed without any additional area overhead.

δ-error elimination using truncation retention method and implementation on FPGA for non-redundant CORDIC

In this paper, δ-error is concerned and eliminated in digital implementation of CORDIC algorithm. An analysis on the accumulation mechanism of the computing error which leads to δ-errors is first conducted. And a truncated bits retention method is proposed to compensate the accumulated computing errors and eliminate δ-errors. Results of numerical simulations show that δ-error elimination and calculation accuracy improvement are achieved with the increase of SY even for extremely small inputs. Hardware implementation and resource consumption are also discussed.

Improving the signal-to-noise ratio in a fiber-optic Fabry–Pérot acoustic sensor

A fiber-optic Fabry–Pérot acoustic sensor with a ~50 nm-thick multilayer graphene diaphragm is reported. In this paper, the results of the simulation and experimental investigation of the Fabry–Pérot acoustic sensor are primarily presented, and the main area of interest is studying the different algorithms for enhancement of the sensor sensitivity. The phase generated carrier (PGC) demodulation algorithm is presented, based on differential-cross-multiplying (DCM), the arctangent (ATAN) function and ATAN based on a coordinate rotation digital computer CORDIC algorithm. The simulation results reveal that the PGC demodulation method, based on the ATAN CORDIC algorithm, has a better result (signal-to-noise ratio) than the DCM and ATAN function without using the CORDIC algorithm. On this account, a PGC demodulation algorithm based on the ATAN method with a CORDIC algorithm is applied in the experimental investigation due to the simulation results and simpler digital implementation on a field programmable gate array. The acoustic sensor shows a high frequency response from 8–10 kHz and may be useful for highly sensitive acoustic sensing without temperature and pressure fluctuation. The results also show acoustic sensitivity in the order of −98 dB re rad µPa−1 at 1 kHz.

Realization of Direct Digital Synthesis in Cordic Algorithm

Realization of Direct Digital Synthesis in Cordic Algorithm

Economic Modelling and Implementation of Test Signal Generator for Characterization of Continuous Time Sigma-Delta Analog-to-Digital Converter

Now there is a tremendous growth in the specific applications positively related to wireless communications, which posses the specific requirement for mixed-signal integrated circuits. When these independent circuits are used in the unique design of ADC and DAC practical applications, the considerable complexity of the testing increases. BIST is a precisely conventional technique which typically reduces this considerable complexity and prevents functional dependence on high-cost test equipment ATE. Moreover, in Built-In-self-Test (BIST), the output response analyzer (ORA) is the most significant component of architecture of continuous time (CT) sigma-delta analog-to-digital converter (ADC). There are numerous techniques of ORA used for accurate determining the design parameters like integral non-linearity (INL), differential non-linearity (DNL), signal-to-noise ratio (SNR). In this paper, the prime focus is primarily on the modern CORDIC technique which is used as ORA. For the modelling and accurate simulation of this technique Matlab simulink and CADENCE VIRTUOSO EDA tool environment software are properly implemented. A Coordinate Rotation Digital Computer (CORDIC) reduces the design complexity of the independent circuit. The design of ADC can be improved tremendously by typically using BIST. This paper focuses on the system level modelling of test stimuli generator (TSG) and its simulation for accurate characterization of high-resolution sigma-delta ADC. The successful implementation is carefully tested on Matlab simulink tool environment. The auto-testing external test equipment is required to test the integrated structures. TSG is implemented and it helps in extracting of statics and transmission parameters required for characterization of CT sigma-delta ADC.

A Resource-Efficient Multiplierless Systolic Array Architecture for Convolutions in Deep Networks

This brief presents a resource-efficient VLSI architecture for convolution operations in deep networks. Taking advantage of a feature of the max pooling layer in classical convolutional neural networks (CNNs), the image pixels are scaled such that the weight values are constrained to lie in [-1, +1] range. Under this constraint, the weight parameters are chosen as trigonometric functions, enabling realization of convolution without multipliers. In particular, the convolution is realized using the CORDIC algorithm. We also propose a dataflow model based on a reconfigurable systolic ring array to achieve performance comparable to contemporary CNN architectures but with substantially less hardware, high resource utilization efficiency, and reduced power consumption. FPGA implementation of the proposed architecture on Xilinx Virtex-5 XC5VLX5OT achieves roughly 55% higher resource efficiency, with approximately 53% reduction in the slice-delay product and 55% reduction in power consumption compared to recent architectures.

Design of Cascaded CORDIC Based on Precise Analysis of Critical Path

A conventional coordinate rotation digital computer (CORDIC) has a low throughput rate due to its recursive implementation of micro-rotations. On the contrary, a fully-pipelined cascaded CORDIC provides a very high throughput rate at the cost of high complexity and large area. In this paper, possible design choices of cascaded CORDIC are explored over a wide range of operating frequencies, throughput rates, latency, and area complexity. For this purpose, we present a fine-grained critical path analysis of the cascaded CORDIC in terms of bit-level delay. Based on the propagation delay estimate, we propose an algorithm for determining the required number of pipeline stages and locations of the pipeline registers in order to meet the time constraint in a particular application. A hybrid cascaded-recursive CORDIC is also proposed to increase the throughput rate, and to reduce the latency and energy per sample (EPS). From synthesis results, we show that the proposed pipelined cascaded CORDIC with only four pipeline stages requires 31.1% less area and 29.0% less EPS compared to a fully-pipelined CORDIC. An eight stage pipelined recursive cascaded CORDIC provides 18.3% less EPS and 40.4% less area-delay product than a conventional CORDIC.

Iterative Inter-Cell Interference Cancellation Receiver for LDPC-Coded MIMO Systems

In an ultra-dense cellular system, users at the cell-edge are susceptible to inter-cell interference (ICI) because of the overlap of the spectrum. To combat ICI, this paper investigates two iterative ICI cancellation approaches for low-density parity-check-coded multiple-input multiple-output systems. One approach includes separate signal and interference detectors; the other one employs a joint detector for both the desired signal and interference. The joint-detector approach achieves a comparable error-rate performance with only half the computational complexity when compared to the separate-detector counterpart. An iterative ICI cancellation receiver using the joint detector is proposed and implemented. Its hardware efficiency is significantly enhanced by leveraging an efficient coordinate rotation digital computer based processing array, an adaptive input-range scaling scheme, and an area-efficient log-likelihood ratio calculator. The iterative ICI cancellation receiver is flexible enough to support multiple modulations of up to 256-QAM. The maximum gross throughput is 1.24 Gb/s for a 4×4 256-QAM configuration in a 40-nm CMOS technology. The proposed iterative receiver outperforms the current state-of-the-art works in both the throughput-to-area ratio and the normalized energy metrics, despite the added ICI capability.

A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G

A high-throughput programmable fast Fourier transform (FFT) processor is designed supporting 16- to 4096-point FFTs and 12- to 2400-point discrete Fourier transforms (DFTs) for 4G, wireless local area network, and future 5G. A 16-path data parallel memory-based architecture is selected as a tradeoff between throughput and cost. To implement a hardware-efficient high-speed processor, several improvements are provided. To maximally reuse the hardware resource, a reconfigurable butterfly unit is proposed to support computing including eight radix-2 in parallel, four radix-3/4 in parallel, two radix-5/8 in parallel, and a radix-16 in one clock cycle. Twiddle factor multipliers using different schemes are optimized and compared, wherein modified coordinate rotation digital computer scheme is finally implemented to minimize the hardware cost while supporting both FFTs and DFTs. An optimized conflict-free data access scheme is also proposed to support multiple butterflies at any radices. The processor is designed as a general IP and can be implemented using a processor synthesizer (application-specific instruction-set processor designer). The electronic design automation synthesis result based on a 65-nm technology shows that the processor area is 1.46 mm2. The processor supports 972 MS/s 4096-point FFT at 250 MHz with a power consumption of 68.64 mW and a signal-to-quantization-noise ratio of 66.1 dB. The proposed processor has better-normalized throughput per area unit than the state-of-the-art available designs.

Improved VLSI architecture for triangular windowed sliding DFT based on CORDIC algorithm

This study presents a very-large-scale integration (VLSI) architecture for the triangular windowed sliding discrete Fourier transform (SDFT) based on COordinate rotation DIgital computer (CORDIC) algorithm. In the literature, the triangular windowed SDFT is obtained by direct cascading of two SDFT modules, whereas the idea of direct cascading leads to the error in the odd bins of the spectrum. The proposed architecture is modified to provide the correct outputs with a high-throughput rate compared to the existing designs. The SDFT has a recursive structure, and therefore it accumulates the error over iterations as the computation proceeds. A refreshing mechanism is utilised to limit the inaccuracy at the final output. The concept of generalised architecture as an area efficient implementation for obtaining more number of discrete Fourier transform (DFT) bins is introduced. An architecture is implemented using Verilog HDL on FPGA as well as in ASIC platform, and its arithmetic verification is performed in MATLAB.

Simulation and experimental investigation about interferometric optical fiber acoustic sensor for sensitivity enhancement

In this paper, the results of simulation and experimental investigation of interferometric optical fiber acoustic sensing are primarily presented, and the main area of interest is studying the different algorithms for enhancement of sensor sensitivity. In fact, when light propagates through optical fiber, in a Michelson interferometer, the phase of light changes due to effect of external perturbation as acoustic wave on optical path length and this phase change is detected by demodulation algorithm. It is strived to present the Phase Generated Carrier (PGC) demodulation algorithm based on Differential-Cross-Multiplying (DCM), Arctangentfunction (ATAN) and ATAN based on Coordinate Rotation Digital Computer CORDIC algorithm. Simulation results reveal that PGC demodulation method based on ATAN CORDIC algorithm has better result (signal to noise ratio) than DCM and ATAN without using CORDIC algorithm. On this account, PGC demodulation algorithm based on ATAN method with CORDIC algorithm is applied in the experimental investigation due to simulation results and simpler digital implementation on Field Programmable Gate Array (FPGA). Moreover, acoustic frequency is detected as sidebands of harmonics of phase modulator frequencies. The sensitivity of digital circuit is 5μradHz-0.5 and the minimum detectable phase is 50μrad Acoustic frequency is detected as sidebands of harmonics of phase modulator frequencies, and consequently, the system allows detecting the sinusoidal acoustic wave with different frequencies. It is also detected acoustic frequency by measurement of the reflected optical power. Moreover, in this part, it is packaged sensing arm of interferometer with polymer material (polyurethane) for investigation the effect of polymer on sensitivity enhancement of sensor. It is observed with applying of acoustic wave, the reflected optical power decreases and this reduction is more, when sensing arm is packaged with polymer.

A Low-Power and High-PSNR Unified DCT/IDCT Architecture Based on EARC and Enhanced Scale Factor Approximation

The Discrete cosine transform (DCT) and inverse Discrete cosine transform (IDCT) have been widely used in image and video compression standards, and more and more researchers focus on the method that taking use of the coordinate rotation digital computer (CORDIC) to execute the DCT and IDCT, the reason is that CORDIC can realize the complex transcendental functions only by using shifters and adders, and is easily suitable implemented in a parallel way. However, the conventional CORDIC has some drawbacks, such as low precision, long iteration number, scale factor and so on. In our previous paper, we have implemented an unified DCT/IDCT based on adaptive recoding CORDIC (ARC) to improve the performance. In this paper, compared with our previous work, we propose an enhanced unified architecture for DCT and IDCT based on the cooperation between the enhanced adaptive recoding coordinate rotation digital computer (EARC) and the conventional CORDIC, in which the radix-2 scale factor approximation proposed in our previous paper is also optimized significantly to achieve better performance in power consumption and PSNR. To conduct a fair competition, the proposed architecture is also validated on a Virtex 5 FPGA platform to evaluate the performance. Under DCT only mode, compared with the Huang and Lee architectures, the proposed architecture at least uses 3.3% less area, dissipates 9% less power at the nearly 2% cost of the critical path delay. Under DCT/IDCT mode, the proposed architecture also saves over 2% hardware resources, reduces more than 5.9% power dissipation when compared to the latest unified DCT/IDCT architectures. Meanwhile, the proposed architecture exceeds the state-of-the-art unified architectures over 0.98 dB in PSNR. Compared with 2S-8P-DCT and 3S-8P-DCT, the proposed unified DCT/IDCT architecture also achieves the best performance in accuracy, processing time and throughput.

Characteristic Analysis and Calculation of Frequencies of Voltages in Out-of-Step Oscillation Power System and a Frequency-Based Out-of-Step Protection

During the out-of-step oscillation process, the frequency of voltage at every point in power system changes continuously. In this paper, the voltage frequency variation regulation is analyzed in an equivalent two-terminal system whose two-terminal potential amplitudes are not equal and all electrical component impedance angles are different. It finds the bus voltage frequencies at different sides of out-of-step center own different characteristics. In order to use the frequency variation characteristics to construct the criterion of power system out-of-step protection, a fast frequency calculation algorithm is proposed, in which the frequency is calculated by toggling different formulas at different sampling points and the calculation accuracy is improved by the aid of coordinate rotation digital computer (CORDIC) algorithm. The algorithm is easy to implement and measurement errors can keep under a low level. Finally, a novel frequency based out-of-step protection with wide area information is described. It can judge the occurrence of out-of-step oscillation in the first out-of-step oscillation cycle and determine the electrical component where the out-of-step center locates, which lays the foundation for the determination of out-of-step splitting section for complex power systems. The test results with IEEE39 system in PSCAD verify the correctness of the proposed protection.

An enhanced digital predistortion algorithm based on polynomial model identification

To improve the accuracy of the nonlinear distortion correction for the radio frequency (RF) power amplifier (PA), it is necessary to precisely obtain the reverse function of the PA nonlinear model. However, the direct inversion of the PA nonlinear model involves solving a high-order univariate polynomial, which is difficult to apply in engineering. In this study, based on the envelope memory polynomial (EMP) model, the high-order terms of the nonlinear model are approximated by their previously calculated values through iterations and considered as known constants in the polynomial solution finding process, thereby resulting in a significant reduction in computational complexity. Compared with the direct inversion method, model of a 9th-order nonlinear, the proposed method reduces the calculation time in the coordinated rotation digital computer (CORDIC) algorithm by at least 80%. The simulation results show that for a long-term evolution (LTE) downlink signal, the results obtained by the proposed simplified method agree well with those obtained by direct inversion method.

Fingerprint Identification Using FPGA with a Newly Designed Architecture

The Aadhaar project was recently introduced by the Unique Identification Authority of India (UIDAI) to provide a Unique Identification (UID) number to every resident of India. Biometric and demographic information are used to create a unique identification number (Aadhaar). You may use your Aadhaar number to get a subsidy on LPG cylinders, a driving licence, a PAN card and a bank account. The software industry is crucial to the success of the Aadhaar system. The suggested work, including the pre-processing stage, fingerprint recognition process, and fingerprint recognition system, is carried out across three platforms, including MATLAB, field programmable gate array (FPGA), and application specific integrated circuit (ASIC). In order to improve the processing speed, resource utilisation, power consumption, and recognition rate of the proposed job, the FPGA is programmed with two specialised hardware methods: the CORDIC algorithm and IP cores. The suggested work largely focuses on fixing the processing time and accuracy issues. The concept is converted into an ASIC using FPGA technology with the goal of reducing power consumption and resource utilisation without sacrificing performance. In contrast to FPGA implementation, which makes use of look-up tables (LUTs) and customizable logic blocks (CLBs), ASIC implementation makes use of the basic cells directly. When compared to FPGA design, ASIC development speeds up recognition by 20%.

СИНТЕЗ СВЕРТОЧНЫХ ФУНКЦИЙ В РЕАЛЬНОМ ВРЕМЕНИ В СИСТЕМАХ ПРОГРАММНО-ЗАВИСИМОГО РАДИО И ФАЗО-ЧАСТОТНЫХ ИЗМЕРИТЕЛЬНЫХ УСТРОЙСТВАХ

This article presents a state-of-the-art method of mathematical analysis and implementation of a hardware-accelerated generator of kernel functions based on Morlet wavelet. The method is based on heavy usage of hardware cores of high-performance programmable logic devices (PLD) for generating harmonic and Gaussian modulating functions in real-time mode. The usage of modulated harmonic series allows tuning parameters of kernel functions both in frequency and time domains, while fine tuning of damping factor of Gaussian function is performed on the base of fixed-point representation of wavelet samples. The proposed hardware generator has a feature allowing to create high-order kernel functions, which is impossible with the approach based on storing coefficients in on-chip memory limited in size. An analysis performed in the article allows calculating a set of integration limits and corresponding damping coefficients for Gaussian modulating function. Implementation on the PLD was performed with combination of existing IP-cores based on CORDIC algorithm and original developed components. Modelling and implementation are performed with Kintex-7 series PLD. Using this approach several high-precision systems were designed. These systems are precision measurement devices for frequency and phase measurements. They also may be used for software-defined radio devices, including pure digital implementation of an input radio-frequency signal. Some examples are also reviewed.

CORDIC-Based Architecture for Computing Nth Root and Its Implementation

This paper presents a COordinate Rotation Digital Computer (CORDIC)-based architecture for the computation of Nth root and proves its feasibility by hardware implementation. The proposed architecture performs the task of Nth root simply by shift-add operations and enables easy tradeoff between the speed (or precision) and the area. Technically, we divide the Nth root computation into three different subtasks, and map them onto three different classes of the CORDIC accordingly. To overcome the drawback of narrow convergence range of the CORDIC algorithm, we adopt several innovative methods to yield a much improved convergence range. Subsequently, in terms of convergence range and precision, a flexible architecture is developed. The architecture is validated using MATLAB with extensive vector matching. Finally, using a pipelined structure with fixed-point input data, we implement the example circuits of the proposed architecture with radicand ranging from zero to one million, and achieve an average mean of approximately 10−7 for the relative error. The design is modeled using Verilog HDL and synthesized under the TSMC 40-nm CMOS technology. The report shows a maximum frequency of 2.083 GHz with $197421.00~{\mu }\text{m}^{2}$ area. The area decreases to $169689.98~{\mu }\text{m}^{2}$ when the frequency lowers to 1.00 GHz.

Efficient Low-Latency Implementation of CORDIC-Based Sorted QR Decomposition for Multi-Gbps MIMO Systems

This brief presents the efficient VLSI implementation of coordinate rotation digital computer (CORDIC)-based sorted QR decomposition (SQRD) for multiple-input and multiple-output (MIMO) systems. SQRD is widely adopted in MIMO signal processing to mitigate error propagation. However, its iterative sorting process after every column annihilation requires a large hardware overhead and suffers from a latency issue. The proposed CORDIC-based SQRD modifies a real-value decomposition matrix to utilize symmetry and jointly performs sorting processes and CORDIC rotations with adjacent symmetric columns to reduce the required number of CORDIC rotations and CORDIC stages. Furthermore, the VLSI design of the proposed SQRD has been synthesized and implemented with a Virtex-6 FPGA and a 65-nm CMOS technology, respectively. The 65-nm implementation results show an overall processing latency of 266.5 ns, a throughput of 48.8 MSQRD per second, and can support a 4.7-Gbps MIMO system throughput.

Development of a high-speed full digital processing phase detector for interferometry.

This study describes the development of a fully digital-type phase detector for plasma interferometry. This detector functions even in situations in which the phase changes rapidly or the input signal is too small to derive the correct phase shift from the intermediate frequency (IF) signal. The detector directly converts the IF signal waveform of the interferometer to the phase shift signal by means of data processing in a logic circuit. Thus, the phase is derived from the whole waveform of the IF signal. The IF signal of the interferometer is converted to in-phase and quadrature-phase signals by Hilbert transformation, processed by a digital low-pass filter, and converted to polar coordinates by a coordinate rotation digital computer algorithm to obtain the phase shift. A simulation of the high-speed full digital processing phase detector shows that a fringe jump does not occur unless the phase change rate exceeds 0.8 × 106 rad/s. This value is sufficiently large compared to the phase change velocity in rapid density increase resulting from a pellet injection. The phase conversion is simulated using a real IF signal from an interferometer measured with a Heliotron J device. The results show that the phase signal is correctly calculated by the full digital processing method from the IF signal, the phase derivation of which is typically difficult to obtain when using a conventional analog phase detector.

Algorithm for realisation, parameter analysis, and measurement of pipelined separable 3D finite impulse response filters composed of Givens rotation structures

A novel algorithm for the realisation of an orthogonal digital system performing three-dimensional filtering for a separable transfer function is presented in this study. The algorithm is based on a state-space approach and consists of synthesis and implementation algorithms. A structure composed of Givens rotators and delay elements is obtained. A coordinate rotation digital computer algorithm has been used to implement Givens rotators in a pipelined structure. The obtained structure has been realised on a field-programmable gate array (FPGA) chip and its performance has been evaluated. It achieved good finite precision, good sensitivity of filter amplitude to filter coefficients, less noise, better impulse response, and less FPGA chip occupation. To verify the obtained results, they have been compared to the results obtained using a direct-form structure consisting of adders, multipliers, and delay elements.