Abstract
A conventional coordinate rotation digital computer (CORDIC) has a low throughput rate due to its recursive implementation of micro-rotations. On the contrary, a fully-pipelined cascaded CORDIC provides a very high throughput rate at the cost of high complexity and large area. In this paper, possible design choices of cascaded CORDIC are explored over a wide range of operating frequencies, throughput rates, latency, and area complexity. For this purpose, we present a fine-grained critical path analysis of the cascaded CORDIC in terms of bit-level delay. Based on the propagation delay estimate, we propose an algorithm for determining the required number of pipeline stages and locations of the pipeline registers in order to meet the time constraint in a particular application. A hybrid cascaded-recursive CORDIC is also proposed to increase the throughput rate, and to reduce the latency and energy per sample (EPS). From synthesis results, we show that the proposed pipelined cascaded CORDIC with only four pipeline stages requires 31.1% less area and 29.0% less EPS compared to a fully-pipelined CORDIC. An eight stage pipelined recursive cascaded CORDIC provides 18.3% less EPS and 40.4% less area-delay product than a conventional CORDIC.
Highlights
The key concept of coordinate rotation digital computer (CORDIC) arithmetic is that it can effectively compute trigonometric functions, vector rotation, multiplication, and division through an iterative formulation of shift and add operations
As CORDIC acts as a basic arithmetic operator in addition to adders, subtractors, and multipliers in hardware implementation, their performance greatly affects the performance of the entire system, especially in CORDIC applications requiring high performance, such as fast Fourier transform (FFT) [13] or embedded FPGA-based synthesizers, including chaotic Pseudo-random number generators [14]
The proposed K-stage pipelined-recursive-cascaded CORDIC (PRCC) is compared with a conventional CORDIC [1] computed through recursive computation of one stage and opposing non-recursive cascaded CORDIC computed through N stages
Summary
The key concept of coordinate rotation digital computer (CORDIC) arithmetic is that it can effectively compute trigonometric functions, vector rotation, multiplication, and division through an iterative formulation of shift and add operations. The speed of CORDIC operations is limited either by the required precision (number of iterations) or the clock period. Given each pipeline stage performs one predetermined micro-rotation, the number of shifts required for shift-add or shift-sub operations in each pipeline stage is known a priori. The critical path of pipelined CORDIC amounts to the time required to execute add or subtract operations in each stage. Fully-pipelined-cascaded CORDIC (FPCC) has potential for a very low clock period and very high throughput. Such high throughput rate is usually not required in real applications.
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