Coordinate Rotation Digital Computer Processor Research Articles

Fault Classification and Diagnosis Approach Using FFT-CNN for FPGA-Based CORDIC Processor

Within the realm of digital signal processing and communication systems, FPGA-based CORDIC (Coordinate Rotation Digital Computer) processors play pivotal roles, applied in trigonometric calculations and vector operations. However, soft errors have become one of the major threats in high-reliability FPGA-based applications, potentially degrading performance and causing system failures. This paper proposes a fault classification and diagnosis method for FPGA-based CORDIC processors, leveraging Fast Fourier Transform (FFT) and Convolutional Neural Networks (CNNs). The approach involves constructing fault classification datasets, optimizing features extraction through FFT to shorten the time of diagnosis and improve the diagnostic accuracy, and employing CNNs for training and testing of faults diagnosis. Different CNN architectures are tested to explore and construct the optimal fault classifier. Experimental results encompassing simulation and implementation demonstrate the improved accuracy and efficiency in fault classification and diagnosis. The proposed method provides fault prediction with an accuracy of more than 98.6% and holds the potential to enhance the reliability and performance of FPGA-based CORDIC circuit systems, surpassing traditional fault diagnosis methods such as Sum of Square (SoS).

Research and Hardware Implementation of a Reduced-Latency Quadruple-Precision Floating-Point Arctangent Algorithm

In the field of digital signal processing, such as in navigation and radar, a significant number of high-precision arctangent function calculations are required. Lookup tables, polynomial approximation, and single/double-precision floating-point Coordinate Rotation Digital Computer (CORDIC) algorithms are insufficient to meet the demands of practical applications, where both high precision and low latency are essential. In this paper, based on the concept of trading area for speed, a four-step parallel branch iteration CORDIC algorithm is proposed. Using this improved algorithm, a 128-bit quad-precision floating-point arctangent function is designed, and the hardware circuit implementation of the arctangent algorithm is realized. The results demonstrate that the improved algorithm can achieve 128-bit floating-point arctangent calculations in just 32 cycles, with a maximum error not exceeding 2×10−34 rad. It possesses exceptionally high computational accuracy and efficiency. Furthermore, the hardware area of the arithmetic unit is approximately 0.6317 mm2, and the power consumption is about 40.6483 mW under the TSMC 65 nm process at a working frequency of 500 MHz. This design can be well suited for dedicated CORDIC processor chip applications. The research presented in this paper holds significant value for high-precision and rapid arctangent function calculations in radar, navigation, meteorology, and other fields.

Area and power-efficient reconfigurable digital down converter on FPGA

This paper presents a field-programmable gate array (FPGA)-based digital down converter (DDC) that can reduce the bandwidth from about 70 MHz to 182.292 kHz. The proposed DDC consists of a polyphase COordinate Rotation DIgital Computer (CORDIC) processor and a multirate filter. The advantage of polyphase CORDIC processor is to process with high sample rate input data and produces computational efficient noiseless baseband spectrum. The pipeline multirate filter works at a high clock speed. Moreover, the multirate filter generates a fractional sample rate factor using a cubic B-spline Farrow filter. The proposed DDC is coded with optimal hardware description language (HDL) and tested on Kintex-7 Xilinx FPGA as the target device. Experimental results indicate that the proposed design saves chip area, power consumption and operates at high speed without loss of any functionality. Additionally, the proposed design offers sufficient spurious-free dynamic range (SFDR) and produces less than 1 Hz frequency resolution at the output.

A unified reconfigurable CORDIC processor for floating-point arithmetic

ABSTRACT This paper presents a unified reconfigurable coordinate rotation digital computer (CORDIC) processor for floating-point arithmetic. It can be configured to operate in multi-mode to achieve a variety of operations and replaces multiple single-mode CORDIC processors. A reconfigurable pipeline-parallel mixed architecture is proposed to adapt different operations, which maximises the sharing of common hardware circuit and achieves the area-delay efficiency. Compared with previous unified floating-point CORDIC processors, the consumption of hardware resources is greatly reduced. As a proof of concept, we apply it to 16384 × 16384 points target synthetic aperture radar (SAR) imaging system, which is implemented on Xilinx XC7VX690T field programmable gate array platform. The maximum relative error of each phase function between hardware and software computation and the corresponding SAR imaging result can meet the accuracy index requirements.

CORDIC-Based Azimuth Calculation and Obstacle Tracing via Optimal Sensor Placement on a Mobile Robot

Autonomous robots are currently engaged in emergency informatics and participate in operations such as search and rescue. Real-time data collection is a key requirement while there are constraints on the space, height and weight of the hardware on-board with such robots. In this paper, we investigate the amount and sophistication of sensing and processing hardware needed by a mobile robot for performing high-level tasks in real time. In particular, we consider two tasks, namely azimuth calculation and dynamic obstacle tracing and show that one ultrasonic sensor along with a coordinate rotation digital computer processor are adequate for azimuth calculation while one more ultrasonic sensor is required for dynamic obstacle tracing. For dynamic obstacle tracing, we also study a related problem of optimal placement of a pair of ultrasonic sensors. Experiments with a field programmable gate array-based robot equipped with ultrasonic sensors are presented to support the theory.

Design and Implementation of a Generic CORDIC Processor and its Application as a Waveform Generator

Background: With the advent in hand held mobile computing devices, the demand for high performance compact processors is increasing. In this work a processor is designed with hardwired instructions for elementary mathematical functions like sine, cosine, sinh, cosh, division and multiplication. Methods: The processor employs Coordinate Rotation Digital Computer (CORDIC) algorithm for efficient hardware implementation of the above mentioned instructions. The parallel and pipelined implementation of the processor is carried out. The pipelined processor is configured as waveform generator. The novelty of this work is the integration of both trigonometric and hyperbolic operations in the same processor. Findings: ASIC Implementation is carried out with 40nm technology libraries. The parallel processor so designed operates at maximum frequency of 24.23 MHz and pipelined processor operates at maximum frequency of 261.36 MHz. Conclusion: This increase in operating frequency is achieved at the cost of increased silicon area and optimal power dissipation. The waveform generator generates sine, cosine waves of 3.5 MHz and sine hyperbolic, cosine hyperbolic waves and exponential waves of 7.9 MHz. The limitation being the waveform generator generates waves of constant frequency. Additional circuit is required in generating waves of different frequencies.

CORDIC‐based window implementation to minimise area and pipeline depth

Filtering is one of the most important modules in signal processing paradigm. This study presents a field-programmable gate array implementation of various window functions using coordinate rotation digital computer (CORDIC) algorithm to minimise area-delay product. First, the authors modify the Taylor series approximation order used in the scaling-free CORDIC, to completely eliminate the scale-factor and, yet, preserve the range of convergence spanning across the entire coordinate space. Secondly, the authors propose a new generalised technique for micro-rotation sequence identification to reduce the number of iterations required by the pipelined CORDIC processor. Then, this circular CORDIC processor is used to realise window functions. The existing window architecture uses a linear CORDIC processor in series with circular CORDIC processor, resulting in long pipeline. The authors replace the linear CORDIC with multiple optimised shift-add networks to reduce area and pipeline depth. As a result, the proposed window architecture, on an average requires approximately 64.34% less pipeline stages and saves up to 48% area. The authors have designed the processor to implement Hanning, Hamming and Blackman window families. The implementation of the proposed architecture is detailed in this study.

Implementation of Efficiency CORDIC Algorithmfor Sine & Cosine Generation

This paper presents an area-time efficient coordinate rotation digital computer (CORDIC) algorithm that completely eliminates the scale-factor. A generalized micro-rotation selection technique based on high speed most-significant-1-detection obviates the complex search algorithms for identifying the micro-rotations. This algorithm is redefined as the elementary angles for reducing the number of CORDIC iterations. Compared to the existing re-cursive architectures the proposed one has 17% lower slice-delay product on Xilinx Spartan XC2S200E device. The CORDIC processor pro-vides the flexibility to manipulate the number of iterations depending on the accuracy, area and latency requirements. Index Terms—coordinate rotation digital computer (CORDIC), cosine/sine, field-programmable gate array(FPGA),most-significant-1, recursive architecture.

Reconfigurable Design of Pipelined CORDIC Processor for Digital Sine-Cosine

Digital sine and cosine waves have been used in countless applications in the field of vector rotated Digital Signal Processing (DSP). The COordinate Rotation DIgital Computer (CORDIC) algorithm has become very popular due to its simplicity in catering to almost perfect digital sine and cosine waveforms during modulation and demodulation processes in DSP modules. In this paper, we have presented the design of pipelined architecture for the computation of flexible and scalable digital Sine and Cosine values using the CORDIC algorithm. The design of an application-specific CORDIC processor in circular rotation mode gives high system throughput due to pipelined architecture by reducing latency in each individual pipelined stage. Saving area on FPGA is essential to the design of pipelined CORDIC and can be achieved through optimizing the number of micro rotations. The computed quantization error is also minimized using a required number of iterations. The design has been synthesized and implemented on a Xilinx Spartan 3 device using 10.1 ISE design tool suite and results are shown and discussed.

Computation Error Analysis in Digital Signal Processing Systems With Overscaled Supply Voltage

It has been recently demonstrated that digital signal processing systems may possibly leverage unconventional voltage overscaling (VOS) to reduce energy consumption while maintaining satisfactory signal processing performance. Due to the computation-intensive nature of most signal processing algorithms, the energy saving potential largely depends on the behavior of computer arithmetic units in response to overscaled supply voltage. This paper shows that different hardware implementations of the same computer arithmetic function may respond to VOS very differently and result in different energy saving potentials. Therefore, the selection of appropriate computer arithmetic architecture is an important issue in voltage-overscaled signal processing system design. This paper presents an analytical method to estimate the statistics of computer arithmetic computation errors due to supply voltage overscaling. Compared with computation-intensive circuit simulations, this analytical approach can be several orders of magnitude faster and can achieve a reasonable accuracy. This approach can be used to choose the appropriate computer arithmetic architecture in voltage-overscaled signal processing systems. Finally, we carry out case studies on a coordinate rotation digital computer processor and a finite-impulse-response filter to further demonstrate the importance of choosing proper computer arithmetic implementations.

Highly accurate reduced iteration CORDIC processor algorithm

In this study, we propose a COordinate Rotation Digital Computer (CORDIC) algorithm that gives highly accurate results in fewer iteration counts than previously published methods. The utilisation of a look-up table in the conventional CORDIC algorithm and the usage of the scaling factor is eliminated. The CORDIC algorithm is initiated from the first micro rotation. The accuracy of the micro rotation angle values and the vector coordinate components are improved. The number of iterations is reduced below the level of methods which use look-up tables in their algorithms while maintaining accuracy. In addition, the computation error is greatly reduced with respect to the other algorithms.

FPGA implementation of area time efficient CORDIC processor dedicated to compute exponentials in neural networks

This paper presents high-performance exponential computation based on the Coordinate Rotation Digital Computer (CORDIC) algorithm with emphasis on minimum hardware requirements. The redesigned unified CORDIC algorithm provides high throughput and is beneficial for the VLSI implementation of the activation functions in neural networks and realisation of exponent calculations in Gaussian Potential Functions (GPFs). Ease of design and scale-free operation of the proposed technique extend the range of convergence compared with the original CORDIC algorithm. Approximately, 57.1% hardware savings are accomplished in comparison with Flat CORDIC architectures for 32-bit word-length. The word-length of the processor is extendible and the experimental results confirm its efficacy.

Fixed-Point Error Analysis of CORDIC Arithmetic for Special-Purpose Signal Processors

CORDIC (COordinate Rotation DIgital Computer) is a well known algorithm using simple adders and shifters to evaluate various elementary functions. Thus, CORDIC is suitable for the design of high performance chips using VLSI technology. In this paper, a complete analysis of the computation error of both the (conventional) CORDIC algorithm and the CORDIC algorithm with expanded convergence range is derived to facilitate the design task. The resulting formulas regarding the relative and absolute approximation errors and the truncation error are summarized in the tabular form. As the numerical accuracy of CORDIC processors is determined by the word length of operands and the number of iterations, three reference tables are constructed for the optimal choice of these numbers. These tables can be used to facilitate the design of cost-effective CORDIC processors in terms of areas and performances. In addition, two design examples: singular value decomposition (SVD) and lattice filter for digital signal processing systems are given to demonstrate the goal and benefit of the derived numerical analysis of CORDIC.

Design and simulation of reusable IP CORDIC core for special-purpose processors

Coordinate rotation digital computer (CORDIC) is a well-known algorithm using simple adders and shifters to evaluate various elementary functions. A double rotation CORDIC algorithm with an efficient strategy to predict the rotation direction is proposed for a high-speed sine and cosine generator and complex multiplier. Simulation results show that the computation time can be improved by 37.2%, 42.67% and 46.04% for 16-bit, 32-bit and 64-bit operands, respectively. In addition, the overall power consumption per CORDIC arithmetic computation can be improved by 21.2% and 38.5% for 32-bit and 64-bit operands, respectively. Thus, the proposed double rotation CORDIC processor is suitable for high-speed applications.

Design of an efficient CORDIC-based architecture for synchronization in OFDM

This paper presents a new architecture to estimate the time and frequency offsets required to synchronize packed-based orthogonal frequency division multiplexing (OFDM) modulation receivers. The proposed estimators, which operate in the frequency-domain, use CORDIC (coordinate rotation digital computer) processors to achieve an efficient hardware implementation which is simpler than other computational intensive estimators based on processing in the time-domain. The hardware saving is twofold: the proposed implementation does not require complex cells such as multipliers or dividers; and some cells already existing in OFDM receivers for pay-load demodulation are reused during the synchronization phase. In addition, this paper also shows how to optimize the CORDIC cells, in terms of number of iterations, to provide a given signal-to-noise ratio (SNR) due to approximation error, and proposes an error propagation model for the proposed synchronization architecture

Optimization of CORDIC cells in the backward circular rotation mode

The COordinate Rotation DIgital Computer (CORDIC) algorithm in the backward circular rotation mode efficiently computes phase estimation. In this letter, a set of new rules are proposed to design a CORDIC processor to achieve a given signal-to-noise ratio ( SNR). To this end, two new approximate expressions to estimate the SNR are derived accounting for the approximation and quantization errors, respectively.

Novel architecture for QAM modulator–demodulator and its generalization to multicarrier modulation

This paper presents an architecture for quadrature amplitude modulation (QAM) modulator and demodulator with hardware economic structure. While the modulator part requires simple logic circuits for its implementation, the more complex demodulator utilizes Running Fourier transform based on CORDIC (Co-Ordinate Rotation DIgital Computer) processor, for demodulation as well as synchronization. The basic design philosophy has been extended to multicarrier modulation and demodulation technique by using pipelined CORDIC structure for computing Running Fourier transform. The architectures have been implemented with 16 bit wordlength in Xilinx Spartan series field programmable gate arrays (FPGA).

Fixed-Point Error Analysis of CORDIC Processor Based on the Variance Propagation Formula

This paper presents a fixed-point mean-square error (MSE) analysis of coordinate rotation digital computer (CORDIC) processors based on the variance propagation method, whereas the conventional approaches provide only the error bound which results in large discrepancy between the analysis and actual implementation. The MSE analysis is aimed at obtaining a more accurate analysis of digital signal processing systems with CORDIC processor, especially when the design specification is given by the signal-to-noise ratio or MSE. For the MSE analysis, the error source and models are first defined and the output error is derived in terms of MSE in the rotation mode of the conventional CORDIC processor. It is shown that the proposed analysis can also be applied to the modified CORDIC algorithms. As an example of practical application, a fast Fourier transform processor using the CORDIC processor is presented in this paper, and its output error variance is analyzed with respect to the wordlength of CORDIC. The results show a close match between the analysis and simulation.

Efficient architecture and design of an embedded video coding engine

By doubling the accuracy of motion compensation from integer-pel to half-pel, we can significantly improve the coding gain. Therefore, in this paper, we propose a novel COordinate Rotation Digital Computer (CORDIC) architecture for combined design of discrete cosine transform (DCT) and half-pel motion estimation. Unlike the conventional block matching approaches based on interpolated images, our CORDIC design can directly extract motion vectors at half-pel accuracy in the transform domain without interpolation. Compared to the conventional block matching methods with interpolation, our multiplier-free design achieves significant hardware saving and far less data flow. Our emphasis in this paper is on achieving efficient design of video coding engine by minimizing computational units along the data path. Furthermore, we implement the embedded design on a dedicated single chip to demonstrate its performance. The DCT-based nature of our design enables us to efficiently combine both DCT and motion estimation units, which are the two most important components of many multimedia standards consuming more than 80% of computing power for a video coder, into one single component. As a result, we can provide a single chip solution for video coding engine while many conventional designs may require multiple chips. In addition, all multiply-and-add (MAC) operations in plane rotations are replaced by CORDIC processors with simple shift-and-add, which is quite simple and compact to realize while being no slower than the bit serial multipliers widely proposed for VLSI array structures. Based on the test result, our chip can operate at 20 MHz with 0.8-/spl mu/m CMOS technology. Overall, we provide a low-complexity, high throughput solution in this paper for MPEG-1, MPEG-2, and H.263 compatible video codec design.

A CORDIC processor for FFT computation and its implementation using gallium arsenide technology

In this paper, the architecture and the implementation of a complex fast Fourier transform (CFFT) processor using 0.6 /spl mu/m gallium arsenide (GaAs) technology are presented. This processor computes a 1024-point FFT of 16 bit complex data in less than 8 /spl mu/s, working at a frequency beyond 700 MHz, with a power consumption of 12.5 W. The architecture of the processor is based on the COordinate Rotation DIgital Computer (CORDIC) algorithm, which avoids the use of conventional multiplication-and-accumulation (MAC) units, but evaluates the trigonometric functions using only add and shift operations, Improvements to the basic CORDIC architecture are introduced in order to reduce the area and power of the processor. This together with the use of pipelining and carry save adders produces a very regular and fast processor, The CORDIC units were fabricated and tested in order to anticipate the final performance of the processor. This work also demonstrates the maturity of GaAs technology for implementing ultrahigh-performance signal processors.