Abstract
Digital sine and cosine waves have been used in countless applications in the field of vector rotated Digital Signal Processing (DSP). The COordinate Rotation DIgital Computer (CORDIC) algorithm has become very popular due to its simplicity in catering to almost perfect digital sine and cosine waveforms during modulation and demodulation processes in DSP modules. In this paper, we have presented the design of pipelined architecture for the computation of flexible and scalable digital Sine and Cosine values using the CORDIC algorithm. The design of an application-specific CORDIC processor in circular rotation mode gives high system throughput due to pipelined architecture by reducing latency in each individual pipelined stage. Saving area on FPGA is essential to the design of pipelined CORDIC and can be achieved through optimizing the number of micro rotations. The computed quantization error is also minimized using a required number of iterations. The design has been synthesized and implemented on a Xilinx Spartan 3 device using 10.1 ISE design tool suite and results are shown and discussed.
Published Version
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