Coordinate Rotation Digital Computer Algorithm Research Articles

Creative and accurate method for optimal hardware implementation of neurons and biological cells: Application in FPGA-based implementation of cardiac pacemaker cell

The sinoatrial (SA) node cells play a vital role as the principal pacemaker in mammalian hearts, generating regular and spontaneous action potentials to regulate the heart’s rhythm. Comprehending the intricate activity of the SA node’s operation necessitates a collection of differential formulas that tackle non-linear functions. The study presents a new technique to improve the digital representation of the SA node cell model, offering benefits such as decreased hardware needs, enhanced processing speed and accuracy, and reduced implementation expenses by transforming the original model’s differential equations into a unified trigonometric function. This transformation significantly simplifies the computational complexity by eliminating the need for multipliers, resulting in a streamlined set of mathematical expressions. The digital implementation of this novel method can be efficiently realized using the Coordinate Rotation Digital Computer (CORDIC) algorithm, which circumvents the necessity for cumbersome mathematical operations. To demonstrate the viability of this approach, the proposed model is successfully synthesized and implemented on a Field-Programmable Gate Array (FPGA). The results of the implementation demonstrate a significant rise in the operating frequency, which is approximately 6.14 times greater than that of the original model. Furthermore, there is a notable 45 percent decrease in power usage. The lowered hardware needs make significant scalability possible, thus allowing for the inclusion of approximately 12 times as many SA node cells on a sole FPGA board in comparison to the original design.

Miniaturized photoelectrochemical sensing system for reusable detection of macromolecules and its applications for unattended environmental monitoring

Photoelectrochemical (PEC) sensors are widely employed in biochemical detection due to their accuracy and speed, but most PEC measurement systems face challenges with bulky instruments and complex operations. Current miniaturized systems based on Potentiostat and constant light are limited in accuracy and application ranges. PEC systems based on mod/demod signal processing offer high SNR and accuracy but struggles with miniaturization due to complex algorithms of Lock-in amplifier. Herein, discrete Fourier transform (DFT) algorithm instead of Lock-in algorithm was used for the photocurrent demodulation in PEC system. After functional verification, coordinate rotation digital computer (CORDIC) algorithm was used to implement DFT demodulation to further reduce resource occupancy. Afterwards, the spectral leakage was reduced by applying Hanning window, which improves the SNR and accuracy of photocurrent demodulation. Subsequently, a miniaturized, low-cost, low-power and high-accuracy PEC measurement system was obtained by integrating designed Hanning-CORDIC-DFT module, Potentiostat, light source driver and other miniaturized modules. The performances of miniaturized PEC measurement system were compared with that of the commercial PEC measurement system based on Lock-in amplifier by using the same MIP-PEC sensor, validating the feasibility and accuracy of designed miniaturized PEC system. Then, the performance of MIP-PEC sensor was investigated in detail. The results showed that MIP-PEC sensor has good sensitivity, stability, selectivity and recyclability for detecting MC-LR. The reliability of MIP-PEC sensor was further confirmed by the recovery test of MC-LR in lake water. Finally, long-term, cyclic and unattended measurements of microcystin-LR were achieved by designed miniaturized PEC system and MIP-PEC sensor under different conditions, verifying the practicality of the system for field monitoring. The designed measurement system provides a new method for constructing miniaturized PEC sensing platform, and a new solution for continuous biochemical detection in complex environments.

Design and FPGA Implementation of Signal Strength Measurement Techniques for Satellite Communication Systems

Communication receivers perform three major functions, frequency down conversion, IF demodulation and subcarrier demodulation. The functioning of a receiver is mainly controlled by input signal strength and relative dynamics. Signal strength is measured in terms of Signal to Noise ratio (SNR) and Carrier to Noise power density (C/No). Any measure of signal strength indirectly gives information about receiver performance for that period. Apart from this, SNR measurement in close loop with Phase Locked Loop (PLL) parameter forms the adaptive PLL system, which is one of the driving forces for this paper. The focus of this paper is to find suitable signal strength measurement techniques and their implementation for satellite communication systems. Signal to Noise Variance method (SNV) and Narrow band Wide band Power Ratio (NWPR) methods are considered based on the performance and realization aspects. All techniques require division, logarithm, and multiplication functions for their realization in hardware. CO-ordinate Rotation Digital Computer (CORDIC) algorithm is considered for realizing logarithm function. A comparison study is done for developed algorithm with Intellectual Property (IP) core. Developed SNR techniques are simulated for Binary Phase Shift Keying (BPSK) demodulator system and performance is evaluated for Additive White Gaussian Noise (AWGN). The paper describes the FPGA design and simulations of these techniques. Developed design is targeted to commercial and space qualified FPGA platforms. FPGA implementations results are compared with system level simulation results, and both are found to be satisfactory. Application of developed system in adaptive BPSK demodulator is also presented.

Low complex CNN for semiconductor wafer defect detection

Fabrication of semiconductor wafers is a complex process and chances of defect wafers are high. Because of defective wafers the circuit patterns will not be created correctly and it is necessary to identify them. Manual identification of defects are time consuming and expensive. Deep learning methods are widely used for defect detection. In this paper we propose a simple Convolutional Neural Network (CNN) model for classification of nine defects in wafers. A custom CNN consisting of 9 layers is used for the classification of defects as Center, Donut, Edge-Loc, Edge-Ring, Loc, Random, Scratch, Near-full, and None. Performance of the model is evaluated using WM-811K dataset. Results shows that the model classifies the defects with high confidence score and an accuracy of 99.1% is achieved using this method. Further, the convolution operation in the CNN is realized using Coordinate Rotation Digital Computer (CORDIC) algorithm. The model is implemented in Field Programmable Gate Arrays (FPGA) and proved less complex method and consume less computational power than conventional methods.

Digital design of a spatial-pow-STDP learning block with high accuracy utilizing pow CORDIC for large-scale image classifier spatiotemporal SNN

The paramount concern of highly accurate energy-efficient computing in machines with significant cognitive capabilities aims to enhance the accuracy and efficiency of bio-inspired Spiking Neural Networks (SNNs). This paper addresses this main objective by introducing a novel spatial power spike-timing-dependent plasticity (Spatial-Pow-STDP) learning rule as a digital block with high accuracy in a bio-inspired SNN model. Motivated by the demand for precise and accelerated computation that reduces high-cost resources in neural network applications, this paper presents a methodology based on COordinate Rotation DIgital Computer (CORDIC) definitions. The proposed designs of CORDIC algorithms for exponential (Exp CORDIC), natural logarithm (Ln CORDIC), and arbitrary power function (Pow CORDIC) are meticulously detailed and evaluated to ensure optimal acceleration and accuracy, which respectively show average errors near 10–9, 10–6, and 10–5 with 4, 4, and 6 iterations. The engineered architectures for the Exp, Ln, and Pow CORDIC implementations are illustrated and assessed, showcasing the efficiency achieved through high frequency, leading to the introduction of a Spatial-Pow-STDP learning block design based on Pow CORDIC that facilitates efficient and accurate hardware computation with 6.93 × 10–3 average error with 9 iterations. The proposed learning mechanism integrates this structure into a large-scale spatiotemporal SNN consisting of three layers with reduced hyper-parameters, enabling unsupervised training in an event-based paradigm using excitatory and inhibitory synapses. As a result, the application of the developed methodology and equations in the computational SNN model for image classification reveals superior accuracy and convergence speed compared to existing spiking networks by achieving up to 97.5%, 97.6%, 93.4%, and 93% accuracy, respectively, when trained on the MNIST, EMNIST digits, EMNIST letters, and CIFAR10 datasets with 6, 2, 2, and 6 training epochs.

Review on FPGA Implementation of CORDIC Algorithm

The Coordinate Rotation Digital Computer (CORDIC) algorithm has emerged as a pivotal method for executing trigonometric and various mathematical operations within digital systems. Field-Programmable Gate Arrays (FPGAs) have witnessed a remarkable surge in adoption for implementing the CORDIC algorithm owing to their inherent flexibility and exceptional performance capabilities. This paper endeavours to provide a comprehensive overview of FPGA implementations of the CORDIC algorithm, elucidating both the advantages and challenges associated with this methodology. It thoroughly examines various FPGA architectures customized for CORDIC implementation, meticulously analyzing their respective trade-offs regarding resource utilization, performance metrics, and accuracy levels. Moreover, the paper explores numerous applications where the FPGA-based CORDIC algorithm shines, illustrating its adaptability across diverse domains like digital signal processing and control systems. These applications underscore the algorithm's efficacy in addressing real-world challenges and its potential to significantly augment system performance and efficiency.By furnishing profound insights into FPGA-based CORDIC implementations, this paper serves as an invaluable resource for engineers and researchers keen on harnessing the capabilities of FPGAs for high-performance mathematical computations in digital systems.

The Parallel Solving Method of Robot Kinematic Equations Based on FPGA

In the implementation of robot motion control, complex kinematic computations consume too much central processing unit (CPU) time and affect the responsiveness of robot motion. To solve this problem, this paper proposes a parallel method for solving kinematic equations of articulated robots based on the coordinate rotation digital computer (CORDIC) algorithm. The method completes the fast calculation of the transcendental function based on the CORDIC algorithm, adopts the tree structure method to optimize the key computational paths of forward and inverse solutions, and designs a parallel pipeline to realize the low latency and high throughput of the kinematic equations. The experiments of the proposed method are validated based on the field-programmable gate array (FPGA) hardware experimental platform, and the experimental results demonstrate that the computational time to complete the entire kinematic equations is 4.68 μs, of which the computational time for the kinematic positive solution is 0.52 μs and the computational time for the kinematic inverse solution is 4.16 μs.

A Unified Parallel CORDIC-Based Hardware Architecture for LSTM Network Acceleration

Deep Neural Networks (DNNs) have recently become the standard tool for solving various practical problems in a wide range of applications with state-of-the-art performance. Recurrent Neural Networks (RNNs) such as Long Short-Term Memory (LSTM) are a subset of DNNs with fully connected single or multi-layer networks. The complex neurons and internal states of LSTM networks enable them to build a memory of events, making them ideal for time series applications. Despite the great potential of LSTM networks, their heterogeneous operations and computational resource requirements create a vast gap when it comes to the fast processing time required in real-time applications using low-power, low-cost edge devices. This work proposes a novel hardware architecture that combines serial-parallel computation with matrix algebra concepts and efficient low-power computer arithmetics for LSTM network acceleration. The hardware is based on a systolic ring of outer-product-based processing elements (PEs) and a reusable single activation function block (AFB). PEs and AFB are implemented using the coordinate rotation digital computer algorithm (CORDIC) in the linear and hyperbolic modes. Unlike most approaches, the proposed hardware can be configured to perform recurrent and non-recurrent fully connected layers (FC) computations, making it suitable for various low-power edge applications. The architecture is validated on the Xilinx PYNQ-Z1 development board using an open-source time series dataset. The implemented design achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$114 \mu s$</tex-math></inline-formula> average latency and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$1.8GOPS$</tex-math></inline-formula> throughput. The proposed design's low latency and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$0.438W$</tex-math></inline-formula> power consumption makes it suitable for resource-constrained edge platforms.

Research and Hardware Implementation of a Reduced-Latency Quadruple-Precision Floating-Point Arctangent Algorithm

In the field of digital signal processing, such as in navigation and radar, a significant number of high-precision arctangent function calculations are required. Lookup tables, polynomial approximation, and single/double-precision floating-point Coordinate Rotation Digital Computer (CORDIC) algorithms are insufficient to meet the demands of practical applications, where both high precision and low latency are essential. In this paper, based on the concept of trading area for speed, a four-step parallel branch iteration CORDIC algorithm is proposed. Using this improved algorithm, a 128-bit quad-precision floating-point arctangent function is designed, and the hardware circuit implementation of the arctangent algorithm is realized. The results demonstrate that the improved algorithm can achieve 128-bit floating-point arctangent calculations in just 32 cycles, with a maximum error not exceeding 2×10−34 rad. It possesses exceptionally high computational accuracy and efficiency. Furthermore, the hardware area of the arithmetic unit is approximately 0.6317 mm2, and the power consumption is about 40.6483 mW under the TSMC 65 nm process at a working frequency of 500 MHz. This design can be well suited for dedicated CORDIC processor chip applications. The research presented in this paper holds significant value for high-precision and rapid arctangent function calculations in radar, navigation, meteorology, and other fields.

CORDIC KSVD based Online Dictionary Learning for Speech Enhancement on ASIC/FPGA Platforms

Background: The enhancement of real-world speech signals is still a challenging task to eliminate noises, namely reverberation, background, street, and babble noises. Recently learned methods like dictionary learning have become increasingly popular and showed promising results in speech enhancement. The K-means Singular Value Decomposition (KSVD) algorithm is best suited for dictionary learning among many sparse representation algorithms. Moreover, the orthogonal matching pursuit (OMP) based algorithm used for signal recovery is given. The orthogonal matching pursuit (OMP) based algorithm for signal recovery gives the best enhancement results. On the other hand, FPGAs and ASICs are widely used to accelerate speech enhancement applications. FPGAs are commonly used in healthcare and consumer applications, where speech enhancement plays a crucial role. Methods: This paper proposes a modified KSVD algorithm that can easily be implemented onto hardware platforms like FPGAs and ASICS. Instead of using the double-precision arithmetic for the singular value decomposition part of the KSVD algorithm, we proposed to use CORDIC (Coordinate Rotation Digital Computer) based QR decomposition and QR-based singular value decomposition in dictionary learning. Results: The proposed KSVD algorithm is optimal with the CORDIC algorithm that can reduce by 7-8 times the processing time. Conclusion: The finding indicates that the proposed work is best suited to FPGA or ASIC platforms.

Error Analysis of Sine-Cosine Computation using CORDIC Algorithm

Background: Coordinate Rotation Digital Computer (CORDIC) can be used for computing trigonometric functions like sine and cosine for which it iterates over a for loop and performs rotation of the input angle. Methods: On the basis of the condition, it decides addition and subtraction operations to compute the sine and cosine values. In general, for each iteration in the CORDIC algorithm, it produces 1 extra bit of accuracy. This paper presents an in-depth survey of the many changes to the CORDIC algorithm proposed over recent years. An efficient method to calculate the sine and cosine of an input angle using the CORDIC algorithm with minimum hardware requirement is presented here. Results: CORDIC algorithm is implemented for 8 bits, 16 bits and 32 bits input and the average percentage error obtained as the results are 1.67%, 0.003785% and 0.003290% respectively. Conclusion: It can be seen that by increasing the number of bits, the accuracy increases. For a complete survey, discussions addressing the CORDIC algorithm are also presented.

The Ultrasound Signal Processing Based on High-Performance CORDIC Algorithm and Radial Artery Imaging Implementation

The radial artery reflects the largest amount of physiological and pathological information about the human body. However, ultrasound signal processing involves a large number of complex functions, and traditional digital signal processing can hardly meet the requirements of real-time processing of ultrasound data. The research aims to improve computational accuracy and reduce the hardware complexity of ultrasound signal processing systems. Firstly, this paper proposes to apply the coordinate rotation digital computer (CORDIC) algorithm to the whole radial artery ultrasound signal processing, combines the signal processing characteristics of each sub-module, and designs the dynamic filtering module based on the radix-4 CORDIC algorithm, the quadrature demodulation module based on the partitioned-hybrid CORDIC algorithm, and the dynamic range transformation module based on the improved scale-free CORDIC algorithm. A digital radial artery ultrasound imaging system was then built to verify the accuracy of the three sub-modules. The simulation results show that the use of the high-performance CORDIC algorithm can improve the accuracy of data processing. This provides a new idea for the real-time processing of ultrasound signals. Finally, radial artery ultrasound data were collected from 20 volunteers using different probe scanning modes at three reference positions. The vessel diameter measurements were averaged to verify the reliability of the CORDIC algorithm for radial artery ultrasound imaging, which has practical application value for computer-aided clinical diagnosis.

A Digital Timing-Mismatch Calibration Technique for Time-Interleaved ADCs Based on a Coordinate Rotational Digital Computer Algorithm

Timing-mismatch errors among channels in time-interleaved analog-to-digital converters (TIADCs) greatly degrade the whole performance of the system. Therefore, techniques for calibrating timing mismatch are indispensable, and a new fully-digital calibration technique is presented in this article. Based on a Hilbert filter, modified moving averagers (MMAs) and inverse cosine functions, the proposed estimation algorithm is fast (within 1200 sample points) and accurate. Meanwhile, the coordinate rotational digital computer (CORDIC) algorithm, which is used to implement inverse cosine functions, is also improved, giving it higher precision. In addition, a compensation method based on second-order Taylor series approximation with less hardware resource consumption is provided. Through analyses and simulations, this calibration technique proved to be suitable for TIADCs with an arbitrary number of channels, in which the signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) were, respectively, improved from 24.06 dB and 24.57 dB to 67.96 dB and 85.69 dB.

Research and Implementation of a Numerical Control Oscillator with Improved Pipelined CORDIC Algorithm

As the recognized core of electronic systems, frequency synthesizers have been applied in many communication fields. NC oscillator (NCO) is the main component of the frequency synthesizer. It helps to generate high-precision and high-frequency signals, so it has been widely used. NCO implementation methods include table lookup method, polynomial expansion method, coordinate rotation digital computer (CORDIC) algorithm, etc. CORDIC algorithm is one of many commonly used methods in trigonometric function calculation and digital signal processing, and is often used as the core of DDS (direct digital synthesis) to generate signals. Compared with table lookup and polynomial expansion, CORDIC algorithm has higher efficiency in signal generation and hardware utilization. In view of the disadvantages of traditional CORDIC algorithm, which takes up large resources and has relatively slow calculation speed, in order to improve the output efficiency, this paper uses an efficient 12-stage pipelined CORDIC architecture and a very small lookup table (LUT) to implement a sine wave generator. The system is coded and simulated in Quartus and ModelSim. The results show that the proposed structure can increase the operating speed of the system from 217.77 MHz to 291.04 MHz, and improve the output efficiency of the system.

Research on a method of high precision frequency measurement based on coordinate rotation digital computer algorithm and Kalman filter.

Frequency measurement is one of the key techniques in high-precision data acquisition technology of broadband signals. Generally, frequency measurement not only needs to deal with a large amount of data processing but also requires a high precision, but these two aspects are sometimes difficult to reconcile. Some algorithms are overly dependent on the accuracy of the to-be-measured data, which might not be the desired option for real projects since it is almost impossible to get ideal error-free data. This article adopts a frequency measurement method based on the coordinate rotation digital computer algorithm, differential algorithm, and Kalman filter. The use of these algorithms for the frequency measurement process would not only simplify the calculation but also reduce the effect of the measurement error. This method can measure all signals that satisfy the sampling theorem and can also measure multi-channel parallel signals. The experimental results of data simulation and actual measurement on the hardware platform show that the accurate frequency measurement algorithm has a strong data processing ability, stable measurement, and steady improvement in the accuracy of measurement results, which can meet the needs of most instruments for accurate frequency measurement. The measurement error could be reduced to the percentile by the Kalman filter and could be reduced to below the thousandth by the combining the algorithms.

A Comparative Study on CORDIC Algorithms and Applications

Jack Edward Volder had introduced the CORDIC (COordinate Rotation DIgital Computer) in 1959. This year, critical development and advancement of the CORDIC algorithm have reached 62 years. The VLSI implementation of the CORDIC requires simple hardware (of the form add–shift), which makes CORDIC the most suitable building block for many real-time applications. The sequential nature of the CORDIC computation and scale factor are crucial aspects to be considered as they limit the overall performance of the algorithm. In this work, we have studied the various CORDIC algorithms and their architectures which improve the performance of the standard radix-2 CORDIC algorithm. This comparative study aims to provide first-order information on CORDIC algorithm implementations, including their potential applications. In addition, the study also reflected the works done by numerous researchers and highlighted the limitations of the existing architectures and algorithms, and executed the assessment using various parameters such as convergence range, number of iterations required to achieve the complete rotation, and hardware resource complexity to implement [Formula: see text]/[Formula: see text] rotator, [Formula: see text] rotator, and scale factor compensation. We have also carried out error analysis of various CORDIC algorithms in terms of root-mean-squared error (RMSE) and peak signal-to-noise ratio (PSNR). The number of iterations, scale factor, and the sequential computing of the micro-rotations can be identified as significant improvement areas of the CORDIC algorithm and modifications are required for real-time applications.

A High-Accuracy Digital Implementation of the Morris–Lecar Neuron With Variable Physiological Parameters

A highly accurate digital implementation of the Morris-Lecar neuron model is presented with the intended application of hardware acceleration for neuroscience simulation. The novel implementation employs the COordinate Rotation DIgital Computer (CORDIC) algorithm to create a fixed-point implementation that is not only very accurate but requires low digital hardware resources. The accuracy exceeds that of the current state-of-the-art, requires fewer hardware resources to implement, and operates at a higher maximum clock frequency. The design is validated on FPGA and a normalized RMSE of 0.2039 is achieved at a maximum clock frequency of 378.07MHz.

CORDIC-Based FPGA Realization of a Spatially Rotating Translational Fractional-Order Multi-Scroll Grid Chaotic System

This paper proposes an algorithm and hardware realization of generalized chaotic systems using fractional calculus and rotation algorithms. Enhanced chaotic properties, flexibility, and controllability are achieved using fractional orders, a multi-scroll grid, a dynamic rotation angle(s) in two- and three-dimensional space, and translational parameters. The rotated system is successfully utilized as a Pseudo-Random Number Generator (PRNG) in an image encryption scheme. It preserves the chaotic dynamics and exhibits continuous chaotic behavior for all values of the rotation angle. The Coordinate Rotation Digital Computer (CORDIC) algorithm is used to implement rotation and the Grünwald–Letnikov (GL) technique is used for solving the fractional-order system. CORDIC enables complete control and dynamic spatial rotation by providing real-time computation of the sine and cosine functions. The proposed hardware architectures are realized on a Field-Programmable Gate Array (FPGA) using the Xilinx ISE 14.7 on Artix 7 XC7A100T kit. The Intellectual-Property (IP)-core-based implementation generates sine and cosine functions with a one-clock-cycle latency and provides a generic framework for rotating any chaotic system given its system of differential equations. The achieved throughputs are 821.92 Mbits/s and 520.768 Mbits/s for two- and three-dimensional rotating chaotic systems, respectively. Because it is amenable to digital realization, the proposed spatially rotating translational fractional-order multi-scroll grid chaotic system can fit various secure communication and motion control applications.

FPGA Implementation of Reconfigurable CORDIC Algorithm and a Memristive Chaotic System With Transcendental Nonlinearities

Coordinate Rotation Digital Computer (CORDIC) is a robust iterative algorithm that computes many transcendental mathematical functions. This paper proposes a reconfigurable CORDIC hardware design and FPGA realization that includes all possible configurations of the CORDIC algorithm. The proposed architecture is introduced in two approaches: multiplier-less and single multiplier approaches, each with its advantages. Compared to recent related works, the proposed implementation overpasses them in the included number of configurations. Additionally, it demonstrates efficient hardware utilization and suitability for potential applications. Furthermore, the proposed design is applied to a memristive chaotic system with different transcendental functions computed using the proposed reconfigurable block. The memristive system design is realized on the Artix-7 FPGA board, yielding throughputs of 0.4483 and 0.3972 Gbit/s for the two approaches of reconfigurable CORDIC.

Pipeline Implementation of the Unified CORDIC Algorithm in FPGA

This work presents a pipeline implementation of the COordinate Rotation DIgital Computer (CORDIC) algorithm in VHDL. This implementation computes both the trigonometric (sine, cosine, and arctangent of two parameters) and hyperbolic (hyperbolic sine, hyperbolic cosine, and hyperbolic arctangent) fixed-point functions. The implementation was synthesized on a Xilinx ® Zynq UltraScale + ZCU102 FPGA evaluation board, reaching an operating frequency of 297.89 MHz. The results show the proper operation of the proposed architecture, achieving relative errors of less than 1.4% for a 16-bit fixed-point representation. The VHDL implementation is easily adjustable to meet the specific requirements of each system and is available as an open-source code under a Creative Commons license.