Conversion Of Basal Plane Dislocations Research Articles

Effects of terraces and steps on the 4H-SiC BPD-TED conversion rate: A reaction pathway analysis

The practical use of 4H-SiC as a semiconductor material alternative to Si has been investigated by several researchers. However, a key challenge impeding its practical implementation is the elimination of killer defects in the epitaxial layer, such as basal plane dislocations (BPDs), which cause bipolar degradations. The conversion of BPDs into threading edge dislocations is crucial to reduce detrimental mobile dislocations. However, their underlying atomistic mechanisms remain unclear. In this study, the effects of the step height and distance from the step on the contraction of BPDs were determined using a reaction pathway analysis. Notably, the step height did not affect the contraction, and the activation energies for the contraction of the partial dislocation pairs with Burgers vectors closed toward the step were 0.4 (C face) and 0.3 eV (Si face) lower than those for expansion. Conversely, for the partial dislocation pairs with Burgers vectors open toward the step, the activation energies for contraction were 0.4 (C face) and 0.2 eV (Si face) higher than those for expansion. Furthermore, the effect of the step diminished when the distance from the step exceeded 3 nm. The results suggest that the steps prevented contraction, and longer terraces reduced this preventive effect. Therefore, a surface morphology with fewer steps and longer terraces would increase the conversion rate. Furthermore, a low-off-angle substrate and surface polishing would increase the conversion rate, whereas step bunching slightly would decrease it. Macrosteps would decrease the conversion rate as the average distance from the surface to BPDs increased.

Charge-transfer interatomic potential to reproduce 30° partial dislocation movements for 4H-SiC in the surface vicinity and its application to BPD-TED conversion

4H-SiC has recently attracted attention as a new power semiconductor material to replace silicon. One of the challenges impeding its practical use is the elimination of killer defects in its epitaxial layer, such as dislocations and stacking faults. The conversion of basal plane dislocations (BPDs) into threading edge dislocations (TEDs) is crucial for reducing harmful mobile dislocations. However, the atomistic mechanism underlying the process remains elusive. To clarify the BPD–TED conversion mechanism, we developed a charge-transfer interatomic potential to reproduce 30° partial dislocation dynamics in the surface vicinity of 4H-SiC. The proposed potential significantly improved the accuracy of estimating the stacking fault energy and dislocation mobility in the regions where the dislocation core and surface overlap. Using the developed potential, we investigated the mechanism underlying the contraction of a pair of 30° partial dislocations in the vicinity of the surface. From the energy landscape, the equilibrium distance between the two partials decreased as the depth from the surface decreased because of the strong image force near the surface. The equilibrium distance decreased to zero when the depth reached 0.25 nm. This result is qualitatively consistent with the dislocation theory and the known effect of image force. From the viewpoint of the activation energies of kink nucleation and migrations, the activation energy for C-core and Si-core partial contractions decreased below a depth of 1 nm from the C-face and S-face surfaces, respectively, and became almost equal to that of C-core and Si-core expansions, respectively, when the depth reached 0.25 nm. Therefore, the partial BPDs can contract easily in the corresponding structures, particularly when the depth from the surface is less than 1 nm.

Study of Defects in 4H-SiC Epitaxy at Various Buffer Layer Growth Conditions

Buffer layer optimization is a critical technique to mitigate defect propagation from substrate to epilayer, reduce stress, and prevent generation of ingrown defects. In the present study, the impact of dopant transition from substrate to the buffer layer on various epilayer defects was investigated. It was found that a ramped transition of the dopant concentration from substrate to buffer layer is beneficial for reduction of basal plane dislocations in the epilayer compared to an abrupt doping transition. This reduction of defects can be attributed to reduced stress at the substrate-to-buffer layer transition. Tests on buffer layer growth rates also revealed that higher growth rates reduce BPDs (basal plane dislocations) in the epilayers. We believe that BPD conversion in epilayers grown at higher growth rates is energetically more favorable than the conversion at slower growth rates resulting in the observed reduced BPDs at higher growth rates.

Nitrogen Decoration of Basal-Plane Dislocations in 4H - SiC

Basal-plane dislocations (BPDs) pose a great challenge to the reliability of bipolar power devices based on the 4H silicon carbide (4H-SiC). It is well established that heavy nitrogen (N) doping promotes the conversion of BPDs to threading edge dislocations (TEDs) and improves the reliability of 4H-SiC-based bipolar power devices. However, the interaction between N and BPDs, and the effect of N on the electronic properties of BPDs are still ambiguous, which significantly hinder the understanding on the electron-transport mechanism of 4H-SiC-based bipolar power devices. Combining molten-alkali etching and the Kelvin probe force microscopy (KPFM) analysis, we demonstrate that BPDs create acceptor-like states in undoped 4H-SiC, while acting as donors in N-doped 4H-SiC. First-principles calculations verify that BPDs create occupied defect states above the valence band maximum (VBM) and unoccupied defect states under the conduction-band minimum (CBM) of undoped 4H-SiC. The electron transfer from the defect states of intrinsic defects and native impurities to the unoccupied defect states of BPDs gives rise to the acceptor-like behavior of BPDs in undoped 4H-SiC. Defect formation energies indicate that N atoms can spontaneously decorate BPDs during the N doping of 4H-SiC. The binding between N and BPD is strong against decomposition. The accumulation of N dopants at the core of BPDs results in the accumulation of donor-like states at the core of BPDs in N-doped 4H-SiC. This work not only enriches the understanding on the electronic behavior of BPDs in N-doped 4H-SiC, but also helps understand the electron transport mechanism of 4H-SiC-based bipolar power devices.

Effect of temperature on conversion of basal plane dislocations to treading edge dislocations during 4H-SiC homoepitaxiy

Abstract 4H-SiC homoepitaxial layer grown on 4° off-axis substrates is performed at various growth temperature by using the traditional chemical vapor deposition. The effect of growth temperature on propagation of basal plane dislocations from substrate to epitaxy was studied using the deep KOH etching and Synchrotron reflection X-ray topography, and the conversion mechanism was also investigated. It is found that the majority basal plane dislocations are converted to threading edge dislocations during epitaxial growth. Meanwhile, the two types of threading edge dislocations in epitaxial layer are observed after KOH etch. By the optimization of growth temperature, high quality epitaxial wafer with extremely low basal plane dislocations density (

(Invited) Recent Progress in 4H-SiC CVD Growth for High-Voltage Power Devices

This paper reports recent progress in 4H-SiC CVD growth, aiming to obtain high-quality epilayers and bulk crystals with a high productivity for high-voltage power devices. The production of 150 mm-diameter 4H-SiC wafers has become the industry standard and the practical use of 4H-SiC unipolar devices such as Schottky barrier diodes and MOSFETS with a blocking voltage from 600 to 3,300 V started in various fields, including power conditioners for photo voltaic systems, air conditioning equipment, power supplies for IT and manufacturing industries, and inverters for electric cars and trains. Although bipolar devices such as PiN diodes and IGBTs may be more suitable for very high-voltage classes over ten kilo volts, the practical application of the bipolar devices is hindered because of the degradation phenomenon (“bipolar degradation”) in which forward on-state voltage of the devices increases after current stress applied due to the expansion of stacking faults in the crystal during current conduction. Based on the current understanding on the bipolar degradation phenomenon, basal plane dislocations (BPDs) are responsible for the nuclei of expanding single Shockley stacking faults (1SSFs) and the expansion of the 1SSFs is activated by minority carrier injection exceeding a certain level. Although epilayers with low-density BPDs (< 0.1 cm-2) were obtained by enhancing the conversion of BPDs in the substrate to threading edge dislocations (TEDs) at the beginning of epitaxial growth, the expansion of 1SSFs from the BPD segments below the conversion points was confirmed in the high current density operation [1]. This can be understood due to the injection of minority carriers into a region below the BPD-TED conversion points located near the epilayer and substrate interface or in the substrate where high-density BPDs (102 cm-2) are existing. Meanwhile, inserting a buffer layer with a short carrier lifetime between the substrate and drift epilayer has been proposed to prevent minority carrier injection into a region where BPDs remain. At this time, a thinner buffer layer is more preferable and a technique to obtain shorter carrier lifetimes compatible with the practical epitaxial growth and device fabrication processes will be promising. High nitrogen (N) doping yielding high-density free electrons has been shown as a promising method to enhance direct and Auger recombination and reduce carrier lifetimes [2, 3]. Short carrier lifetimes of 66-120 ns were obtained at RT-250 ºC for an epilayer doped with N at 5×1018 cm-3. We also attempted intentional vanadium (V) doping during epitaxial growth of a buffer layer to realize much shorter carrier lifetimes. The highly N+V-doped epilayer (N=5×1018, V=7×1014 cm-3) shows very short carrier lifetimes of ~20 ns or less at RT-250 ºC. Inserting a N- or N+V-doped buffer layer between a substrate and n- drift epilayer in the PiN diodes was confirmed to be effective to prevent the formation of 1SSFs from BPDs in the substrate. Besides continuous improvements in the quality of wafers, the strong demand to cut the cost of 4H-SiC devices from the application side may request to promote wafer productivity. Meanwhile, the development of 200 mm-diameter wafers has been demonstrated by sublimation growth in past conferences. Apart from enlarging wafer diameter, massively enhancing the growth rate or ingot length may pose the ultimate challenge in 4H-SiC bulk growth and trials featuring solution and high-temperature CVD growth methods are now underway. For high-temperature CVD growth, we attempted fast bulk crystal growth of 4H-SiC at a seed temperature of 2350-2550ºC using an H2-SiH4-C3H8-N2 gas system in a vertical CVD reactor [4]. By adjusting process parameters to enhance growth rates and improve crystal quality, fast 4H-SiC crystal growth at a growth rate exceeding 3 mm/h was achieved while maintaining the low dislocation density (threading screw dislocations: ~2.5×102 cm-2) of the seed crystal. A part of this work was supported by Council for Science, Technology and Innovation (CSTI), Cross-ministerial Strategic Innovation Promotion Program (SIP), “Next-generation power electronics/Consistent R&D of next-generation SiC power electronics” (funding agency: NEDO). [1] A. Tanaka et al., J. Appl. Phys. 119, 095711 (2016), [2] T. Tawara et al., J. Appl. Phys. 120, 115101 (2016), [3] T. Tawara et al., J. Appl. Phys. 123, 025707 (2018), [4] N. Hoshino et al., J. Cryst. Growth 478, 9 (2017).

(Invited) UVPL Imaging of 4H-SiC Wafers Along the Device Processing Chain

The market for power electronic devices is highly competitive among devices made of silicon (Si), silicon carbide (4H-SiC) and gallium nitride (GaN) – devices with best performance and reliability at lowest cost will win the race. The price of SiC devices depends on material costs and device production yield, the latter one is limited by technological and structural defects. The device performance is a matter of device design and process technology, and the device reliability is often limited by structural defects. Hence, a characterization method for structural defects in substrates, epiwafers and partially processed wafers is a keystone for development of competitive SiC power electronic devices. Photoluminescence imaging with excitation in the ultraviolet range (UVPL imaging) is an established and powerful technique for such process-accompanying measurements of SiC wafers and we will review its current status in our talk. In this paper we will compare different UVPL imaging systems available on the market in terms of UV excitation parameters and their PL detectors and discuss their defect detection capabilities. We will present the visibility of structural defects in substrates and epiwafers with regard to their defect-specific PL wavelength as well as excitation wavelength and intensity. SiC epiwafers can be optically stressed by using high excitation intensity, i.e. the conversion of basal plane dislocations to stacking faults can be provoked in unprocessed material as shown in figure 1. This “optical stress test” can be used for material quality testing prior to device processing as well as for scientific questions such as the velocities of dislocations. Furthermore, we will present UVPL images of partially processed SiC wafers revealing technologically induced structural defects. In case of 6.5 kV PIN diodes, the UVPL measurements allow even for prediction of bipolar device degradation. UVPL imaging provides fast, non-destructive defect characterization on full-wafer area and allows for targeted process optimization in epitaxial growth and device processing as well as for process control measurements. Defects can be tracked from substrate/epiwafer to different stages of device production. Hence, UVPL imaging is of great importance for cost reduction and reliability improvement of SiC power electronic devices. Figure 1

Effect of C/Si Ratio and Nitrogen Doping on 4H-SiC Epitaxial Growth Using Dichlorosilane Precursor

Application of dichlorosilane (DCS) in 4H-SiC epitaxial growth on 4° off-cut substrates has been studied. The effect of C/Si ratio and N2 gas flow rate on epilayer properties is investigated in detail. It is found that the C/Si ratio has a significant influence on the growth rate, epilayer surface roughness (step-bunching), conversion of basal plane dislocations (BPDs), and generation of morphological defects and in-grown stacking faults. A wide range of doping concentration from p- to n+ can be controlled in DCS growth. High quality 4° off-cut SiC epilayers are achieved for C/Si=1.3 – 1.8. Addition of N2 has no obvious influence on growth rate and defect densities. The BPD conversion greater than 99.8% is achieved independent of N doping without any pretreatment.

Glide of threading edge dislocations after basal plane dislocation conversion during 4H–SiC epitaxial growth

Transmission electron microscopy (TEM) and KOH etching were used to analyze the motion of dislocations after the conversion of basal plane dislocations (BPDs) to threading edge dislocations (TEDs) during 4H–SiC epitaxy. The locations of TED etch pits on the epilayer surface were shifted compared to the original locations of BPD etch pits on the substrate surface. The shift of the TED etch pits was mostly along the BPD line directions towards the up-step direction. For converted screw type BPDs, the conversion points were located below the substrate/epilayer interface. The shift distances in the step-flow direction were proportional to the depths of the BPD–TED conversion points below the substrate/epilayer interface. For converted mixed type BPDs, the conversion points were exactly at the interface. Through TEM analysis, it was concluded that the dislocation shift is caused by a combined effect of H2 etching prior to growth and glide of the threading segments during high temperature epitaxy. The TED glide is only possible for converted pure screw type BPDs and could present a viable means for eliminating BPDs from the epilayer during growth by moving the conversion point below the substrate/epilayer interface.

Study of Surface Morphology, Impurity Incorporation and Defect Generation during Homoepitaxial Growth of 4H-SiC Using Dichlorosilane

The growth of 4° off-axis 4H-SiC epilayers by chemical vapor deposition is studied using dichlorosilane as the Si precursor in a chimney reactor. The unintentional and intentional nitrogen doping at various C/Si ratios and N2 flow rates are investigated. The C/Si ratio has a significant influence on the growth rate, surface morphology, conversion of basal plane dislocations (BPDs), and generation of other defects (e.g., in-growth stacking faults and morphological defects). Addition of N2 has no obvious influence on growth rate and BPD conversion. It is preferable to grow high quality n+ epilayers at a C/Si ratio in the range of 1.3–1.8 along with the addition of a suitable amount of N2 in consideration of high growth rate, good surface morphology, and low defect density. In this case, the conversion ratio of BPDs to threading edge dislocations is greater than 99.8% regardless of N2 addition. Therefore >99.8% substrate BPDs can be buried in an n+ buffer layer, which is beneficial to SiC bipolar power devices. No special treatment prior to, during or after the epigrowth is necessary. The epilayers with doping concentration all the way from p− (∼1e15 cm−3) to semi-insulating, then to n+ (∼1e18 cm−3), can be achieved, giving a great range of flexibility in growth using dichlorosilane precursor. Further optimization of in-situ etching and growth conditions to eliminate step bunching has also been suggested.

Spontaneous Conversion of Basal Plane Dislocations in 4° Off-Axis 4H–SiC Epitaxial Layers

The conversion of basal plane dislocations (BPDs) to electrically benign threading edge dislocations in 4° off-axis 4H–SiC epilayers has been investigated using ultraviolet photoluminescence imaging. The conversion spontaneously occurred throughout the epitaxial layer for all substrates studied using similar epitaxial growth conditions. BPD conversion in highly doped epilayers was suppressed compared with lower n-type doped layers, suggesting that nitrogen concentration influences the conversion mechanism. However, it is technologically important for the conversion to occur in a heavily doped buffer layer. The densities of BPDs in low-doped (∼1014 cm–3) films having a thickness of 20 μm were significantly reduced when a ∼20 μm thick highly doped N+ buffer layer was grown between the low-doped layer and the substrate. Without the buffer layer, an average of ∼50 BPDs cm–2 was observed and with the buffer layer, an average of 1.5 BPDs cm–2 was detected; the best result was 0.2 BPD cm–2. A PiN structure consisting of a 25 μm thick N+ buffer layer to convert the majority of BPDs prior to the device structure was used to test the mitigation process, and the diodes demonstrated no forward voltage change after 225 h of continuous biasing at 100 A cm–2.

Studies of Relaxation Processes and Basal Plane Dislocations in CVD Grown Homoepitaxial Layers of 4H-SiC

It is well known that basal plane dislocations (BPDs) that are replicated from Physical Vapor Transport (PVT) grown 4H-SiC substrates into Chemical Vapor Deposition (CVD) grown homoepitaxial layers can have a detrimental effect on device performance by inducing the expansion of Shockley faults in the epilayer which cause forward voltage drop. As a result, significant advances have been made in engineering the processes by which BPDs are replicated into the epilayer. For example, the conversion of BPDs into less harmful threading edge dislocations (TEDs) at the substrate/epi interface can be enhanced by direct etching of the substrate surface intersections of the BPDs or by growth interrupts which induce etching. Conversion rates of BPDs into TEDs during epilayer growth have been studied in this paper. Secondly, the behavior of BPDs which are replicated into the epilayer has been studied using Synchrotron White Beam X-ray Topography (SWBXT), Monochromatic Beam X-ray Topography (SMBXT), KOH etching and other techniques on pre- and after- epilayer growth of the same substrate. It is observed that dislocation loops inside substrate can move towards interface and then produce interfacial dislocations (IDs) and half-loop arrays (HLAs) under certain growth conditions during homoepitaxy growth of 4H-SiC on off-cut substrates. The HLAs and IDs are observed to form from pairs of opposite sign screw oriented basal plane dislocations in the substrate which replicate into the epilayer and glide opposite directions once critical thickness has been exceeded. Thirdly, we report on both interfacial dislocations and HLA’s generated from: (a) surface sources of BPDs; (b) micropipes; (c) 3C inclusions; and (d) substrate/epilayer interface scratches.It is also observed that some dislocations glide past the interface and into the substrate. This will also be discussed.

Innovative Solutions to Materials Challenges for High-Voltage SiC Power Devices

Silicon carbide (SiC) is a material of interest for high-temperature, high-voltage and high-power switching device applications. Key materials challenges inhibiting such devices include elimination of basal plane dislocations (BPDs) and enhancement of minority carrier lifetimes in the drift or blocking regions of the device. Recent progress in addressing both of these issues is presented. BPDs are a major concern for the SiC bipolar devices required for high-voltage applications as they source Shockley-type stacking faults in the presence of an electron-hole plasma and reduce minority carrier lifetimes. Many methods have been investigated to reduce the BPD density including pre-growth treatments, substrate orientation, growth parameters and growth interrupts. It has been shown that the conversion of BPDs to threading edge dislocations (TEDs) continues throughout the epitaxial growth process in 4° off-axis SiC material and that a minimum thickness of ~16 µm is required to convert all BPDs to TEDs. Here we show that optimizing a hydrogen etch of the substrate prior to epitaxial growth significantly enhances conversion efficiency in a thin highly doped n+ buffer layer (BL). IN this work, epitaxial layers were grown on 4° off-axis substrates in an Aixtron/Epigress VP508 horizontal hot-wall reactor using the standard chemistry of silane (2% in H2) and propane. In addition, using various growth approaches, low-doped epitaxial layers of only 20 µm in thickness on a 5 µm highly doped buffer layer have demonstrated minority carrier lifetimes up to 4 µs, as measured by time resolved photoluminescence, without any pre- or post- processing treatment. Interface recombination likely dominates these measurements. We extend this approach by presenting new data investigating the non-uniformity of lifetime found on as-grown material under various conditions.This work is supported by the Office of Naval Research

Site Specific TEM Specimen Preparation for Characterization of Extended Defects in 4H-SiC Epilayers

Silicon carbide (SiC) is an important semiconductor for high temperature, high voltage and high power electronic applications. Unfortunately, SiC still has not reached its potential in these applications due to the presence of extended defects in epilayers, which degrade the performance of SiC-based devices. In this work, focused ion beam (FIB) is employed to prepare site-specific cross-sectional transmission electron microscopy (TEM) specimens allowing direct characterization of unwanted in-grown stacking faults (IGSFs) and basal plane dislocations (BPDs). IGSFs are known to decrease breakdown voltages and increase leakage currents in SiC diodes [1]; however, their nucleation mechanism is currently not established. BPDs can form recombination-induced stacking faults, which lead to device performance degradation over time [2]. Recently, KOH etching of the substrate was reported to cause conversion of BPDs to electrically benign threading edge dislocations (TEDs) in the epilayer. However, for some BPDs this conversion was also associated with a shift in the locations of etch pits [3]. In this study, FIB and TEM are used to explain the nucleation mechanism of IGSFs and the previously observed shift in the locations of BPDs.

Conversion of Basal Plane Dislocations to Threading Edge Dislocations in Growth of Epitaxial Layers on 4H-SiC Substrates with a Vicinal Off-Angle

We have investigated a conversion of basal plane dislocation (BPD) to threading edge dislocation (TED) in growth of epitaxial layers (epi-layers) on 4H-SiC vicinal substrates with an off-angle of 0.85° at low C/Si ratio of 0.7 by using deep KOH etching and X-ray topography observations. Deep KOH etching indicated that BPDs in the substrates converted to TEDs in the epi-layers. X-ray topography observations suggested that the conversion occurred during epitaxial growth when the thickness of epi-layers was less than 1.5 μm. We found that the conversion ratio obtained from counting deep KOH etch pits was over 99%.

Experimental verification of the model by Klapper for 4H-SiC homoepitaxy on vicinal substrates

4H-SiC homoepitaxial layers free of basal plane dislocations (BPDs) are urgently needed to overcome the so-called bipolar degradation of high-voltage devices. BPDs being present in substrates are able to either propagate to the epilayer or convert to harmless threading edge dislocations (TEDs) in the epilayer. The model by Klapper predicts the conversion of BPDs to TEDs to be more efficient for growth on vicinal substrates with low off-cut angle. This paper aims to verify the model by Klapper by an extensive variation of epitaxial growth parameters and the substrates' off-cut. It is shown that the off-cut angle is the key parameter for growth of BPD-free epilayers. Furthermore, it is shown that the model also describes adequately the behavior of different types of TEDs, i.e., TED II and TED III dislocations, during epitaxial growth. Therefore, the model by Klapper is verified successfully for 4H-SiC homoepitaxial growth on vicinal substrates.

Managing Basal Plane Dislocations in SiC: Perspective and Prospects

Conversion of basal plane dislocations (BPDs) to threading edge dislocations in 8 and 4{degree sign} offcut SiC material has been studied in order to eliminate the nucleation source of Shockley-type stacking faults in the active region of bipolar devices. Ex situ and in situ growth interrupts were used to convert BPDs in the 8{degree sign} material, where conversion rates up to 98% were achieved for in situ interrupts in epilayers with doping < 1x1016 cm-3. Complete spontaneous conversion of BPDs was found to be possible in 4{degree sign} offcut material after ~ 20 µm of epitaxial growth for both intentionally and unintentionally doped films.

Basal plane dislocation conversion near the epilayer/substrate interface in epitaxial growth of 4° off-axis 4H–SiC

The conversion of basal plane dislocations (BPDs) is investigated in the epitaxial growth of 4° off-axis SiC by three approaches: (1) regular growth on untreated substrates, (2) growth on pre-etched substrates and (3) growth-etch-regrowth approach. In the regular growth, ∼99.0% of the substrate BPDs are converted to threading edge dislocations (TEDs) in the vicinity of the epilayer/substrate interface and the rest ∼1.0% BPDs are converted throughout the ∼20μm thick epilayer. A modified KOH–NaOH–MgO eutectic mixture is developed to mildly etch the substrate in approach (2) or a grown buffer-layer in approach (3) to enhance BPD conversion rate. In the subsequent epitaxial growth, the BPD conversion rate near the interface is enhanced up to 99.9% in approach (2) and to 100% in approach (3). Using the modified KOH–NaOH–MgO eutectic mixture, very mild etching of the surfaces (substrate or buffer-layer) for a short duration (2–3min) will generate very small etch pits, and will not degrade the morphology of the etched surfaces and also that of the subsequently grown epilayer surfaces, but very high (∼100%) BPD conversion rate is still preserved. Post-polishing process is no longer needed for future device fabrication. It is proposed that the opening of a sector plane in the BPD etch pit, which enables lateral epitaxial growth to pinch off the step-flow growth inside the etch pit, is responsible for the high BPD conversion rate near the interface. The degree of anisotropic etching in the 〈11–20〉 directions versus the 〈1–100〉 directions determines the sector open angle of the BPD etch pits. The degree of anisotropic etching is studied for different KOH formulations—pure KOH, regular KOH–NaOH eutectic and the modified KOH–NaOH–MgO eutectic mixture.

Conversion of Basal Plane Dislocations to Threading Edge Dislocations by Annealing 4H-SiC Epilayers at High Temperatures

Basal plane dislocations (BPDs) converting to threading edge dislocations (TEDs) has been observed in 4H-SiC epilayers after thermal annealing at high temperatures. Grazing incidence reflection synchrotron X-ray topography was used to investigate the dislocation behaviors. It is argued that the conversion is achieved by constricted BPD segments cross-slipping to the prismatic plane and TED glide on its slip plane. Higher conversion ratio and better surface morphology were achieved by performing ion implantation and annealing before epitaxial growth.

Dislocation Conversion in 4H-SiC Crystals Grown by Metastable Solvent Epitaxy

Dislocation conversion in 4H-SiC single crystals grown by metastable solvent epitaxy (MSE) was investigated using synchrotron X-ray topography, repeated polishing and molten KOH etching, and transmission electron microscopy (TEM). The conversion of basal plane dislocations to threading edge dislocations occurred not only near the interface between the MSE layer and the substrate, but also throughout the MSE layer. At the initial stage of MSE growth, all threading screw dislocations (TSDs) were converted into Frank-type basal plane stacking faults (Frank SFs). High resolution TEM observation revealed that the four extra SiC planes generated by this conversion were inserted among adjacent basal planes. These results suggest that the driving force for the conversion of TSDs is significantly larger for MSE growth than for growth by conventional chemical vapor deposition. A g·b analysis of the Frank partial dislocations (PDs) associated with the Frank SFs revealed that the total sum of the Burgers vectors of the four Frank PDs had two different values of b = c and b = c + a, and that approximately 50% of TSDs in the substrate had a Burgers vector component parallel to the a-axis.