Conventional Switching Scheme Research Articles

High energy-efficient partial floating capacitor array DAC scheme for SAR ADCs

A high energy saving and high linearity switching method of successive approximation register analogue-to-digital converters is presented. The proposed method can achieve high energy savings and high linearity due to the fact that the partial floating and split capacitor techniques are combined. This scheme has no reset energy consumption, and achieves purely 98.63% less switching energy and 75% reduction of the total capacitance over the conventional switching scheme. Moreover, the proposed scheme achieves Differential Nonlinearity and Integral Nonlinearity only 0.140LSB and 0.122LSB, respectively.

Reference switching pre‐emphasis‐based successive approximation register ADC with enhanced DAC settling

A reference switching pre-emphasis (RSP) technique is proposed for successive approximation register (SAR) ADC in order to improve the SAR DAC settling time, which limits the conversion speed of conventional SAR ADCs. While SAR ADCs that employ redundancy techniques relax DAC settling requirements by overlapping search spaces, this requires more conversion steps which offsets the benefit from the DAC settling relaxation, especially for low–medium resolution SAR ADCs. The proposed RSP technique improves DAC settling by breaking its dependence on ADC resolution and achieves up to 71% speedup of DAC settling relative to a conventional DAC switching scheme without introducing additional conversion steps or significant hardware overhead.

A 0.975 μW 10-bit 100 kS/s SAR ADC with an energy-efficient and area-efficient switching scheme

A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an energy-efficient and area-efficient switching scheme was presented. By using C-2C dummy capacitor and an extra reference [Formula: see text] for the last capacitor, the proposed switching scheme achieves 97.65% switching energy saving, 87.2% capacitor area reduction and 47.06% switches reduction, compare to conventional switching scheme. The ADC was implemented in a 180 nm CMOS technology 1.8 V power supply, at sampling rate of 100 kS/s, the ADC achieves an SNDR of 57.84 dB and consumes 0.975 [Formula: see text], resulting in a figure-of-merit (FOM) of 15.3 fJ/conversion-step.

99.8% energy saving and 97.4% area reduction switching scheme for SAR ADCs

A high energy and area efficiency switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented. The proposed procedure achieved 99.8% saving in switching energy and 97.4% reduction in total capacitance when applied to a 10-bit SAR ADC, compared to the conventional switching scheme. The switching energy has been calculated by taking into account both the power consumed in the switching processes and the reset energy.

Closed‐loop charge recycling switching scheme for SAR ADC

An energy-efficient switching scheme for successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed. Based on closed-loop charge recycling method, the proposed switching scheme achieves 100% less switching energy over the conventional switching scheme. Furthermore, the common-mode voltage of the comparator is always V cm and only two reference voltages are used.

Low-Power High-Linearity Switching Procedure for Charge-Redistribution SAR ADC

An energy-efficient capacitive switching scheme in successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed for biomedical applications. With novel sequence initialization and by reducing the up-switching steps during the A/D conversion, the average switching energy of this proposed procedure is reduced by over 98.7% compared with the conventional architecture after taking the parasitic capacitance into consideration. The number of capacitors in the proposed capacitor array is just 1/4 of that in the conventional switching scheme. Moreover, behavioral simulation performed in MATLAB for the 10-bit SAR ADC shows that the linearity performance of this proposed switching scheme is much better than that of previous architectures.

A Photoswitchable Fluorophore for the Real-Time Monitoring of Dynamic Events in Living Organisms.

This study reports the synthesis of a photoactivatable fluorophore with optimal photochemical and photophysical properties for the real-time tracking of motion in vivo. The photoactivation mechanism designed into this particular compound permits the conversion of an emissive reactant into an emissive product with resolved fluorescence, under mild illumination conditions that are impossible to replicate with conventional switching schemes based on bleaching. Indeed, the supramolecular delivery of these photoswitchable probes into the cellular blastoderm of Drosophila melanogaster embryos allows the real-time visualization of translocating molecules with no detrimental effects on the developing organisms. Thus, this innovative mechanism for fluorescence photoactivation can evolve into a general chemical tool to monitor dynamic processes in living biological specimens.

A Switched-Capacitor Filter With Reduced Sensitivity to Reference Noise for Audio-Band Sigma–Delta D/A Converters

A switched-capacitor analog reconstruction filter with a new reference switching scheme is presented for reducing sensitivity to reference noise in audio-band sigma–delta ( $\Sigma\Delta$ ) digital-to-analog converters. By sampling a single reference voltage with its polarity depending on the filter digital input, the ac component of the reference voltage is attenuated by a first-order difference to appear at the filter output. Considering that the oversampling ratio in many audio-band $\Sigma\Delta$ modulators is equal to or higher than 128, the integrated reference noise power in the signal band is reduced by more than 40 dB at the filter output. To verify the effectiveness of the proposed switching scheme, two experimental prototypes have been implemented using 0.25- $\mu\mbox{m}$ devices in a 28-nm CMOS technology: one with a conventional reference switching scheme and the other with the proposed one. The measured results show that, in the proposed filter, the noise floor in the signal band is significantly reduced, which results in an improved converter dynamic range.

A 100-nW 9.1-ENOB 20-kS/s SAR ADC for Portable Pulse Oximeter

This brief presents an energy-efficient 10-bit accuracy with 20-kS/s successive approximation register analog-to-digital converter for portable pulse oximeter. A data-dependent capacitor reset (DDCR) switching scheme for the capacitive digital-to-analog converter (CDAC) to reduce the average switching energy and the number of unit capacitors is proposed and implemented. Compared with the conventional capacitor switching scheme for CDACs, the proposed DDCR switching scheme reduces the average switching energy and the total number of unit capacitors by 97% and 75%, respectively. We achieved a signal-to-noise-and-distortion ratio of 56.5 dB and a spurious-free dynamic range of 64.7 dBc at the Nyquist input frequency. The measured peak differential and integral nonlinearities are 0.44 and 0.58 least significant bit, respectively. The figure of merit is 9.1 fJ/conversion-step. The prototype, fabricated in the 0.11- $\mu\mbox{m}$ CMOS process, occupies 0.033 mm2.

Pulse delay control for capacitor voltage balancing in a three‐level boost neutral point clamped inverter

The cross regulation effect in multi-output DC/DC converters offers a reliable support for the grid integration of multilevel inverters by balancing the capacitor voltages. The capacitor voltage balancing by single input dual output boost converter is often realised by conventional three-level switching scheme. The three-level operation benefits lower inductor ripple current, but it limits the maximum possible compensation voltages. In this study, the entire operating modes of the boost converter is presented and all the possible cases which contribute to the voltage balancing are employed for balancing the capacitor voltages in a three-level neutral point clamped inverter. A proportional-integral controller based duty ratio control and pulse delay control are used for DC link voltage regulation and capacitor voltage balancing. Since the classical state-space averaging technique is not suitable for SIDO converters, inductor current ripple averaging technique is utilised for controller design. The circuit simulation is performed in Matlab/Simulink. The digital controller is realised using the Virtex-5FPGA in Labview/CompactRIO module. Both simulation and experimental results are presented to validate the controller performance.

A pseudo‐differential current‐reuse structure for opamp‐sharing pipelined analog‐to‐digital converters

SummaryIn this paper, a power efficient pseudo‐differential (PD) current‐reuse structure is presented to alleviate the memory effects of opamp‐sharing in pipelined analog‐to‐digital converters. To implement the PD current‐reuse structure, a switched‐capacitor circuit is introduced for multiplying digital‐to‐analog converter, which has a slight modification compared with the conventional switching scheme with no power penalty. In the proposed multiplying digital‐to‐analog converter circuit, the common‐mode offset amplification of the PD structures is eliminated. Moreover, a PD current‐reuse amplifier is developed from the telescopic structure with an inverter‐based gain‐boosting circuit. The effectiveness of the proposed structure is evaluated in comparison with existing current‐reuse techniques. Copyright © 2014 John Wiley & Sons, Ltd.

A novel link switching scheme using pre-scanning and RSS prediction in visible light communication networks

Abstract Visible light communication (VLC) is gaining increasing attention and is considered as a promising technology for future wireless indoor communications. Because movable users expect a seamless connectivity experience when switching among transmitters (i.e., VLC access points) in the VLC system, fast link switching operations must be supported by the networks. This paper presents a novel hard link switching scheme for VLC networks with the use of pre-scanning and received signal strength (RSS) prediction. Our proposed scheme achieves the advantages of both conventional hard and soft link switching schemes without changing device hardware or the IEEE 802.15.7 medium access control (MAC) protocol. To help compare our proposed scheme with conventional hard and soft link switching schemes, the signal-to-interference-plus-noise ratio (SINR), the outage probability regarding the link switching situation, and the queuing models for link switching schemes are taken into account. Simulation and numerical results validate that our proposed scheme outperforms conventional hard and soft link switching schemes.

Balanced Switching Schemes for Gradient-Error Compensation in Current-Steering DACs

This paper introduces balanced switching schemes to compensate linear and quadratic gradient errors, in the unary current source array of a current-steering digital-to-analog converter (DAC). A novel algorithm is proposed to avoid the accumulation of gradient errors, yielding much less integral nonlinearities (INLs) than conventional switching schemes. Switching scheme examples with different number of current cells are also exhibited in this paper, including symmetric arrays and nonsymmetric arrays in round and square outlines. (a) For symmetric arrays where each cell is divided into two parallel concentric ones, the simulated INL of the proposed round/square switching scheme is less than 25%/40% of conventional switching schemes, respectively. Such improvement is achieved by the cancelation of linear errors and the reduction of accumulated quadratic errors to near the absolute lower bound, using the proposed balanced algorithm. (b) For non-symmetric arrays, i.e. arrays where cells are not divided into parallel ones, linear errors cannot be canceled, and the accumulated INL varies with different quadratic error distribution centers. In this case, the proposed algorithm strictly controls the accumulation of quadratic gradient errors, and different from the algorithm in symmetric arrays, linear errors are also strictly controlled in two orthogonal directions simultaneously. Therefore, the INLs of the proposed non-symmetric switching schemes are less than 64% of conventional switching schemes. key words: digital-to-analog converter, gradient errors, nonlinearity, switching scheme, the integral nonlinearity

Smooth motion control of the adaptive cruise control system by a virtual lead vehicle

The adaptive cruise control system maintains the appropriate distance to the lead vehicle when the lead vehicle exists and maintains the desired speed when no lead vehicle is detected. A virtual lead vehicle scheme is introduced to make the switching between the speed control algorithm and the distance control algorithm unnecessary and simplify the structure of the control system. The speed and the position of the virtual vehicle can be decided by the control system according to the current situation. Smoother responses are achieved by the virtual lead vehicle scheme compared to the conventional mode switching scheme. This method is also shown to provide a good reaction for when a lead vehicle cuts in or out. A linear quadratic controller with variable weights is suggested to control the virtual lead vehicle. This scheme shows improved performance in terms of passenger comfort and fuel efficiency of the host vehicle.

Reduced Sideband Levels in Time-Modulated Arrays Using Half-Power Sub-Arraying Techniques

A new approach to reducing the sidebands levels and power losses in the harmonic patterns of time-modulated linear arrays is presented. The approach is based on reducing the static element weights of the outer elements of a linear array using simple 3 dB power dividers. This approach allows the relative switch-on times of the outer elements of the array to be increased which reduces the transients in the time-domain output from the array and results in lower sideband levels. Numerical results are presented to illustrate and compare the approach to conventional switching schemes.

A Soft-Switching Scheme for an Isolated DC/DC Converter With Pulsating DC Output for a Three-Phase High-Frequency-Link PWM Converter

This paper outlines a soft-switching mechanism based on zero-voltage-zero-current-switching (ZVZCS) principle for the front-end isolated DC/DC converter of an isolated three-phase rectifier-type high-frequency-link bidirectional power converter. In conjunction with a back-end DC/AC converter operating with a novel patent-filed hybrid modulation scheme outlined in , , and that reduces the number of hard-switched commutation per switching cycle, the proposed ZVZCS scheme can lead to less overall switching losses than other conventional switching schemes. The proposed ZVZCS scheme is effective for various load conditions, operates seamlessly with a simple active-clamp circuit, and is suitable for applications where low-voltage dc to high-voltage three-phase ac power conversion is required.

Mode Switching and Smooth Motion Generation for Adaptive Cruise Control Systems by a Virtual Lead Vehicle

The adaptive cruise control system maintains the appropriate distance to the lead vehicle when a lead vehicle exists, otherwise, it maintains the desired speed. These two objectives may be achieved by having two controllers, one for each objective, and a control mode switching logic. Introducing the virtual lead vehicle, however, only the distance control algorithm is used and the structure of the system can be significantly simplified. The speed and the location of the virtual vehicle are given by the control system according to the current situation. Smoother responses are achieved by the virtual lead vehicle scheme compared to the conventional mode switching scheme. The virtual lead vehicle scheme also generates smooth reaction for the host vehicle when the lead vehicle cut out or a vehicle cuts in from a side lane.

Enhanced H.264/AVC stream switching over varying bandwidth networks

This paper proposes an efficient video stream switching scheme among compressed video streams coded at different quality levels and bit rates. The conventional stream switching scheme in H2.64/AVC is effective in switching, but degrades the compression efficiency of the transmitted stream even if the switching operation does not take place. In the proposed scheme, no modification is made to the original compressed streams so the compression efficiency is maintained at switching points. Consequently switching points can be assigned flexibly in our efficient scheme without noticeable bit rate overhead. It is shown by experimental results that the proposed scheme outperforms the conventional switching scheme.

Comparison of different switching patterns in direct torque control technique of induction motors

Abstract In this paper, the direct torque control (DTC) technique is used for induction motor control. Non-pulse-width modulation (NPWM) techniques are frequently preferred due to the high switching frequency resulting from conventional PWM switching schemes. Four different switching algorithms using hysteresis and non-hysteresis controllers are proposed and compared. Results are presented of the steady-state and dynamic behaviour of a drive with speed and torque references, controlled using the four switching techniques. The harmonic spectra of the stator voltage and current are determined and compared for the four switching techniques. The results indicate that the non-hysteresis controllers are cheaper and consume less electric power than the hysteresis controllers. Among these algorithms, the non-hysteresis controllers, referred to as the two-band flux controller and the triple-band torque controller, lead to a better result with an advantage of simpler control algorithms.