Conventional Successive Approximation Register Analog-to-digital Converter Research Articles

A low‐power and area‐efficient ultrasound receiver using beamforming successive approximation register analog‐to‐digital converter with capacitive digital‐to‐analog converter combined delay cell structure for 3‐D imaging systems

The authors present a low-power area-efficient subarray beamforming receiver (RX) structure for a miniaturized 3-D ultrasound imaging system. Given that the delay-and-sum (DAS) and digitization functions consume most of the area and power in the receiver, the beamforming successive approximation register (SAR) analog-to-digital converter (ADC) shares its capacitive digital-to-analog converter (CDAC) with the delay cells. As a result, the delay cells implemented with capacitors are embedded in the CDAC with significant area reduction, further eliminating the need for power-hungry ADC buffers. Furthermore, the dual reference 10-bit SAR ADC reduces the area of CDAC by 32 times, achieving a switching energy reduction of 98.3%, compared to the conventional SAR ADC. As a result, the proposed beamforming SAR ADC, simulated using a 0.18 μm CMOS process, consumes 230 μW per channel, significantly reducing the per channel capacitance.

An 80 dB Second-order Noise Shaping SAR ADC using Differential Integral Capacitors and Comparator with Voltage Gain Calibration

A second-order noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) is proposed for sensor interface applications. It consists of a capacitor-resistor hybrid digital-to-analog-converter (C-R DAC) with 10-bit resolution, a comparator with three inputs, a SAR logic, and a second passive integrator using two differential capacitors. The use of a C-R DAC and two differential capacitors reduces the capacitor area of the conventional NS SAR ADC by 86.25%. Voltage gain calibration for the three-input comparator is proposed to maximize the performance of the NS SAR ADC. The proposed second-order NS ADC is designed using a 180-nm CMOS process with a supply of 1.8 V. The proposed second-order NS SAR ADC with an over sampling ratio of 8 has a SNDR of 80.18 dB and an ENOB of 13.03 bits. Its area and power consumption are 0.165 ㎟ and 248 μW, respectively.

Low-Power Switching Scheme with Quarter Reference Voltage Sources for SAR ADCs

In this paper, an energy-efficient switching scheme with additional quarter-reference voltage sources in a successive approximation register (SAR) analog-to-digital converter (ADC) is proposed for a low power and small area device for frequency modulated continuous wave (FMCW) radar transceivers. Recently, state-of-the-art ADCs have adopted a configuration that also uses Vref/2 as the reference voltage of the ADCs to improve the switching energy of capacitive digital-to-analog converter (CDAC). The proposed switching configuration additionally uses Vref/4 and 3Vref/4 reference voltages as the reference voltage of CDAC. Compared to state-of-the-art configurations that use the additional reference voltage of Vref/2, the average switching energy, and the total capacitance of CDAC in the proposed configuration are reduced by about 87.5% and 50%, respectively. In this switching scheme, the CDAC output voltage gradually converges to Vref/2, like with conventional SAR ADCs, which minimizes the dynamic offset that deteriorates the linearity of the SAR ADC.

An Energy-Efficient 12b 2.56 MS/s SAR ADC Using Successive Scaling of Reference Voltages

This paper presents an energy efficient architecture for successive approximation register (SAR) analog to digital converter (ADC). SAR ADCs with a capacitor array structure have been widely used because of its simple architecture and relatively high speed. However, conventional SAR ADCs consume relatively high energy due to the large number of capacitors used in the capacitor array and their sizes scaled up along with the number of bits. The proposed architecture reduces the energy consumption as well as the capacitor size by employing a new array architecture that scales down the reference voltages instead of scaling up the capacitor sizes. The proposed 12-bit SAR ADC is implemented in Complementary Metal Oxide Semiconductor (CMOS) library using Cadence Virtuoso design tool. Simulation results and mathematical model demonstrate the overall energy savings of up to 97.3% compared with conventional SAR ADC, compared with the SAR ADC with split capacitor, and compared with the resistor and capacitor (R&C) Hybrid SAR ADC. The ADC achieves an effective number of bits (ENOB) of bits and consumes at sampling rate of , offering an energy consumption of per conversion step. The proposed SAR ADC offers 95.5% reduction in chip core area compared to conventional architecture, while occupying an active area of .

A 99.15% energy-reduced switching scheme based on HSRS coarse–fine architecture for SAR ADCs

A trade-off switching scheme between high efficiency and considerable area overhead for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. During the design process, the higher-side-reset-and-set (HSRS) coarse–fine architecture ensures significant energy saving. There is no energy consumption in the first two comparison cycles. The presented switching scheme achieves 99.15% savings in switching energy and 92.1% reduction in total capacitance, compared with the conventional SAR ADC. Benefit from the HSRS method, an improved HSRS scheme is proposed to reduce the switching energy in the coarse quantization process, achieving 1/16CVref2 energy saving for the third comparison cycle compared with HSRS method. Furthermore, the reset energy is verified to be 0.1367CVref2 due to the energy-free charge distribution and capacitor multiplexing (CDCM) technology adopted in the fine quantization process.

A Switched Capacitor-Based SAR ADC Employing a Passive Reference Charge Sharing and Charge Accumulation Technique

In this work, a switched capacitor-based successive approximation register (SAR) analog-to-digital converter (ADC) using a passive reference charge sharing and charge accumulation is proposed. For N-bit resolution, the fully differential version of this architecture needs only 6 capacitors, which is a significant improvement over conventional binary-weighted SAR ADC. The proposed SAR ADC is first modeled in MATLAB, and the effect of practical operational transconductance amplifier limitations such as finite values of gain, unity-gain bandwidth and slew rate on ADC characteristics is verified through behavioral simulations. To validate the proposed ADC performance, an 11-bit 2 kS/s SAR ADC is designed and laid out in UMC 180 nm 1P6M CMOS technology with a supply voltage of 1.8 V. The total design occupies an area of $$568\,\upmu \hbox {m} \times 298\,\upmu \hbox {m}$$ and consumes a power as less as $$0.28\,\upmu \hbox {W}$$ . It is found that the integral nonlinearity and differential nonlinearity of this ADC are in the range + 0.35/− 0.84 least significant bit (LSB) and + 0.1/− 0.6 LSB, respectively. In addition, dynamic performance test shows that the proposed SAR ADC offers an effective number of bits of 10.14 and a Walden figure of merit (FoMW) of 0.12 pJ/conv-step.

A 10 Bit 5 MS/s Column SAR ADC With Digital Error Correction for CMOS Image Sensors

This brief proposes a successive approximation register (SAR) analog-to-digital converter (ADC) whose readout speed is improved by 33%, through applying a digital error correction (DEC) method, compared to an alternative without using the DEC technique. The proposed addition-only DEC alleviates the ADC's incomplete settling errors, hence improving conversion rate while maintaining accuracy. It is based on a binary bridged SAR architecture with 4 redundant capacitors and conversion cycles, which ensure the ADC's linearity of 10 bit within a 5 bit accuracy's settling time. The proposed SAR keeps the same straightforward timing diagram as that in a conventional SAR ADC, incurring no offset to the ADC. Measurement results of 15 columns of SAR ADCs, sampling at 5 MS/s on the same CMOS image sensor (CIS) chip, show integral nonlinearity (INL) around 3 LSB (1LSB = 1 mV), when sampling at 5 MHz, after a proposed swift digital background calibration that incurs no additional hardware complexity. The CIS array read out by the proposed column-level SAR ADCs is measured reasonable photoelectron transfer characteristics.

Low-power asymmetric switching scheme with segmented capacitive architecture for SAR ADCs

In this paper, an energy-efficient asymmetric switching scheme with segmented capacitive architecture in successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed for biomedical applications. Based on the segmented digital-to-analog converter architecture, the proposed method curtails the area overhead by 92% in comparison with the conventional switching method. Additionally, combining a new tri-level switching scheme, the one-side technique and the split-MSB mode, the proposed asymmetric switching scheme achieves 99.68% less switching energy over the conventional SAR ADC.

An Ultra-Low Power Consumption High-Linearity Switching Scheme for SAR ADC

An ultra-low power consumption high-linearity switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented with a mixed switching method. Based on the combination of C-2C dummy capacitors, the charge sharing technique and monotonic switching method, the proposed switching method achieves high-energy saving and high linearity. Compared with the conventional SAR ADC, the proposed method consumes no reset energy and achieves 98.9% less switching energy and 87.2% reduction in capacitor area. Moreover, the proposed scheme obtains good performance in linearity. Furthermore, the common-mode voltage variation of the proposed scheme is smaller than other published schemes, which is important for decreasing input-dependent offset of the comparator.

A 99.8% Energy-Reduced Two-Stage Mixed Switching Scheme for SAR ADC Without Reset Energy

An ultra-low power consumption two-stage mixed switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented. Using two simple switches, the novel switching scheme divides the capacitor arrays into two sub-arrays: stage-one and stage-two arrays. The two sub-arrays convert high and low bits cycles, respectively. Once the high bits conversion cycles are completed, the corresponding sub-arrays are split off from the capacitor arrays. This decreases the number of capacitors used in the rest conversion procedure. Thus, the proposed method improves the energy efficiency of SAR ADC. Thanks to C–2C dummy capacitors and two-stage capacitor arrays, the novel architecture achieves 86% reduction in capacitor area than conventional SAR ADC. Furthermore, based on the charge sharing technique and monotonic switching method, the proposed switching scheme does not consume reset energy and achieves 99.8% less switching energy than the conventional switching method. In addition, the proposed scheme is less sensitive to capacitor mismatch because of its great performance in linearity.

An energy-efficient DAC switching algorithm based on charge recycling method for SAR ADCs

This paper configures a successive approximation register (SAR) analog-to-digital converter (ADC) based on a new switching algorithm with efficient energy consumption. The proposed switching algorithm applies the same reference voltage to the bottom plates of all capacitors in each capacitor array to drain no energy through capacitors. In addition to a 100% energy saving in the switched-capacitor digital-to-analog converter (DAC) block, configuration of an N-bit SAR ADC shows a 50% capacitor area reduction in comparison with the conventional SAR ADC.

A 99.77% energy-reduced asymmetric capacitance switching scheme for SAR ADC with split-capacitor method

A highly energy-efficient, highly area-efficient asymmetric capacitance switching scheme for successive approximation register (SAR) analog-to-digital converters (ADC) is presented. Based on the monotonic switching procedure and asymmetric capacitance array, the novel architecture achieves 97.65% reduction in capacitor area over the conventional SAR ADC. Besides, with the split-capacitor method and most significant bit split switching procedure, the proposed switching scheme achieves 99.77% less switching energy compared with the conventional switching method.

A charge-sharing switching scheme for SAR ADCs in biomedical applications

This paper presents a charge-sharing switching scheme for successive approximation register (SAR) analog-to-digital converters (ADCs) in biomedical applications. By using the charge sharing between two capacitor arrays to generate binary-weighted voltage-changes sequentially on the dummy capacitor, which is used to compare the multiple low bits, the proposed switching method enhances the efficiency of switching energy by 99.51% and achieves a 93.55% reduction in the total capacitor size, compared with the conventional SAR ADC.

An Energy-Efficient DAC Switching Method for SAR ADCs

This brief presents a capacitor switching technique to reduce the power consumption in successive approximation register (SAR) analog-to-digital converters (ADCs). The proposed method ideally does not consume any switching energy in digital-to-analog converter and for a 10-bit ADC; it achieves 87% reduction in the total capacitor area compared to the conventional SAR ADC. In addition, the accuracy of the proposed SAR ADC does not depend on the accuracy of the mid-level reference voltage ( $ {V}_{\text{cm}}$ ). Moreover, the common-mode input voltage of the comparator will remain constant. The proposed ADC is simulated in a 90-nm CMOS technology with sampling rate of 100 kS/s and resolution of 10-bit. The simulation results achieve an 8.5 effective number of bits with about 0.5- ${\mu }\text{W}$ power consumption resulting in a FoM of 9.76 fJ/conversion-step.

High-Resolution SAR ADC With Enhanced Linearity

This brief proposes two digital-to-analog converter switching techniques for binary-weighted capacitor array successive approximation register (SAR) analog-to-digital converter (ADC), rotating&averaging without redundancy technique and rotating&averaging with redundancy technique. The rotating&averaging without redundancy technique can improve the signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR) of conventional SAR ADCs by averaging four samples for one input voltage, while the rotating&averaging with redundancy has better static linearity improvement but less SNR improvement than the rotating&averaging without redundancy technique. The application of these two methods to 14-bit SAR ADC is demonstrated by Monte-Carlo runs, results show that with a mismatch error typical of modern technology, the proposed rotating&averaging with redundancy scheme can improve the root-mean-square of integral nonlinearity from 2.08 to 0.57 LSB, and the SFDR is more than 15 dB better. On the other hand, the averaged SNR of 7.7 dB is improved by using the proposed rotating&averaging without redundancy technique for a 14-bit SAR ADC. Furthermore, the schemes proposed require only small additional circuit on a typical SAR ADC configuration, which are more feasible to implement high-resolution SAR ADC compared with the traditional calibration schemes.

Pipelining method for low-power and high-speed SAR ADC design

A low power analog to digital converter (ADC), based on a pipelining method employed in successive approximation register (SAR) architecture is presented. This structure is a two-stage pipeline SAR ADC with asymmetrical time interleaved (TI) channels, aimed to reach sampling rate as high as about threefold of a conventional SAR ADC while benefiting from its low power consumption and small area. Passive residue conversion without inter-stage amplifier and symphonic collaboration of stages are employed to design a low power, high speed, and accurate converter. In the proposed architecture, every signal sample experiences equal comparator offset during its conversion due to the applied novel operation sequence, without adding redundancy or comparator rotation scheme. A 7-bit ADC with sampling rate of 83 MS/s based on the proposed architecture is designed and its performance is verified by post layout simulation results in a 180-nm CMOS Technology. Both system level analysis and simulation verifications support proposed architecture superiority over similar reported SAR architectures.

A Single-Ended ADC with Split Dual-Capacitive-Array for Multi-Channel Systems

This paper presents a power and area efficient SAR ADC for multi-channel near threshold- voltage (NTV) applications such as neural recording systems. This work proposes a split dual-capacitive- array (S-DCA) structure with shifted input range for ultra low-switching energy and architecture of multi- channel single-ended SAR ADC which employs only one comparator. In addition, the proposed ADC has the same amount of equivalent capacitance at two comparator inputs, which minimizes the kickback noise. Compared with conventional SAR ADC, this work reduces the total capacitance and switching energy by 84.8% and 91.3%, respectively. Index Terms—Multi channel, Near threshold-voltage (NTV), Analog-to-digital converter (ADC), Digital-to- analog converter (DAC), Successive approximation register (SAR), Split dual-capacitive-array (S-DCA)

A 1.33 μW 8.02-ENOB 100 kS/s successive approximation ADC with supply reduction technique for implantable retinal prosthesis.

This paper presents a chip level 9 bits Charge Folding Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) to be used in a CMOS image sensor for retinal prosthesis. It has a maximum single-ended input range of 1.8 V but only uses a supply voltage of 0.9 V for the entire ADC through the Charge Folding method. Therefore, the input range is no longer limited by the supply rail as in conventional SAR ADC. Moreover, the ADC is controlled by an internal delay line based Asynchronous Clock Generator which can be programmed to adjust the resolution of the ADC from 5 to 9 bits. Therefore, resolution adaptation function can be applied to improve the energy efficiency up to 15%. The test chip is implemented in 0.18 μm CMOS process and occupies an area of 0.15 mm(2). At 0.9 V and 100 kS/s, the 9 bit s ADC consumes 1.33 μW and achieves an energy efficiency of 51.3 fJ/conversion-step . In addition, the power consumption can be further reduced by scaling the supply voltage and sampling frequency. At 100 kS/s, this ADC is capable of converting the input signal at a rate equivalent to 30 frames/s for a pixel array up to 3200 pixels.

A 1.0 V 12-bit 500 kS/s SAR ADC With Background Calibration for BioMedical Application

A 1.0 V 12-bit 500 kS/s SAR ADC With Background Calibration for BioMedical Application

A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications

This paper presents an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) for biomedical applications. To reduce energy consumption, a bypass window technique is used to select switching sequences to skip several conversion steps when the signal is within a predefined small window. The power consumptions of the capacitive digital-to-analog converter (DAC), latch comparator, and digital control circuit of the proposed ADC are lower than those of a conventional SAR ADC. The proposed bypass window tolerates the DAC settling error and comparator voltage offset in the first four phases and suppresses the peak DNL and INL values. A proof-of-concept prototype was fabricated in 0.18-μm 1P6M CMOS technology. At a 0.6-V supply voltage and a 200-kS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio of 57.97 dB and consumes 1.04 μW, resulting in a figure of merit of 8.03 fJ/conversion-step. The ADC core occupies an active area of only 0.082 mm2.