A 99.15% energy-reduced switching scheme based on HSRS coarse–fine architecture for SAR ADCs

Abstract

A trade-off switching scheme between high efficiency and considerable area overhead for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. During the design process, the higher-side-reset-and-set (HSRS) coarse–fine architecture ensures significant energy saving. There is no energy consumption in the first two comparison cycles. The presented switching scheme achieves 99.15% savings in switching energy and 92.1% reduction in total capacitance, compared with the conventional SAR ADC. Benefit from the HSRS method, an improved HSRS scheme is proposed to reduce the switching energy in the coarse quantization process, achieving 1/16CVref2 energy saving for the third comparison cycle compared with HSRS method. Furthermore, the reset energy is verified to be 0.1367CVref2 due to the energy-free charge distribution and capacitor multiplexing (CDCM) technology adopted in the fine quantization process.