Conventional Silicon Dioxide Research Articles

Applications of plasma-based technology to microelectronics and biomedical engineering

Plasma-based ion implantation and deposition techniques are widely used in many applications. In addition to the ability to modify the materials surface, novel structures can be fabricated. Another advantage is that the surface characteristics such as mechanical properties and biocompatibility can be selectively enhanced with the favorable bulk attributes of the materials unchanged. In this invited paper, our recent research activities on microelectronics and biomedical engineering are reviewed. Silicon-on-insulator (SOI) is expected to replace conventional bulk silicon substrates in many high speed, low power microelectronic devices because it possesses advantages such as reduction of parasitic capacitance, excellent sub-threshold slope, elimination of latch up, and resistance to radiation. However, wider applications of SOI in microelectronics are hampered by the self-heating effects caused by the poor thermal conductivity of the buried silicon dioxide layer. We have produced alternative buried insulators such as diamond-like carbon that possesses better thermal conductivity compared to conventional silicon dioxide using plasma immersion ion implantation and deposition (PIII&D) and successfully fabricated SOI structures with improved thermal stability. The use of low-energy plasma hydrogenation to substitute for the costly beam-line hydrogen ion implantation in the ion-cutting layer transfer technology is also discussed. In biomedical engineering, plasma spraying is a versatile technique to produce relatively thick ceramic coatings on orthopedic implant surfaces. We have discovered that plasma-sprayed nano-structured TiO 2 coatings favor the growth of apatite. The surface bioactivity is enhanced by hydrogen plasma implantation and the mechanism is discussed. The antibacterial properties of polymers can also be improved by implanting elements such as Ag and Cu and recent work in our laboratory is described.

Indium oxides by reactive ion beam assisted evaporation: From material study to device application

Indium oxides were deposited by reactive ion beam assisted e-beam evaporation at room temperature. A material study was conducted through a variety of material characterization including crystal structure, electrical properties, optical properties, and chemical composition, along with an investigation of material properties as a function of primary deposition parameters such as ion flux and deposition rate. Implementing the developed semiconducting indium oxide as a channel material, the authors further demonstrated high-performance indium oxide thin-film transistors (TFTs) with conventional silicon dioxide gate dielectric derived by plasma-enhanced chemical vapor deposition (PECVD). The n-channel TFT has a threshold voltage of ∼2.0 V, a field-effect mobility of 33 cm2/V s at a gate bias of 20 V, an ON/OFF current ratio of 108, and a subthreshold slope of 2.0 V/decade. The stability study displays a small threshold voltage shift of ∼0.6 V under a 60 h constant current stress condition. The TFT reported here has one of the best performance characteristics in terms of field-effect mobility, ON/OFF current ratio, OFF current and device stability, using conventional and large-area foundry-compatible PECVD gate dielectrics. The device performance coupled with PECVD dielectrics makes ion beam assisted e-beam evaporation derived indium oxide TFT a promising candidate for active matrix flat-panel displays.

Quick planarisation based on hydrogen silsesquioxane (HSQ) for deep etched InP based structures

The ability of HSQ resist films to planarise active deep etched (1.5–2 µm) InP based structures with electrodes is demonstrated for the first time. Vertically etched III-V semiconductor devices require planarisation of the passivation material for metal interconnections and device integration. A new and quicker method is presented, for which it is not necessary to use mask opening on the top of the devices to define via patterns. A comparison between conventional silicon dioxide (SiO2) planarisation and the demonstrated HSQ method validates the interest of the latter.

Plasma-Induced Damage in High-$k$/Metal Gate Stack Dry Etch

Plasma-based dry etch is used as the industry standard gate etch in conventional CMOS fabrication flow. However, past studies indicate that plasma-induced dry etch may impact device performance. The current research trend toward replacing conventional silicon dioxide and polysilicon gate stacks with high-k/metal gate stacks introduces a new challenge: development of new dry etch processes for critical new metals and their alloys. In this letter, a comparative study in the context of device performance has been conducted to compare dry etch versus wet etch for gate stack etch of hafnium oxide/tantalum silicon nitride gate stack. It has been found that the dry-etched gate stack exhibit significantly more gate leakage current and poorer uniformity in threshold-voltage distribution

Fringing Electric Field Effect on 65-nm-Node Fully Depleted Silicon-on-Insulator Devices

In this study, the fringing electric field effect on 65-nm-node technology fully depleted silicon-on-insulator (FD SOI) device is comprehensively examined. A new anomalous degradation in device on-state/off-state characteristics on a nanoscale metal–oxide–semiconductor field-effect transistor (MOSFET) with high-κ gate dielectrics is reported, the so-called fringing-induced barrier lowering (FIBL). This is due to the decrease in fringing electric field and increase in the gate dielectric thickness when gate dielectric permittivity increased. We observe that FIBL can be effectively suppressed using a stack gate dielectric structure. In addition, we also implement a high-κ offset spacer to further improve the on-state driving current Ion to approximately 26% higher than that of a conventional silicon dioxide offset spacer and reduce the off-state leakage current Ioff by about 34%. This benefit is due to the enhanced high vertical channel electric field obtained via the offset spacer using a high-κ material as a spacer. This enhanced fringing electric field can markedly increase Ion/Ioff current ratio and reduce subthreshold swing (S-factor) to improve MOSFET performance, which implies that gate-to-channel controllability can be improved markedly. This would play an important role beyond the 65-nm-node technology.

Measurement of the silicon dioxide concentration in hafnium silicate gate dielectrics with a total reflection X-ray fluorescence spectroscopy

As complementary metal oxide semiconductor devices continue to scale along the rapid pace of Moore’s law, gate dielectric materials with significantly higher dielectric constant (k=10–25) are being evaluated as replacements for conventional silicon dioxide, SiO2 (k=3.9), and silicon oxynitride. This allows for the introduction of a physically thicker film with lower leakage current and with capacitance equivalent to a thinner (1.0 nm and below) SiO2 layer (Schlom and Haeni, 2002; Wilk et al., 2001; Kingon et al., 2001). Although binary metal oxide films such as HfO2 and ZrO2 exhibit higher permittivity than their corresponding silicates and aluminates, alloyed with various molecular percents of SiO2 or Al2O3, respectively, they are compromised by lower onset of crystallization temperature which contributes a higher degree of interfacial microroughness and increased gate leakage current due to dislocations and oxygen vacancies generated along grain boundaries. Accordingly, development of hafnium silicate has been the subject of intense investigation as an advanced gate dielectric thin film designed to meet the device manufacturing requirements of thermal stability in direct contact with substrate silicon and metal gate electrode materials. In this paper, we present results corresponding to the utilization of total reflection X-ray fluorescence spectroscopy (TXRF) as a quick, accurate, nondestructive technique for hafnium silicate composition determination based on detection of the Hf:Si ratio of (HfO2)x(SiO2)1−x, where x varies over the range 0.2–1.0.

Development of a bio‐based composite material from soybean oil and keratin fibers

AbstractA novel bio‐based composite material, suitable for electronic as well as automotive and aeronautical applications, was developed from soybean oils and keratin feather fibers (KF). This environmentally friendly, low‐cost composite can be a substitute for petroleum‐based composite materials. Keratin fibers are a hollow, light, and tough material and are compatible with several soybean (S) resins, such as acrylated epoxidized soybean oil (AESO). The new KFS lightweight composites have a density ρ ≈ 1 g/cm3, when the KF volume fraction is 30%. The hollow keratin fibers were not filled by resin infusion and the composite retained a significant volume of air in the hollow structure of the fibers. Due to the retained air, the dielectric constant, k, of the composite material was in the range of 1.7–2.7, depending on the fiber volume fraction, and these values are significantly lower than the conventional silicon dioxide or epoxy, or polymer dielectric insulators. The coefficient of thermal expansion (CTE) of the 30 wt % composite was 67.4 ppm/°C; this value is low enough for electronic application and similar to the value of silicon materials or polyimides used in printed circuit boards. The water absorption of the AESO polymer was 0.5 wt % at equilibrium and the diffusion coefficient in the KFS composites was dependent on the keratin fiber content. The incorporation of keratin fibers in the soy oil polymer enhanced the mechanical properties such as storage modulus, fracture toughness, and flexural properties, ca. 100% increase at 30 vol %. The fracture energy of a single keratin fiber in the composite was determined to be about 3 kJ/m2 with a fracture stress of about 100–200 MPa. Considerable improvements in the KFS composite properties should be possible by optimization of the resin structure and fiber selection. © 2005 Wiley Periodicals, Inc. J Appl Polym Sci 95: 1524–1538, 2005

Low Dielectric Constant Material from Hollow Fibers and Plant Oil

A new low dielectric constant (k) material suited to electronic materials applications was developed using hollow keratin fibers (HF) and chemically modified soybean oil. High-speed microelectronics is facilitated by preventing the “rubber necking,” or slow-down of electrons on the printed wires through the use of low-k dielectrics. The unusual low-k value of the HF composite material derives both from the air (k = 1) in the hollow microcrystalline keratin fibers (k = 1.7), and the triglyceride molecules (k = 2.7), and is in the range of 1.7 to 2.7, depending on the HF fraction. These values are lower than that of the conventional silicon dioxide (k = 3.8 to 4.2) or epoxy dielectric insulators. Also, the HF dielectric is lightweight (SG < 1) and rigid (Modulus > 2 GPa), with fracture toughness (1.0 MPa m1/2) and approximates the shape and feel of a silicon dioxide insulator. The coefficient of thermal expansion (CTE) of the new material (67.4 ppm/°C) is low enough for electronic materials applications. Multi-Chip-Module circuit printing results suggest that the low-cost composite made with HF (from avian sources) and plant oil (from soybean) has the potential to replace the dielectrics in microchips and circuits boards in the ever-growing electronic materials field, in addition to many applications as new lightweight composite material.

The effects of surface-plasma treatment of thin-film hydrogen silesquioxane low k dielectric

Hydrogen silesquioxane (HSQ) is a low dielectric constant material and a potential substitute for conventional silicon dioxide insulator in ULSI system. In this study, the effect of plasma treatment on HSQ films is investigated. The bond structure changes of HSQ after curing, plasma treatment, and water absorption were observed with Fourier transform infrared spectroscopy. Densification of the film occurs after curing, the higher the curing temperature, the lower the dielectric constant and refractive index of the film. Both H2- and O2-plasma treatments are employed in this study. The H2-plasma bombardment enhances the formation of the network structure but raises the moisture absorption of HSQ films. It is found that films subjected to both H2- and O2-plasma treatments have lower dielectric constant than those subjected to O2 treatment alone. Possible mechanisms for the effects of plasma treatments are explored. The residual stress of HSQ film is also studied.

A new structure of SOI MOSFET for reducing self-heating effect

We use the MEDICI (a two-dimensional, 2D, device simulator) to examine the 2D distribution of potential and carrier concentrations as well as current vectors in a device in order to predict its electrical characteristics for any bias condition. In this work, we investigated the high-temperature operation of SOI MOSFETs with SiO 2/Si 3N 4/SiO 2 buried insulators (we call it Multi-layered insulator structure), rather than the conventional silicon-dioxide (SiO 2). Since the thermal conductivity of this Multi-layered insulator is much higher than that of SiO 2, this new kind of silicon-on-insulator (SOI) structure will greatly reduce the often-severe self-heating problem of conventional SOI, making SOI potentially suitable for high-temperature applications. A detailed electrothermal transport model is used in the simulations in conjunction with conventional drift and diffusion equations. Also, we compare the performance of Multi-layer-based SOI with that of SiO 2-based SOI. We find that Multi-layered SOI does indeed remove the self-heating penalty of SOI.

The interface between silicon and a high-k oxide

The ability of the semiconductor industry to continue scaling microelectronic devices to ever smaller dimensions (a trend known as Moore's Law) is limited by quantum mechanical effects: as the thickness of conventional silicon dioxide (SiO(2)) gate insulators is reduced to just a few atomic layers, electrons can tunnel directly through the films. Continued device scaling will therefore probably require the replacement of the insulator with high-dielectric-constant (high-k) oxides, to increase its thickness, thus preventing tunnelling currents while retaining the electronic properties of an ultrathin SiO(2) film. Ultimately, such insulators will require an atomically defined interface with silicon without an interfacial SiO(2) layer for optimal performance. Following the first reports of epitaxial growth of AO and ABO(3) compounds on silicon, the formation of an atomically abrupt crystalline interface between strontium titanate and silicon was demonstrated. However, the atomic structure proposed for this interface is questionable because it requires silicon atoms that have coordinations rarely found elsewhere in nature. Here we describe first-principles calculations of the formation of the interface between silicon and strontium titanate and its atomic structure. Our study shows that atomic control of the interfacial structure by altering the chemical environment can dramatically improve the electronic properties of the interface to meet technological requirements. The interface structure and its chemistry may provide guidance for the selection process of other high-k gate oxides and for controlling their growth.

Thermal modeling of localized laser heating in multi-level interconnects

Thermal modeling was used to simulate thermal profiles from localized laser heating on two multi-level interconnect structures with metallization complexity comparable to those used in advanced interconnect systems. The modeling focused on addressing issues with regard to the effectiveness of laser-based techniques in defect localization in state-of-the-art metallization schemes. Modeling results indicate that indirect heating from the laser does not propagate effectively through adjacent metal layers from both the front side and the back side. Poor heat conduction and its associated thermal spreading during laser heating make defect detection difficult beyond three levels of metal. Thermal distribution and spreading were found to be more affected by interconnect geometries than by variations in laser spot size. Smaller temperature rises during laser heating were observed in the newer interconnect structures consisting of copper and low- k dielectric materials than in those with conventional aluminum, tungsten, and silicon dioxide. The smaller temperature rise leads to weaker signal strength at the defect sites and makes it more difficult to detect defects in the newer-material structures. Metallization density also affects heat conduction in advanced interconnect systems but the temperature rise during laser heating varies slowly as a function of metallization density.

Contact angle measurements for adhesion energy evaluation of silver and copper films on parylene-n and SiO2 substrates

Copper and silver films are being considered for future multilevel interconnect systems. The reduction of feature size has also demanded the use of different low-dielectric materials (e.g., parylenes) in place of conventional silicon dioxide based layers. Adhesion of these materials with each other is a major hurdle in the reliable and durable performance of the devices. Contact angle measurements are used to measure adhesion energies of Cu and Ag layers on substrates of either SiO2 and Pa–n. Qualitative tape-test analysis indicates improved adhesion of these films with anneal and plasma treatment. Surface energy increase of parylene–n using oxygen plasma treatment is demonstrated using sessile water-drop method. The increase in adhesion for the Ag/Pa–n system is attributed to increased roughness and presence of carbonyl groups on the surface. The contact angle measurements are corrected to compensate for the effect of roughness. The adhesion energy for Ag/Pa–n system increases from 0.33 to 1.28 N/m with plasma treatment. Higher-surface energies of copper at room temperature attribute to higher-copper adhesion energy when compared to that of silver.

The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K/sub gate/) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K/sub gate/ for different target subthreshold leakage currents has been identified.

Polarity Dependence of Degradation in Ultra Thin Oxide and JVD Nitride Gate Dielectrics

AbstractWe have studied high field degradation of Jet Vapor Deposited (JVD) silicon nitride MNSFETs with DC stress fields and compared their degradation with conventional silicon dioxide MOSFETs under identical stress conditions. We have observed that in both oxide and nitride devices, the interface degradation is higher for negative gate field. Further, the relative degradation of nitrides is always lower compared to that of oxides for both positive and negative stress conditions. AC stress experiments were performed on these ultra thin oxide transistors to understand possible degradation processes. The frequency, the peak-to-peak and offset voltage of the applied AC signal are some of the parameters that have been varied. Detailed characterization results and an analysis of the degradation mechanisms are presented in this paper. We conclude that many of the degradation results can be explained using the trapped hole recombination model.

Enhancing the thermal stability of low dielectric constant hydrogen silsesquioxane by ion implantation

Low density material such as hydrogen silsesquioxane (HSQ) can provide a lower dielectric constant than a conventional silicon dioxide insulator. However, the thermal stability of as-cured HSQ is about 400°C. Both the leakage current and dielectric constant of HSQ rapidly increase with increasing annealing temperature. In this work, we study the enhancement of the thermal stability of the HSQ film by fluorine ion implantation treatment. The fluorine implantation step can enhance the thermal stability of the HSQ film as high as 500°C. In addition, the implantation treatment after the curing step is more efficient in enhancing the thermal stability of the HSQ film than before the curing step.

Ultra-thin dielectrics for semiconductor applications— growth and characteristics

As the physical dimensions of integrated circuit devices decrease the resultant dielectric thickness also decreases. However with this reduction in thickness particularly in the sub-15 nm region there are a number of undesirable physical and electrical effects associated with conventional silicon dioxide films. This paper considers the growth kinetics and resultant characteristics of such thin oxides as well as possible replacements by way of oxynitrides or nitrides. A comparison is made of each type of dielectric and their applicability to future semiconductor processing.