Conventional Silicon-controlled Rectifier Research Articles

4H-SiC-Based ESD Protection Design With Optimization of Segmented LIGBT for High-Voltage Applications

4H-SiC is a wide-bandgap material that exhibits excellent high-temperature conductivity and high operating voltage. These characteristics can provide high electrostatic discharge (ESD) robustness in high voltage applications. However, a considerably wide range of snapback phenomena is triggered for 4H-SiC-based ESD protection devices owing to a high critical electric field. In this study, an ESD protection device based on a lateral insulated-gate bipolar transistor (LIGBT) with a new structure that creates an internal silicon-controlled rectifier (SCR) path is proposed. The proposed ESD protection device minimizes the effective base region of the NPN parasitic bipolar transistor to the gate length based on the internal SCR operation of the LIGBT. It also adjusts the emitter injection efficiency of the PNP parasitic bipolar transistor by introducing a segment topology and inserting an additional implant area. Consequently, the proposed ESD protection device significantly improves the wide range of snapback phenomena occurring in the 4H-SiC materials. A conventional SCR, the LIGBT, and the proposed protection device were fabricated using the 4H-SiC process under the same condition, and their electrical characteristics were comparatively analyzed using a transmission-line pulse system. Moreover, its high-temperature reliability was evaluated at 300–500 K to examine the compatibility with 4H-SiC devices and circuits that require a relatively high-temperature operation.

Enhance the ESD Ability of UHV 300-V Circular LDMOS Components by Embedded SCRs and the Robustness P-Body Well

The ultra-high voltage (UHV) Lateral-diffused MOSFET (LDMOS) transistor has been widely used in power circuit applications and also used as an electrostatic discharge (ESD) self-protection device. However, the ESD ability of an UHV LDMOS is generally worse than that of low- and high-voltage (HV) devices, which means this UHV LDMOS device can be easily failed under an ESD event. Then, the method of embedded a silicon-controlled rectifier (SCR) into the HV LDMOS has been used in the HV circuit as an ESD protection technique. But when this architecture is applied to UHV devices, will its ESD capability be as good as in HV devices? A novel SCR with a P-body well architecture is proposed, which can effectively enhance the ESD ability of the UHV nLDMOS device when the drain side is embedded this new structure. The proposed structure can greatly improve the ESD capability of the device without adding any extra process step (& photomask), layout area and affecting the basic breakdown voltage. Finally, the proposed structure of the PPP-arranged type with the P-body well can greatly increase the ESD (FOM) ability which $\text{I}_{\mathrm{ t2}}$ and HBM ability can be increased by 68.7% and 22.2% (72.9%), respectively, as compared with the conventional SCR PPP-arranged type.

A Novel Dual-Directional SCR Structure With High Holding Voltage for 12-V Applications in 0.13-μm BCD Process

This article proposes a dual-directional silicon-controlled rectifier (SCR) with a novel structure and high holding voltage to improve the electrostatic discharge (ESD) design area efficiency in high-voltage environments. In terms of structure, by decreasing the emitter injection efficiency of the p-n-p parasitic bipolar transistor formed at the bottom of the gate region, the SCR positive feedback gain is reduced, which endows the proposed device with improved snapback characteristics compared with the conventional low-voltage triggering SCR (LVTSCR) and low-trigger dual directional SCR (LTDDSCR). This article conducted 2-D and mixed-mode simulations to compare and analyze the operating principles of the proposed and traditional devices. Additionally, experimental devices were fabricated under the same conditions using the 0.13- $\mu \text{m}$ process to verify their electrical properties and latch-up immunity by measuring the transmission line pulse (TLP) and transient latch-up (TLU). This article also conducted a detailed analysis on the optimization of electrical properties for the ESD design window of the proposed device according to the design variables and application of segment topology, and also analyzed the temperature reliability using a hot chuck control system. The measurement results reveal that the proposed device is highly suitable for the 12-V-class ESD design window, has improved reliability, and can provide excellent area efficiency in related applications.

Design of fabrication of ESD protection circuit with high holding voltage for power IC

ABSTRACTIn this paper, A newly Silicon Controlled Rectifier (SCR)-based Electric Static Discharge (ESD) protection circuit is proposed. The proposed circuit has the latch-up immunity in normal operating conditions with the high holding voltage by inserting the floating regions. To verify the electrical characteristics, a Technology Computer Aided Design (TCAD) simulation is performed by setting each of variables: D1, D2, D3, and D4. The results of the simulation show that the proposed protection circuit has the holding voltage 5 V higher than the conventional circuits and has the same level of robustness properties as the existing SCR. In addition, the proposed circuit is fabricated through a 0.18 μm Bipolar-CMOS-DMOS process. The electrical characteristics are confirmed by measuring Transmission Line Pulse, and the robustness properties are measured through Human Body Model (HBM) and Machine Model (MM). The holding voltage is about 20 V, which has the increases above 18 V or more compared to the conventional SCR. Therefore, the proposed circuit is proved to have the better ESD protection performance than HBM 8 kV and MM 800 V higher than HBM 2 kV and MM 200 V, the commercial standard.

An improved GGNMOS triggered SCR for high holding voltage ESD protection applications

Developing an electrostatic discharge (ESD) protection device with a better latch-up immunity has been a challenging issue for the nanometer complementary metal-oxide semiconductor (CMOS) technology. In this work, an improved grounded-gate N-channel metal-oxide semiconductor (GGNMOS) transistor triggered silicon-controlled rectifier (SCR) structure, named GGSCR, is proposed for high holding voltage ESD protection applications. The GGSCR demonstrates a double snapback behavior as a result of progressive trigger-on of the GGNMOS and SCR. The double snapback makes the holding voltage increase from 3.43 V to 6.25 V as compared with the conventional low-voltage SCR. The TCAD simulations are carried out to verify the modes of operation of the device.

SCR 기반 양방향성 ESD보호회로의 설계 변수 변화에 따른 전기적 특성의 관한 연구

본 논문에서는 높은 홀딩 전압을 갖는 SCR(silicon-controlled rectifier)기반 양 방향성 ESD 보호회로를 제안하였다. 일반적인 ESD 보호회로와 달리 양방향의 ESD Stress mode의 방전경로를 제공하며 높은 홀딩전압으로 latch-up면역 특성을 갖어 효과적인 ESD보호를 제공한다. 또한, 높은 홀딩전압을 위한 설계변수인 Gate Length와 N+bridge Length의 길이 변화에 따른 시뮬레이션을 Synopsys사의 TCAD 시뮬레이터를 사용하여 확인 하였다. 시뮬레이션 결과 2.1V에서 6.5V까지 홀딩 전압의 증가로 latch-up 면역 특성을 개선 하였으며, 기존 SCR보다 6.5V의 낮은 트리거 전압특성을 갖고 있어 제안된 ESD 보호 회로는 5V 이상의 공급전압을 갖는 application에 적용 가능하다. In this paper, we proposed a dual-directional SCR (silicon-controlled rectifier) based ESD (electrostatic discharge) protection circuit. In comparison with conventional SCR, this ESD protection circuit can provide an effective protection against ESD pulses in the two opposite directions, so the ESD protection circuit can be discharged in two opposite direction. The proposed circuit has a higher holding voltage characteristic than conventional SCR. These characteristic enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. it was analyzed to figure out electrical characteristics in term of individual design parameters. They are investigated by using the Synopsys TCAD simulator. In the simulation results, it has trigger voltage of 6.5V and holding voltage increased with different design parameters. The holding voltage of the proposed circuit changes from 2.1V to 6.3V and the proposed circuit has symmetrical I-V characteristic for positive and negative ESD pulse.

파워 클램프용 래치-업 면역 특성을 갖는 SCR 기반 ESD 보호회로

In this paper, SCR(Silicon Controlled Rectifier)-based ESD(Electrostatic Discharge) protection circuit for power clamp is proposed. In order to improve latch-up immunity caused by low holding voltage of the conventional SCR, it is modified by inserting n+ floating region and n-well, and extending p+ cathode region in the p-well. The resulting ESD capability of our proposed ESD protection circuit reveals a high latch-up immunity due to the high holding voltage. It is verified that electrical characteristics of proposed ESD protection circuit by Synopsys TCAD simulation tool. According to the simulation results, the holding voltage is increased from 4.61 V to 8.75 V while trigger voltage is increased form 27.3 V to 32.71 V, respectively. Compared with the conventional SCR, the proposed ESD protection circuit has the high holding voltage with the same triggering voltage characteristic.

An Improved Bidirectional SCR Structure for Low-Triggering ESD Protection Applications

An improved dual-polarity silicon-controlled rectifier (SCR) device has been proposed and realized in a 0.6-mum bipolar complementary metal-oxide-semiconductor process. The device can be used to protect electrostatic discharge (ESD) in both the positive and negative directions on pins with a voltage range that goes below ground. Comparing with the conventional bidirectional SCR structures, the new device is more suitable for low-voltage integrated circuit ESD protection applications because it possesses a smaller trigger voltage, a smaller leakage current, and a larger holding voltage.