Conventional Delta-sigma Modulator Research Articles

Complexity-Reduced Parallel Time-Interleaved Delta–Sigma Modulator for Transmitter Applications

High sampling frequency requirement in delta–sigma modulator (DSM) is one of the limiting factors toward its employment in high-frequency application, such as software-defined radio (SDR) transmitters. In this paper, a complexity-reduced parallel time-interleaved DSM is proposed to reduce the clock speed requirement of DSM transmitters. The complexity of the proposed parallel time-interleaved DSM is reduced by input delay blocks and input downsampler blocks in comparison to conventional time-interleaved DSMs. Simulation results show that the clock speed requirement of DSM transmitter is reduced four times by using the proposed four-branch complexity-reduced time-interleaved DSM, while signal quality is maintained.

Delta-sigma modulation microphone sensors employing a resonant tunneling diode with a suspended microstrip resonator

Purpose This paper aims to propose and demonstrate novel microphone sensors based on the frequency delta-sigma modulation (FDSM) technique, which replaces the conventional delta-sigma modulator in the delta-sigma analog-to digital converters. A key of the FDSM technology is to use a voltage-controlled oscillator (VCO) for converting an input analog signal to a 1-bit pulse-density modulated digital signal. High-performance sensors can be realized if the VCO is replaced by an oscillator whose oscillation frequency depends on an external physical parameter. Design/methodology/approach Microphone sensors are proposed based on FDSM that uses a suspended microstrip disk resonator, where the backside ground plane is replaced by a thin metal diaphragm. A resonant tunneling diode (RTD) oscillator is also used, as the performance of these sensors significantly depends on the oscillation frequency. To demonstrate the basic operation of the proposal, prototype devices were fabricated with an InGaAs/AlAs RTD. Findings A satisfactory noise shaping property, which is a significant nature of delta-sigma modulation, was demonstrated over three decades for the prototype device. A sound-sensing peak was also clearly observed when applying 1 kHz sound from a speaker. Practical implications High-performance ultrasonic microphone sensors can be realized if the sensors are fabricated by using a thin InP substrate with high-frequency oscillator design. Originality/value In this study, the authors proposed and experimentally demonstrated novel microphone sensors, which are promising as future ultrasonic sensors that have high dynamic range with wide bandwidth.

A re-configurable MASH 2-2 bandpass DQEFM for multi-standard applications

ABSTRACTThe design, analysis and implementation of a multi-stage noise shaping (MASH) bandpass modulator that employs a differentially quantized error feedback modulator (DQEFM) structure is described. The re-configurability, reduction of power-hungry active blocks and reduced sensitivity to circuit non-idealities makes this proposed bandpass modulator a suitable candidate for a digital intermediate frequency receiver system. The mathematical analysis and simulation results indicate the resemblance of the proposed modulator with the conventional sigma-delta modulator. The circuit level simulations indicate the better performance of the proposed modulator in terms of hardware complexity and power. The proposed cascaded modulator when implemented using 45nm CMOS process attains a signal-to-noise plus distortion ratio of 81.4 dB for a bandwidth of 200 kHz (GSM) and 61 dB for a bandwidth of 5 MHz (WCDMA). The circuit level simulation of the proposed bandpass architecture indicates a power consumption of 3.7 mW and 6.9 mW for GSM and WCDMA modes with 1V supply.

Designing and optimizing of a novel sigma-delta modulator using PSO algorithm

The performance of the conventional Sigma-Delta modulator can be improved by cascading electrical integrator behind the mechanical sensing element. In this paper, a novel Sigma-Delta modulator with a fractional-order PIλDμ controller is proposed and thus extending the traditional Sigma-Delta modulator to a new fractional-order in the Sigma-Delta ADC design field. The fractional-order PIλDμ controller allows fine tuning accuracy in seeking the coefficients for the proposed Sigma-Delta modulator and provides the robust stability in the placement of poles and zeros for compensating the phase delays. The parameters of the proposed fractional-order Sigma-Delta modulator is designed by using swarm intelligent algorithm, which offers opportunity to simplify the process of tuning parameters and further improve the noise performance. Simulation from the proposed fractional-order Sigma-Delta modulator, results of SNR > 134 dB and the noise floor under –170 dB are obtained in frequency range of [5-150 Hz].

Improving performance of mobile fronthaul architecture employing high order delta-sigma modulator with PAM-4 format.

An improved high-order delta-sigma modulator with multi-level quantizer is proposed to enable carrier aggregation of 4G-LTE signals in mobile fronthaul. Different from conventional delta-sigma modulation-based digital mobile fronthaul, a 2-bit quantizer is employed to reduce the quantization noise, which enabling the transmission via PAM-4 based IM-DD channel. Moreover, we employ the 4th-order high-pass filter (HPF) to replace the 1st-order HPF in the conventional delta-sigma modulator, resulting in a much better noise shaping performance. In the experiment, a PAM-4 based mobile fronthaul transmission of 32 aggregated 4G-LTE signals with a CPRI equivalent data rate of 39.32-Gb/s is demonstrated in a single-λ 10-Gb/s IM-DD channel. Significant improvement of 68% is achieved in the average EVM performance compared to the previous delta-sigma modulation-based digital mobile fronthaul.

A Single Opamp Third-Order Low-Distortion Delta-Sigma Modulator with SAR Quantizer Embedded Passive Adder

A third-order low-distortion delta-sigma modulator (DSM), whose third-order noise-shaping ability is achieved by just a single opamp, is proposed. Since only one amplifier is required in the whole circuit, the designed DSM is very power efficient. To realize the adder in front of quantizer without employing the huge-power opamp, a capacitive passive adder, which is the digital-to-analog converter (DAC) array of a successive-approximation-type quantizer, is used. In addition, the feedback path timing is extended from a nonoverlapping interval for the conventional low-distortion structure to half of the clock period, so that the strict operation timing issue with regard to quantization and the dynamic element matching (DEM) logic operation can be solved. In the proposed DSM structure, the features of the unity-gain signal transfer function (STF) and finite-impulse-response (FIR) noise transfer function (NTF) are still preserved, and thus advantages such as a relaxed opamp slew rate and reduced output swing are also maintained, as with the conventional low-distortion DSM. Moreover, the memory effect in the proposed DSM is analyzed when employing the opamp sharing for integrators. The proposed third-order DSM with a 4-bit SAR ADC as the quantizer is implemented in a 90-nm CMOS process. The post-layout simulations show a 79.8-dB signal-to-noise and distortion ratio (SNDR) in the 1.875-MHz signal bandwidth (OSR=16). The active area of the circuit is 0.35 mm2 and total power consumption is 2.85 mW, resulting in a figure of merit (FOM) of 95 fJ/conversion-step. key words: delta-sigma modulator, DSM, opamp sharing, relaxed dynamic element matching (DEM) timing

New Delta Sigma Modulator Structure Using Second Order Filter in One Stage Technique

In this paper, a new structure of delta sigma modulator has been proposed in which a second order filter in one stage technique has been taken into the account and a second order noise shaping method and a third order one have been designed by the proposed idea. In the proposed structure an OPAMP has been saved and since in a conventional delta sigma modulator OPAMPs consumes most of the power and takes very large area, the proposed idea causes less power consumption and also the chip area is minimized.

An Input-Feedforward Multibit Adder-Less $\Delta{-}\Sigma$ Modulator for Ultrasound Imaging Systems

This paper describes a high-speed delta-sigma modulator with 65-nm CMOS technology for ultrasound imaging systems. The delta-sigma modulator is based on a 4th-order single-loop switched-capacitor architecture with a 4-bit quantizer. The designed modulator has the advantages associated with input-feedforward architecture, such as the reduced output swing of the integrator, which relaxes the amplifiers' design requirements. Due to the power and area overheads and the timing constraint of the active adder in the conventional multibit input-feedforward modulator, we use an adder-less input-feedforward delta-sigma architecture. As a result, the designed architecture eliminates the extra power consumption and silicon area required by the adder. The designed architecture also relaxes the timing requirement for the quantizer and the dynamic element-matching block compared with the conventional delta-sigma modulator. The modulator achieves a dynamic range of 76dB and a peak signal-to-noise-plus-distortion ratio of 72.3 dB in a signal bandwidth of 6 MHz. The power consumption is 18.5 mW with 1.2-V supply voltage, and the chip core size is 0.25 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The energy required per conversion step is 0.46 pJ/conv.

A wideband high-resolution time-interleaved sigma-delta modulator with VCO-based quantizer

A time-interleaved sigma-delta modulator with VCO-based quantizer for next generation wireless applications is presented. This proposed modulator firstly introduces the VCO-based multibit quantizer into the time-interleaved sigma-delta modulator, which can achieve the improvement of the signal bandwidth and signal-to-noise ratio simultaneously. Moreover, these performance metrics have no adverse effects on power consumption, which is more suitable for wireless applications. A two-channel proposed modulator is taken as an example, and the simulation results show that the proposed modulator achieves a signal-to-noise ratio of 112.1dB over a 4.7MHz signal bandwidth with a clock frequency of 300MHz, which improves 100% in the range of signal bandwidth and 21dB in the signal-to-noise ratio compared to the conventional sigma-delta modulator with the same clock frequency and power consumption.

Vector quantized signal dependant Delta-Sigma modulator based high performance three-phase switching converter

The conventional second-order Delta-Sigma modulator (DSM) based switching converter (SC) cannot be used for full range (-1 to +1) of input signal. The DSM becomes unstable when the normalized input signal is about 0.4. The output of the second integrator saturates the operational amplifier which is used as comparator in the single-bit quantizer. The three- phase switching converter, based on DSM with hexagonal quantizer, improves the signal to noise ratio as well as the spectral response without improving the range of the input signal. This paper proposes three-phase signal dependant DSM based switching converter with vector quantizer. The proposed three-phase SC increases the input signal to full scale and maintains its stability. The SNR and spectral response are better than the conventional DSM based three-phase switching converter with hexagonal quantizer. The overall maximum percentage of difference in phase voltages is 0.4%.

2비트 시그마-델타 변조를 이용한 새로운 폴라 트랜스미터

본 논문에서는 2비트 시그마-델타 변조기를 도입한 새로운 구조의 폴라 트랜스미터에 대해 논의한다. 제안된 구조에서는 2비트 시그마-델타 변조 방식을 도입하여 양자화 잡음을 낮추도록 하였다. 전력 증폭기는 2비트 디지털 처리된 진폭 신호를 받아들이기 위하여 2진법의 형태로 분할되도록 고안되었다. 새로운 구조의 폴라 트랜스미터를 EDGE 시스템에 적용하여 시뮬레이션 한 결과, 전체 전송 대역에서 스펙트럼 특성이 개선되는 것을 확인할 수 있었다. 2비트 변조기에 세밀한 양자화 방식을 적용함으로써 오버 샘플링 비가 2배 이상 증가한 정도의 잡음 감소 특성을 얻을 수 있었고 오버 샘플링 비를 증가시키지 않고도, 트랜스미터 출력 신호의 주파수 잡음을 10dB 이상 낮출 수 있었다. 또한, 전력 증폭기를 2진법으로 분할한 결과 다이나믹 영역이 5dB 정도까지 증가하는 효과를 얻었다. This paper presents a novel polar transmitter architecture with a 2-bit sigma-delta modulator. In the proposed architecture, the 2-bit sigma-delta modulator is introduced to suppress quantization noise of conventional sigma-delta modulator. The power amplifier configuration is also modified in a binary form to accommodate the 2-bit digitized envelope signal. The Ptolemy simulation results of the proposed structure show that the spectral property is greatly improved in full transmit band of EDGE system. The fine quantization scheme of the 2-bit modulator lowers the noise level by 10dB without increasing the over-sampling ratio, which may be obtained if the over-sampling ratio increases twofold. Dynamic range is also enhanced up to 5dB owing to the new form of the power amplifier in the transmitter.

Managing Subthreshold Leakage in Charge-Based Analog Circuits With Low-&amp;lt;tex&amp;gt;$V_rm TH$&amp;lt;/tex&amp;gt;Transistors by Analog T- Switch (AT-Switch) and Super Cut-off CMOS (SCCMOS)

The analog T-switch (AT-switch) scheme is introduced to suppress subthreshold-leakage problems in charge-based analog circuits such as switched capacitors and sample-and-hold circuits. A 0.5-V sigma-delta modulator is manufactured in a 0.15-/spl mu/m FD-SOI process with low V/sub TH/ of 0.1 V using the concept. The scheme is compared with another leakage-suppression scheme based on super cut-off CMOS (SCCMOS) and the conventional circuit which are also fabricated. The sigma-delta modulator based on AT-switch greatly improves 8.1-dB SNDR through reducing nonlinear leakage effects while the modulator based on SCCMOS improves the dynamic range rather than the SNDR by comparing with the conventional sigma-delta modulator.

An enhanced first-order sigma-delta modulator with a controllable signal-to-noise ratio

This paper presents an enhanced first-order sigma-delta modulator. The proposed modulator, derived using the Al-Alaoui operator, outperforms the conventional modulator. A comparison is drawn showing that the conventional sigma-delta modulator is a special case of the enhanced sigma-delta modulator. The paper includes an analytical derivation as well as extensive simulations revealing the superiority of the proposed modulator reaching optimal performance

Dual-clock MASH delta-sigma modulator employing a frequency modulated intermediate signal

A dual-clock MASH (multi-stage noise shaping) delta-sigma modulator (DSM) is proposed for high performance analog-digital converter. This employs a DSM using a frequency modulated intermediate signal (FMDSM) for the last stage. The sampling clock frequency for the last stage can be increased due to the features of the FMDSM. It is shown that this can increase the SNR beyond the conventional MASH DSMs.

Efficient dithering of sigma-delta modulators with adaptive bit flipping

A new technique is presented for dithering single bit sigma-delta modulator (SDM) A/D and D/A converters in the digital domain. The system operates by detecting and randomising the limit cycle oscillations responsible for baseband tones. The system is efficient to implement in hardware and does not surfer from the analogue dither that is required in conventional SDM A/D converters. >

Exploiting chaos to suppress spurious tones in general double-loop Sigma Delta modulators

Conventional Sigma Delta modulators are operated exclusively in the nonchaotic regime in which the internal integrators are stable. Theoretical interest in chaotic Sigma Delta modulators recently arose, mainly because the circuits are simple and strongly nonlinear systems with rich behavior, not unlike Chua's circuit. It has since been recognized that the application of conventional Sigma Delta modulators to A/D and D/A conversion may be haunted by spurious tones in the output, and it has been proposed to use chaotic modulators to overcome that problem. This paper employs a semi-analytical technique to solve the design problem for general chaotic double-loop modulators with constant inputs. Using the results, optimized scaling factors are easily found for given integrator pole locations, such that an approximate performance measure is maximized subject to bounds on internal state variables. The clarification of this explicit tradeoff between tone rejection through chaos, system stability, and practical performance may help to overcome some understandable scepticism in the community of Sigma Delta designers. >