Conventional Si Substrate Research Articles

THz Metamaterial Sensitivity Enhancement by Reduction of Substrate's Fabry-Pérot Oscillations Using Back Plates as an Optical De-Coupler.

This work presents a new method for the enhancement of sensitivity in Terahertz (THz) spectroscopy on metamaterial (MM) in terms of its resonance frequency shift (ΔF), by attaching the dielectric back plate to the MM's silicon (Si) wafer. The dielectric back plates are designed to minimize the Fresnel reflections at the backside of the substrate, identical to a broadband antireflective (AR) plate tailored for THz. Utilizing broadband AR technology, we demonstrate the concept of decoupling MM resonance from the substrate's Fabry-Pérot (FP) oscillations. This is done by effectively coupling the THz light out of the high-permittivity substrate, resulting in the improved quality factor of the MM resonance and overall plasmonic enhancement on the metasurface. The back plate acts as a surface plasmonic enhancer to the THz MM by increasing the field intensity on the front metasurface, leading to enhancement of dielectric response (MM's ΔF). This makes the MM resonance ultrasensitive to the minor changes of particle size/concentration under test spread on the metasurface, contributing to enhanced resonance ΔF. The plate also makes the Si substrate optically lossless, enabling the full effect of MM resonance shift and increasing the resonance ΔF by 8-fold compared with MM's fabricated on conventional Si substrates. This research is backed-up with system-level CST simulations and experimental THz impedance spectroscopy of the MM. This method and chip structure is CMOS compatible having potential applications for any resonant MM fabricated on a substrate aimed to maximize dielectric sensitivity for biosensing and nanoparticle THz spectroscopy.

Effect of linear antenna chemical vapor deposition process parameters on the growth of nanocrystalline diamond-on-GaN films

The present work will systematically study the effect of different linear antenna microwave plasma enhanced chemical vapor deposition (LACVD) processing parameters on the optimal deposition of the diamond films. The low pressure and low temperatures of LACVD growth conditions is expected to deposit diamond films on otherwise reactive gallium nitride (GaN) surfaces, without any intermediate nitride buffer layer. First, the distances between the quartz tube and the samples put on the stage are varied (3–15 cm), which has a direct impact on the substrate temperature (415°–300 °C). Thereafter, the microwave input power was also altered (1.5–2.8 kW) to attain low substrate temperatures. It was found that 300 °C is the temperature limit, which can be attained by heating only with microwave plasma when the substrates are kept farthest (15 cm) away from the liner antenna quartz tube. An additional heater was used under the stage for rapidly achieving such minimum substrate temperature of 300 °C. Substrate heater was used for efficient growth of the diamond phase while using pulse mode frequency of microwave power input for optimization of the diamond films. The microstructure (plate-like and cauliflower-like) of the deposited nanocrystalline diamond (NCD) films and the cross-sectional images for thickness measurements was observed under the scanning electron microscope and the elemental analysis of the film surfaces was done by electron diffraction spectroscopy. Moreover, the diamond film quality and crystallinity were evaluated by Raman spectroscopy with 488 nm laser light. Diamond-on-GaN film results were compared with conventional Si substrate. Different LACVD reactor parameters like, antenna to stage distances, microwave input power in continuous wave mode, and growth temperatures have significant impacts on the grown films, both in terms of their quality and microstructure. It was found that the optimum deposition of nanocrystalline diamond film on GaN substrates without its surface etching was possible, under pulse mode (20 kHz, 45 % duty cycle) with 2 kW average input microwave power.

Electrical Characteristics of Single Layer Graphene Ribbons in a Wide Temperature Range

This paper provides electrical characterization of single layer graphene ribbon devices defined as back-gated graphene transistors. The two-terminal back-gated graphene ribbon devices were fabricated on a conventional Si substrate covered by a 90 nm-thick thermal SiO2. The chemical vapor deposition process was used for the graphene layer deposition and its quality was checked with optical microscopy, scanning electron microscopy and Raman spectroscopy. For the device fabrication, optical lithography was used for electrode patterns through a mask, and Ti/Au (10 nm/100 nm) metallic contacts were deposited by thermal evaporation. We report low and high field electrical measurements of several devices, under a controlled environment over a wide temperature range, from 77 to 300 K. At 77 K, the drain current decreases, i.e. the resistance of the graphene increases, and the nonlinearity is still present. The maximum influence of the temperature is reached at the charges neutrality point, and we observe that the temperature could influence the position of the charge neutrality point. This indicates that the carriers are thermally activated, which yields a least pronounced current with the increase of the back gate voltage.

An adjustable Ar ion-beam activation strategy to achieve hydrophilic bonding of Si and diamond by deposited AlN interlayer

As a III-nitride, AlN exhibits high thermal conductivity, excellent insulation, and low thermal expansion. Therefore, AlN is an alternative to the insulating layer in conventional Si-on-insulator (SOI) systems to solve the problem of severe self-heating effects caused by the poor thermal conductivity of buried oxide (BOX, SiO2) layers. This is particularly true for high-power integrated circuit and micro-electro-mechanical system fabrication. However, heat transfer also depends on the bottom Si substrate. With the highest thermal conductivity (≥2000 W/mK) among bulk materials, diamond is a highly attractive option to replace conventional Si substrates. Herein, we describe a low-temperature vacuum-free hydrophilic bonding method based on a thin AlN interlayer to prepare a single-crystal Si layer on a polycrystalline diamond. Through suitable Ar ion-beam activation, the surface nanomorphology and chemical state can be simultaneously modified. Increasing the real contact area and removing the surface heavy oxygen layer are critical factors for achieving complete bonding. Moreover, the relatively mild deposition and bonding conditions of AlN make it compatible with the complex CMOS transistor process and could enable the more flexible integration of diamond into 3D chip packages in the future.

Quantitative protein sensing with germanium THz-antennas manufactured using CMOS processes.

The development of a CMOS manufactured THz sensing platform could enable the integration of state-of-the-art sensing principles with the mixed signal electronics ecosystem in small footprint, low-cost devices. To this aim, in this work we demonstrate a label-free protein sensing platform using highly doped germanium plasmonic antennas realized on Si and SOI substrates and operating in the THz range of the electromagnetic spectrum. The antenna response to different concentrations of BSA shows in both cases a linear response with saturation above 20 mg/mL. Ge antennas on SOI substrates feature a two-fold sensitivity as compared to conventional Si substrates, reaching a value of 6 GHz/(mg/mL), which is four-fold what reported using metal-based metamaterials. We believe that this result could pave the way to a low-cost lab-on-a-chip biosensing platform.

(Invited) Electrodeposition of Si in CsF–CsCl Eutectic Melt

1.Introduction In recent years, the demand for solar cells as a clean energy source has been increasing. Among the various types of solar cells, crystalline Si solar cells dominate the solar cell market due to their high efficiency, excellent stability, and abundant natural resources. However, the major disadvantages of the conventional Si substrate manufacturing method are the low productivity of the Siemens process and the considerable kerf loss in the Si slicing process. As the demand for crystalline Si solar cells continues to grow, there is a strong need to develop alternative manufacturing methods for Si substrates. As a promising method, the direct formation of Si films on inexpensive substrates has been investigated [1]. We have proposed the electrodeposition of Si films from molten KF–KCl which has relatively high fluoride-ion concentration at eutectic composition (KF:KCl = 45:55 mol%, m.p.: 878 K) and high solubility in water [2]. We have already studied the optimum conditions for obtaining adherent, compact, and smooth Si films in molten KF–KCl–K2SiF6 at 923 K [3]. Furthermore, good Si films was obtained from KF–KCl after bubbling SiCl4 as a Si-ion source [4]. In this study, we focused on CsF–CsCl eutectic melt (CsF:CsCl = 50:50 mol%, m.p.: 713 K [5]) as a new electrolyte for Si electrodeposition. Molten CsF–CsCl has lower operable temperature and higher fluoride-ion concentration than molten KF–KCl at the eutectic composition. Moreover, CsF and CsCl have extremely high solubility in water (CsF; 573, CsCl; 191 g per 100 g H2O at 293 K [6]), indicating that the solidified salts can be easily removed. In this study, Si was electrodeposited on Ag plate substrates at 923 K at various Si-ion concentrations and cathodic current densities. The obtained Si films were analyzed by XRD and SEM/EDX to determine the optimum electrodeposition conditions.2. Experimental The experiments were conducted in CsF–CsCl eutectic melt in an Ar glovebox. The experimental temperature was 923 K and Cs2SiF6was used as the Si ions source. Ag plate and Ag flag electrodes were used as the working electrodes. The counter and reference electrodes were Si rods. The potential of the reference electrode was calibrated by Cl2/Cl− potential measured at a glass-like carbon electrode. Samples prepared by galvanostatic electrolysis of Ag plates substrates were analyzed by SEM/EDX after washing with distilled water to remove adhered salts.3. Results and Discussion The electrodeposition was carried out by changing the added amounts of Cs2SiF6 from 0.50 to 3.5 mol%. The cathodic current density was also varied in the range of 25–800 mA cm−2. As typical deposits, Fig. 1 shows SEM images of Si prepared at (a) 600, (b) 100, and (c) 50 mA cm−2 in CsF–CsCl–Cs2SiF6 (2.0 mol%). At a higher current density, Si was nodule-shaped because the concentration gradient of Si(IV) ions increased near the electrode, and Si deposition proceeded preferentially on the convex part close to the bulk molten salt. At medium current densities (e.g., 100 mA cm−2), the electrodeposited Si was film-like and the surface was smooth. Fig. 2 shows a cross-sectional SEM image of the film, indicating the smooth and compact deposit. The thickness is about 20 μm (the theoretical film thickness: 25 μm), indicating a relatively high current efficiency. Furthermore, it was found that the upper current limit to obtain Si with smooth surface is higher at the higher Cs2SiF6 concentration; Si films with smooth surface were obtained even at 600 mA cm−2 in CsF–CsCl–Cs2SiF6 (3.5 mol%). At low current density, Si was film-like, but many humps were observed due to insufficient overvoltage and difficulty in nucleation.AcknowledgementThe present address of Kouji Yasuda is Graduate School of Engineering, Kyoto Univ.

Epitaxial Ge-on-Nothing Virtual Substrates for 3D Device Stacking Technologies

Future monolithic heterogeneous integration of Ge and IIIV materials in electronic, optoelectronic and photonic devices requires advanced layer transfer and 3D device stacking technologies, which starts with the fabrication of suitable (virtual) substrates. A layer transfer process based on the reorganization of macro-porous Si at high temperature was developed by imec [1]. The developed fabrication scheme to fabricate macropores is based on standard UV lithography and dry etching techniques rather than electrochemical etching. This enables an easy transfer to full Si wafers (up to 300 mm). During a high-temperature step, the top part of the macro-porous Si reflows. By using proper anneal conditions, the layer detaches from the mother substrate, being anchored by a few attachment points only, forming a ‘Si on nothing’ (SoN) stack (Fig. 1a). The suspended Si layer can then easily be transferred to another substrate.In this contribution, we assess the suitability of macro-porous Si and SoN as starting material for Ge virtual substrates. The goal is to provide a fabrication scheme that allows an easy detachment of the virtual substrate after wafer to wafer bonding. Macro-porous Si was only fabricated in the inner 10x10 cm2 area of 200 mm wafers using imec’s qualified fabrication scheme. Ge layers were simultaneously grown on the inner macro-porous Si (or SoN) and the outer bulk Si. This allows to compare the material properties without the risk of wafer to wafer variations due to non-reproducibility issues. Our approach for making macro-porous Si and SoN provides mono-crystalline, nearly defect-free, and extremely smooth Si starting surfaces. A standard low temperature epitaxial Ge growth process in an ASM-Epsilon® 2000 system was used to deposit the Ge layers [2].As an example, Fig. 1b shows a 1.25 mm thick mono-crystalline epitaxial Ge layer grown on a macro-porous Si layer. The Ge growth proceeds in a 2-dimensional mono-crystalline growth mode. The surface morphology of the grown Ge is not affected by the starting surface (Fig. 1c,d). The Full Width at Half Maximum (FWHM) as extracted from w-2q High Resolution X-ray Diffraction scans acquired around the Ge (004) Bragg peak is strongly reduced after a post Ge deposition anneal, which was also reported for Ge on bulk Si [2]. Threading dislocations annihilate during the post-epi anneal. FWHM values as low as 160 arc sec have been measured for 1.25 mm thick Ge layers independent of the underlying layer. This reflects the high material quality of the grown Ge. The difference in thermal expansion coefficient between Si and Ge results in some tensile stress in the annealed Ge layer, which explains the well-known shift in XRD peak position. The improvement in material quality by using a post-epi anneal is also reflected in the carrier lifetime as extracted from room-temperature photoluminescence measurements. The carrier lifetime increases from <0.2 ns (as-grown layers) to 3.3 ns and 3.6 ns for Ge on porous Si and bulk Si, respectively. The TDD, as extracted from ECCI measurements, was identical for both parts of the Si wafer (2-4e7 cm-2) and close to the values expected from literature. The material properties listed above are not affected by the thickness of the closed Si layer in-between the Ge and the porous Si.In conclusion, we developed a fabrication scheme for strain-relaxed Ge grown on SoN (or on macroporous Si) starting from conventional Si substrates. The material properties of the virtual Ge substrate are identical to those obtained for Ge grown on bulk Si. The virtual substrate serves as starting material for layer transfer and 3D device stacking technologies. The fabrication scheme can be extended to (defect free) bulk Ge for which the fabrication of Ge on nothing followed by layer transfer has been demonstrated [3].

Effect of Hydrogen-Ion-Implantation on Self-Separation of Free-Standing Gallium Nitride Wafers Grown By Hvpe

In recent years, free-standing Gallium Nitride (FS-GaN) wafers were utilized as substrates for high-brightness light-emitting-diodes (HB-LED), LASER diodes (LD) and power devices due to their characteristics, such as 3 times higher thermal conductivity than sapphire substrates and higher breakdown voltage than conventional Si substrates. The FS-GaN wafers grown by hydride vapor phase epitaxy (HVPE) demonstrated lower dislocation density (DD) than that of GaN wafers grown by metal-organic chemical vapor deposition (MOCVD) on sapphire substrates (template GaN wafer). However, one of big challenges for their commercializing is the crack free FS-GaN wafers during the HVPE GaN growth, which resulted in lowering the productivity and increasing the fabrication cost. The main cause of the cracking is the stress induced by the differences in thermal expansion coefficients (TEC) and lattice constants of sapphire and GaN. To overcome this issue, the design of GaN growth process with self-separation is the key technology. The self-separation technique consists of two key points, one is separation enhancement and the other is blocking edge-poly-GaN growth. In this study, we investigated the effect of hydrogen-ion-implantation on self-separation of FS-GaN wafers. In addition, the blocking effect of edge grinding of template GaN wafers was also investigated. Two-inch-diameter template GaN wafers with the GaN layer thickness of 5 μm were prepared and the hydrogen-ions were implanted with various dose conditions to enhance self-separation of FS-GaN wafers from the sapphires. The edges of the implanted template GaN wafers were then ground to eliminate the polished edge surfaces to deter the poly-GaN growth. 800-μm-thick GaN layers were grown by HVPE on the template GaN wafers, and the FS-GaN wafers were successfully self-separated during the cool-down process. Fig. 1 shows the edge images of the GaN on sapphire substrates after 300-μm-thick GaN layer was grown on the template GaN substrates. When the edge-grinding was utilized to template GaN substrate, the poly-GaN was grown less than that of the substrate without edge-grinding. Also, the poly-GaN was easily removed at the edge of the substrate by edge-grinding without additional process. Fig. 2 shows the hydrogen-ion-band inside the MOCVD-GaN layer with three different hydrogen-ion dose conditions. The sample with hydrogen-ion dose of 2.25 E17 H+/cm2 showed larger size of the hydrogen cavity than the samples with hydrogen-ion dose of 1.75 E17 and 2.0 E17 H+/cm2. Fig. 3 shows the wafer images after 800-μm-thick GaN grown on the edge-ground template GaN with three different hydrogen-ion-implantation conditions. The FS-GaN wafers with hydrogen-ion dose of 1.75 E17 and 2.0 E17 H+/cm2 were successfully self-separated from the sapphire substrates, while the sample with hydrogen-ion-dose of 2.25 E17 H+/cm2 was self-separated around 63% of the area. In our presentation, we will report how we achieved the self-separation of FS-GaN wafers without cracking by hydrogen-ion-implantation into the template GaN substrates, and discuss about the crystal quality of the grown FS-GaN samples. * This work was financially supported by the Brain Korea 21 Plus Program in 2018. Figure 1

Piezoelectric control of magnetoelectric coupling driven non-volatile memory switching and self cooling effects in FE/FSMA multiferroic heterostructures

The manipulation of magnetic states and materials' spin degree-of-freedom via a control of an electric (E-) field has been recently pursued to develop magnetoelectric (ME) coupling-driven electronic data storage devices with high read/write endurance, fast dynamic response, and low energy dissipation. One major hurdle for this approach is to develop reliable materials which should be compatible with prevailing silicon (Si)-based complementary metal–oxide–semiconductor (CMOS) technology, simultaneously allowing small voltage for the tuning of magnetization switching. In this regard, multiferroic heterostructures where ferromagnetic (FM) and ferroelectric (FE) layers are alternatively grown on conventional Si substrates are promising as the piezoelectric control of magnetization switching is anticipated to be possible by an E-field. In this work, we study the ferromagnetic shape memory alloys based PbZr0.52Ti0.48O3/Ni50Mn35In15 (PZT/Ni-Mn-In) multiferroic heterostructures, and investigate their potential for CMOS compatible non-volatile magnetic data storage applications. We demonstrate the voltage-impulse controlled nonvolatile, reversible, and bistable magnetization switching at room temperature in Si-integrated PZT/Ni-Mn-In thin film multiferroic heterostructures. We also thoroughly unveil the various intriguing features in these materials, such as E-field tuned ME coupling and magnetocaloric effect, shape memory induced ferroelectric modulation, improved fatigue endurance as well as Refrigeration Capacity (RC). This comprehensive study suggests that these novel materials have a great potential for the development of unconventional nanoscale memory and refrigeration devices with self-cooling effect and enhanced refrigeration efficiency, thus providing a new venue for their applications.

Hole mobility in strained Si/SiGe/vicinal Si(110) grown by gas source MBE

Strained Si/SiGe heterostructures were grown on vicinal Si(110) substrates by using gas-source MBE, and relationship between structural aspects and effective hole mobility was investigated. The surface inclination was found to be effective in obtaining smoother surface. By growing the film at different substrate temperatures, samples which were significantly different in surface morphology and crystalline defects were obtained. Under a certain condition, the strain in the SiGe layer was found to be relaxed mainly by microtwin formation. It was found that this strain relaxation pathway was favorable for pMOSFETs with [1̅10] channel. As a result, the effective hole mobility as high as 350cm2/Vs was achieved on conventional Si substrate.

CAFM Experimental Considerations and Measurement Methodology for In-Line Monitoring and Quantitative Analysis of III–V Materials Defects

To continue technology scaling, a new generation of high-performance devices are considered to be implemented using III–V semiconductors, which need to be grown over the conventional Si substrate. However, due to the lattice mismatch between the III–V and silicon materials, the former tend to develop significant density of structural defects [specifically, threading dislocations (TDs)], which can adversely affect device electrical characteristics. Conductive atomic force microscope (CAFM) technique is among the most promising tools for the identification and analysis of TDs in a nanoscale range although obtaining reliable quantitative data requires precise controls over the measurements conditions. In this study, CAFM technique has been applied for TDs detection and analysis in III–V films, and tool requirements and measurement methodology are discussed.

Impact of three-dimensional stacking silicon on diamond substrate for the electrostatic discharge protection device

In this paper, the electrostatic-discharge (ESD) protection capabilities of the protection devices fabricated on a silicon-on-diamond (SOD) structure and a conventional Si substrate are compared. The results showed that the ESD protection capability of the SOD substrate is higher than that of the silicon-on-insulator (SOI) substrate. We also evaluate the ESD protection device suitable for the SOD structure. In addition, we propose the three-dimensional (3D) stacking structure suitable for a power supply on a chip (power-SoC) and the best location for the implementation of the ESD protection device based on the results of device simulations.

Using aluminum-induced polycrystalline silicon to enhance ultraviolet to visible rejection ratio of ZnO/Si heterojunction photodetectors

Zinc oxide (ZnO) was deposited on aluminum-induced polycrystalline silicon (AIC-pc-Si) thin film, instead of on a conventional bulk silicon (Si) substrate, and n-ZnO/p-AIC-pc-Si heterojunction photodetectors (HPDs) were fabricated. It is found that the usage of AIC-pc-Si film can largely reduce the visible response by nearly 3 orders of magnitude compared to the conventional Si substrate, making the HPDs practical for real ultraviolet (UV) detection. The drastically reduced visible response achieves a much higher UV (340nm)/visible (500nm) rejection ratio of 2.1×103 than that (7.82) in conventional ZnO/p-Si substrate HPDs. Two major contributions are responsible for the drastic reduction in visible response. One is the very thin (300nm) AIC-pc-Si film, which is much thinner than the bulk Si substrate (about 600μm); the very thin AIC-pc-Si film absorbs very few visible photons and hence lowers visible response. Another issue is the addition of Al atom. During the deposition of ZnO, Al atoms diffuse from the AIC-pc-Si film and build up a bump between the ZnO and AIC-pc-Si. The addition of Al in ZnO increases the electron concentration of ZnO, creating a new structure of n-ZnO/n+-ZnO/AIC-pc-Si. The corresponding band diagram shows a hollow region exists in the n+-ZnO, where the visible-light-generating electrons are recombined by the defect states at n-ZnO/AIC-pc-Si interface, largely suppressing the visible response.

AlN-AlN Wafer Bonding and Its Thermal Characteristics

Introduction Wafer bonding allows heterogeneous integration of two materials with similar or very different lattice parameters and thermal properties, via an intermediate bonding layer or direct contact. One of its most prominent applications is silicon-on-insulator (SOI) [1], and it can also be extended to germanium-on-insulator (GOI) or other III-V materials integration. SOI fabricated from wafer bonding is gaining ground from the conventional Si substrate in ultra-large scale integrations (ULSI) and micro-electro-mechanical systems (MEMS) as the starting substrate [2], which benefits from its on-insulator structure. The “on-insulator” advantages make it possible to attain mechanical stability close to Si substrate and excellent electrostatic control. However, the advantages of SOI are degraded due to the presence of a conventional SiO2 insulator layer with thermal conductivity of ~1.4 Wm-1K-1. The squeezed heat dissipation path deteriorates its heat transfer efficiency to the underlying bulk Si layer, leading to severe self-heating effect. The self-heating effect is magnified by device scaling, which limits the applicability of SOI in electronics especially in the cases where high temperature and power dissipation are expected. In order to address this problem, Al2O3-Al2O3 bonding had been demonstrated and appeared to have favorable thermal characteristics [3]. In this paper, a more promising intermediate bonding layer is introduced. It shows the possibility of fabricating bonded wafer with enhanced thermal conductivity through room temperature AlN-AlN fusion bonding. Its strong heat dissipation capability is verified by COMSOL simulation and experimental results obtained from resistance thermal detector (RTD). Experiment, Results and Discussion Si wafers used for bonding were pre-cleaned by the standard RCA cleaning method. Then, a 10 nm AlN thin film was sputtered onto the pre-cleaned Si surface. While for comparative study, a 10 nm of SiO2 and Al2O3 was deposited via PECVD and ALD system, respectively. After deposition, a surface activation step was provided under N2 plasma to enhance the surface hydrophilicity. The activated wafers were cleaned by de-ionized (DI) water rinse and dried with spin dryer. AlN-AlN bonding was initiated at room temperature, and the bond was strengthened by annealing at 300 °C in N2 ambient for a duration of 3 hrs. Next, Si on one side of the bonded structure was removed by grinding and wet etching. Au line Kelvin structures for thermal characteristics verification were patterned and formed. The IR imaging results have shown that AlN thin film exhibits very good bondability when two of them are bonded face-to-face. The good bondability can be attributed to the low surface roughness, which was as low as 0.16 nm in a 5 μm × 5μm AFM scan area. Only very few unbonded areas were observed due to the presence of particles, which were trapped during wafer handling and can be eliminated with careful control of contamination sources. After annealing, no obvious bubble enlargement was found, which indicates that out-gassing is not significant. This led to a respectable AlN-AlN bonded interface with bond strength of ~1359.9 mJ/m2 which is sufficient for subsequent process steps. According to the COMSOL simulation results, AlN has shown great advantage as the insulator layer in term of heat dissipation capability as compared with conventional insulator materials SiO2 and the recently widely studied Al2O3. Their heat dissipation capability was investigated and compared by studying the temperature profile across bonded structure when the material stack was subjected to a heat flux of 1 × 108 W/m2. The simulated surface temperature of 20 nm (Si, SiO2, Al2O3, AlN) on Si structures are 32.403, 33.818, 32.446, and 32.402 °C respectively. 20 nm AlN on Si appeared to have the similar temperature profile as direct Si-Si bonded wafer, because they have close thermal conductivity values (AlN: 134 Wm-1K-1 [4] and Si: 131 Wm-1K-1). Thus, it can be shown that the presence of AlN thin film does not degrade the thermal property or hinder heat from spreading to the underlying Si substrate. Conclusion In conclusion, a successful void-free AlN-AlN wafer bonding was demonstrated. The bonded AlN-AlN layer showed superior heat dissipation capability, which is identical to that of Si-Si direct bonding. Reference [1] U. Gösele et al., Annu. Rev. Mater. Sci., 28, p. 215-241, 1998.[2] R. L. Puurunen et al., in TRANSDUCERS 2011,pp. 978-981. 2011.[3] J. Fan et al., ECS J. Solid State Sci. and Technol.,2, p. 169-174, 2013.[4] M.-H. Park et al., Mater. Sci. Semicond. Process., 15, p. 6-10, 2012.

Monolithic Composite “Pressure + Acceleration + Temperature + Infrared” Sensor Using a Versatile Single-Sided “SiN/Poly-Si/Al” Process-Module

We report a newly developed design/fabrication module with low-cost single-sided “low-stress-silicon-nitride (LS-SiN)/polysilicon (poly-Si)/Al” process for monolithic integration of composite sensors for sensing-network-node applications. A front-side surface-/bulk-micromachining process on a conventional Si-substrate is developed, featuring a multifunctional SiN/poly-Si/Al layer design for diverse sensing functions. The first “pressure + acceleration + temperature + infrared” (PATIR) composite sensor with the chip size of 2.5 mm × 2.5 mm is demonstrated. Systematic theoretical design and analysis methods are developed. The diverse sensing components include a piezoresistive absolute-pressure sensor (up to 700 kPa, with a sensitivity of 49 mV/MPa under 3.3 V supplied voltage), a piezoresistive accelerometer (±10 g, with a sensitivity of 66 μV/g under 3.3 V and a −3 dB bandwidth of 780 Hz), a thermoelectric infrared detector (with a responsivity of 45 V/W and detectivity of 3.6 × 107 cm·Hz1/2/W) and a thermistor (−25–120 °C). This design/fabrication module concept enables a low-cost monolithically-integrated “multifunctional-library” technique. It can be utilized as a customizable tool for versatile application-specific requirements, which is very useful for small-size, low-cost, large-scale sensing-network node developments.

Fabrication and characterization of Ag film with sub-nanometer surface roughness as a flexible cathode for inverted top-emitting organic light-emitting devices

An ultra-smooth Ag film with sub-nanometer surface roughness on a flexible substrate has been fabricated by a template-stripping process and its effect on the carrier injection and transport in organic light-emitting devices (OLEDs) has been investigated. The use of the ultra-smooth Ag film as an electrode results in both enhanced carried injection due to the improved contact between the electrode and the organic layer and enhanced carrier transport due to the larger grain size of the deposited organic layer on it. The ultra-smooth Ag film on the flexible substrate has been applied in inverted top-emitting OLEDs (ITOLEDs) as cathode, which exhibit improved efficiency due to the enhanced electron injection and transport. The maximum current efficiency of the ITOLEDs on the flexible substrate is 9.72 cdA(-1), whereas it is 6.03 cdA(-1) for the devices on the conventional Si substrate, which corresponds to about a 62% enhancement. Moreover, the flexible ITOLEDs keep their good performance under a small bending radius and after repeated bending.

Semi-analytical modeling of Ag and Au nanoparticles and fullerene (C60) embedded gate oxide compound semiconductor MOSFET memory devices

In this paper we present an analytical simulation study of Non-volatile MOSFET memory devices with Ag/Au nanoparticles/fullerene (C60) embedded gate dielectric stacks. We considered a long channel planar MOSFET, having a multilayer SiO2---HfO2 (7.5 nm)---Ag/Au nc/C60 embedded HfO2 (6 nm)---HfO2 (30 nm) gate dielectric stack. We considered three substrate materials GaN, InP and the conventional Si substrate, for use in such MOSFET NVM devices. From a semi-analytic solution of the Poisson equation, the potential and the electric fields in the substrate and the different layers of the gate oxide stack were derived. Thereafter using the WKB approximation, we have investigated the Fowler-Nordheim tunneling currents from the Si inversion layer to the embedded nanocrystal states in such devices. From our model, we simulated the write-erase characteristics, gate tunneling currents, and the transient threshold voltage shifts of the MOSFET NVM devices. The results from our model were compared with recent experimental results for Au nc and Ag nc embedded gate dielectric MOSFET memories. From the studies, the C60 embedded devices showed faster charging performance and higher charge storage, than both the metallic nc embedded devices. The nc Au embedded device displayed superior characteristics compared to the nc Ag embedded device. From the model GaN emerged as the overall better substrate material than Si and InP in terms of higher threshold voltage shift, lesser write programming voltage and better charge retention capabilities.

Enabling Light Emission from Si Based MOSLED on Surface Nano-Roughened Si Substrate

The historical review of Taiwan's researching activities on the features of PECVD grown SiOx are also included to realize the performance of Si nanocrystal based MOSLED made by such a Si-rich SiOx film with embedded Si nanocrystals on conventional Si substrate. A surface nano-roughened Si substrate with interfacial Si nano-pyramids at SiOx/Si interface are also reviewed, which provide the capabilities of enhancing the surface roughness induced total-internal-reflection relaxation and the Fowler-Nordheim tunneling based carrier injection. These structures enable the light emission and extraction from a metal-SiOx-Si MOSLED.

Growth of stoichiometric subnanometer silica films

We present a method to grow stoichiometric SiO2 films of only ∼0.6–0.9nm in thickness on a metal substrate. Based on photoelectron and infrared spectroscopy studies, we conclude that the ∼0.6-nm-thick silica films exhibit characteristics only observed for &amp;gt;2.0-nm-thick films grown on conventional Si substrates. The films can be used as model oxides for fundamental studies and may have implications on the further miniaturization of metal-oxide-semiconductor transistors.

Mechanism of the reduction of dislocation density in epilayers grown on compliant substrates

A simplified model of the mechanism of dislocation reduction in epilayers grown on compliant substrates by molecular-beam epitaxy has been developed based on the dislocation theory and detailed experiments. Theoretical results calculated with this model indicate that up to 100-fold defect reduction can be achieved by using a silicon-on-insulator compliant substrate for the thick epilayer growth as compared to that of using a conventional Si substrate. The advantage of growing thick epilayers on compliant substrates can be predicted quantitatively. The mechanism of a nearly dislocation-free SiGe alloy, as well as GaAs epilayers grown on silicon-on-insulator compliant substrates, is explained and the dislocation density calculated with this model is in good agreement with our experimental results.