Conventional Readout Scheme Research Articles

A Sun-Tracking CMOS Image Sensor With Black-Sun Readout Scheme

This article presents a black-sun readout scheme for CMOS image sensors (CISs) that utilizes the black-sun effect caused by a strong illumination condition. Based on the analysis of the black-sun phenomenon in CISs, the proposed CIS extracts the black-sun indication and its strength images while providing normal images without any degradation. By effectively utilizing the black-sun readout capability, a prototype CIS with the proposed readout scheme was identified as a useful solution to track the brightest source of light. In addition, the proposed black-sun readout scheme is reversible to the conventional readout scheme such that it can be used for various purposes in several electronic devices using CISs. The proposed readout scheme was verified in the typical CIS structure, and it shows the feasibility of utilizing it in sun tracking sensor applications for improving energy conversion efficiency. The prototype chip was implemented in a 0.11- $\mu \text{m}$ 1P4M CIS process with a 2.9- $\mu \text{m}$ pitch.

Efficiency of a microwave reflectometry for readout of a THz multipixel Schottky diode direct detector

In this paper we report on the results of investigation of efficiency of a microwave reflectometry for readout of a terahertz multipixel Schottky diode direct detector. Decent capabilities of the microwave reflectometry readout were earlier justified by us for a hot electron bolometric direct detector. In case of a planar Schottky diode, we observed increase of an optical noise equivalent power by a factor of 2 compared to that measured within a conventional readout scheme. For implementation of a multipixel camera, a microwave reflectometer is to be used to readout each row of the camera, and the row switching is to be maintained by a CMOS analog multiplexer. The diodes within a row have to be equipped with filters to distribute the probing microwave signal properly. The simultaneous use of analog multiplexing and microwave reflectometry enables to reduce the camera response time by a factor of its number of columns.

Experimental Demonstration of Superconducting Series Nanowire Photon-Number-Resolving Detector at 660 nm Wavelength

Photon-number-resolving (PNR) is an important functionality in many applications. The traditional single photon detectors (SNSPDs) operated with the conventional readout scheme does not have the PNR functionality. In this paper, we demonstrate a superconducting photon-number-resolving detector operating at the visible wavelength regime, based on the serial connection of six superconducting nanowires. The results of our 6-element PNR device show clear evidence of n -photons differentiation with n ranging from 1 to 6. The system detection efficiency reaches 54% with the dark counts rate below 10 Hz at 660 nm. The demonstrated 6-element PNR device does not require a complex readout circuit compared with the SNSPD array device, and is expected to have wider applications in addition to imaging and communication.

A predischarged bitline 1T-1C DRAM readout scheme

It is well known that the dynamic random-access memory (DRAM) is one of the main means for primary storage. However, the conventional readout scheme of the one-transistor one-capacitor (1T-1C) DRAM cells requires dealing with the relatively large bitline parasitic capacitance. This causes delay and power penalties. In this paper, a novel fast readout scheme that depends on predischarging the bitline parasitic capacitance is proposed. The several circuit design issues of the proposed scheme is analyzed quantitatively. The proposed scheme is simulated adopting the 45 nm CMOS Berkeley predictive-technology model (BPTM) with a power-supply voltage, VDD, equal to 1 V and shows 48% and 13% reductions in the read-cycle times in cases of reading “0” and “1”, respectively. The power consumption is investigated and compared with that of the conventional readout scheme taking into account the probabilities of occurrences of “0” and “1” storage.

A novel low-latency DRAM based on the bitline-discharge rate

ABSTRACTAs well known by computer architects, the performance gap between the processor and the memory has been increasing over the years. This causes what is known as the memory wall. In order to alleviate the problem, a novel fast readout scheme is proposed in this article for the single-transistor single-capacitor dynamic random-access memory (1T-1C DRAM) cells. The proposed scheme works in the current domain in which the difference between the discharging rates of the bitline in the cases of ‘1’ and ‘0’ readings is detected. The proposed scheme is analysed quantitatively and compared with the conventional readout scheme. It is verified by simulation adopting the 45 nm CMOS Berkley predictive-technology model (BPTM) and shows 44 and 7.7% reductions in the average read-access and cycle times, respectively, as compared to the conventional readout scheme. It is also shown that the power is saved according to the proposed scheme if the probability of occurrence of ‘0’ storage exceeds 66.7%. This minimum value can be alleviated, however, at the expense of a smaller saving in the average read-access time. The impacts of process variations and technology scaling are also taken into account.

A simple SQUID system with one operational amplifier as readout electronics

We describe a dc Superconducting Quantum Interference Device (SQUID) readout electronics in Flux Locked Loop (FLL) mode without integrator and with only one operational amplifier, which is called Single Chip Readout Electronics (SCRE). A weakly damped niobium-SQUID magnetometer with a large flux-to-voltage transfer coefficient of about ∂V/∂Φ ≈ 380 μV/Φ0 and SCRE results in a very simple SQUID system. We characterize the system and demonstrate its applicability to Magnetocardiography (MCG) and measurements using the Transient ElectroMagnetic (TEM) method. SCRE not only simplifies the readout scheme, but also improves the system stability, the bandwidth and the slew rate. The difference between SCRE and a conventional readout scheme (preamplifier + amplifier + integrator) is also discussed.