Conventional Phase-locked Loop Research Articles

Self-cascode and self-biased Dickson charge pump for fast locking wide lock range PLL with reduced phase noise

The charge pump is a fundamental component in phase-locked loop (PLL) circuits, essential for generating a control voltage that adjusts the frequency and phase of the voltage-controlled oscillator (VCO) to match the input reference signal. The self-cascode and self-biased Dickson charge pump architecture presented in this work addresses several key challenges encountered in conventional PLL designs. By integrating self-cascode techniques, the charge pump exhibits enhanced charging and discharging capabilities, enabling faster locking times essential for wide lock range PLLs. This comprehensive approach offers a compact and integrated solution that simultaneously enhances locking speed, widens the lock range, reduces phase noise, and simplifies design complexity, making it highly suitable for demanding applications in communication systems, radar, and wireless technologies. The novel CP is implemented in 90-nm CMOS technology with a 1.0-V supply voltage. It is integrated with a phase-locked loop (PLL) that has a lock time of 1.0 us, a negligible reference spur, and an average power consumption of 34.7 mW. The PLL is having a wide lock range of 0.98 GHz to 2.98 GHz with a center frequency of 1.54 GHz where the phase noise is calculated to be −100.9 dBc/Hz at 1 MHz offset frequency. This makes the PLL compatible with both GSM having 1.8 GHz and Wi-Fi having 2.8 GHz frequency bands. The proposed PLL is also capable of operating at a wide range of temperatures (−27 °C, 0 °C, 27 °C, 84 °C) and at various corners (NN, FS, SF, SS, FF) making it reliable in adverse circumstances.

Research on a New Synchronous Phase-Locked Method for Renewable Energy Grid-connected Converters

Background:: The phase-locked loop (PLL) is widely used to estimate synchronization information such as magnitude and phase angle of the grid voltage, which is essential for gridconnected power generation from distributed renewable energy sources. However, the harmonics in the grid often affect the accurate extraction of fundamental positive sequence, resulting in phase deviations. Methods:: A dual extended novel third-order generalized integrator (DENTOGI) is proposed and placed into the control outer loop of the PLL. This approach can be applied in the condition of the grid with DC offset voltage (DCOV). Additionally, the PLL is proposed by introducing moving average filter (MAF) and eliminating the proportional controller of the integration link to suppress high-frequency harmonics and speed up the response. Results:: A comparative experiment using Matlab/Simulink is conducted to evaluate the proposed PLL against the conventional PLLs. The experimental results confirm that the proposed PLL exhibits superior filtering performance for DC offset and harmonic components when compared to the conventional PLL. Additionally, the proposed PLL demonstrates better dynamic adjustment capabilities. Conclusion:: The main contribution of this paper is to propose a phase-locked method that can eliminate DCOV and harmonic components, which can be applied in non-ideal power grid conditions. The proposed PLL based on DENTOGI and MAF can lock the grid phase stably without errors under the grid fault involving DCOV and harmonic disturbance, it also exhibits the characteristics of fast response.

Enhanced Position Estimation of PMSM Using the Luenberger Observer and PLL Algorithm: Design and Simulation Study

This study proposes an enhanced method for estimating the position of a permanent magnet synchronous motor (PMSM) using the Luenberger observer and phase-locked loop (PLL) algorithm. The main contribution to this research is the use of two low-pass filters (LPF) at the input of the PLL, which results in softer position reconstruction compared with conventional PLL. The proposed method is designed and simulated using the MATLAB/Simulink platform. The performance of the proposed method was evaluated and compared with conventional PLL and PLL with one LPF using several performance metrics such as estimation accuracy, convergence time, and stability. Simulation results show that the proposed method achieves better estimation accuracy and higher stability compared with the other methods. Additionally, the proposed method is robust to various disturbances such as load torque and parameter variations. Overall, the proposed method offers an effective and efficient solution for estimating the position of PMSM in various industrial applications.

Design of a Low-Power Delay-Locked Loop-Based 8× Frequency Multiplier in 22 nm FDSOI

A low-power delay-locked loop (DLL)-based frequency multiplier is presented. The multiplier is designed in 22 nm FDSOI and achieves 8× multiplication. The proposed DLL uses a new simple duty cycle correction circuit and is XOR logic-based for frequency multiplication. Current starved delay cells are used to make the circuit power efficient. The circuit uses three 2× stages instead of an edge combiner to achieve 8× multiplication, thus requiring far less power and chip area as compared to conventional phase-locked loop (PLL) circuits. The proposed 8× multiplier occupies an active area of 0.09 mm2. The measurement result shows ultra-low power consumption of 130 µW at 0.8 V supply. The post-layout simulation shows a timing jitter of 24 ps (pk-pk) at 2.44 GHz.

On Absolute Stability of Open-Loop Synchronized Single-Phase Grid-Following Inverters

This article is concerned with the strict stability problem for grid-following inverters subject to synchronous nonlinearity and large transient disturbances. Firstly, considering that the complex nonlinear structure of the conventional phase-locked loop (PLL)-based grid synchronization scheme may difficult to match the existing intuitive nonlinear analysis methods, a simplified open-loop grid synchronizer is developed for the grid-following control. Subsequently, the sector-bounded condition of the system nonlinear factor is derived by setting the grid voltage and power control variation intervals, and the frequency-domain conditions for absolutely stable are further obtained with the help of the circle criterion. The derived conditions illustrate that the stability assessment is intuitive, because it is only necessary to observe the graphical position of the disk <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$d(-\psi,-\phi)$</tex-math></inline-formula> with respect to the Nyquist curve of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$-\Omega _{\alpha }(s)$</tex-math></inline-formula> . Finally, the effects of weak grid and power control variations on system stability are further analyzed, and the effectiveness of the proposed theories is fully supported by transient experimental results.

A Virtual-Flux State Observer-Based Inductance Identification Method for Model Predictive Control of Grid-Tied Inverters With a Finite Phase Angle Set-Based PLL

To reduce the calculation burden of the conventional finite phase angle set-based phase-locked loop (PLL) and enhance the parameter robustness of the model predictive control for grid-tied inverters (GTIs), an improved finite phase angle set-based PLL and a new inductanceidentification method basedonvirtual-flux state observer (VFSO) are proposed in this paper. First, three improved PLLs are proposed based on the principles of the conventional finite phase angle set-based PLL. Second, the proposed PLLs are further improved by redesigning the cost function, which can search the optimal phase angle within the region of [0, π] instead of [0, 2π], reducing the iteration times. Third, a new VFSO with only one observer parameter is proposed, based on which a new inductance identification method is presented. Fourth, by analyzing the characteristics of the proposed VFSO, it is found that a larger observer gain can improve the dynamic convergence speed of the proposed VFSO, while a smaller one can enhance its robustness against grid frequency deviation. So, an observer gain adaptive method is proposed, aiming to improve both the dynamic and steady state control performance of the proposed inductance identification method. Finally, comparative experimental studies verify the effectiveness of the proposed strategies.

Analysis of optimized phase locked loop for grid synchronization of solar PV system under grid disturbances

AbstractIn this work, an optimal phase locked loop (PLL) is employed to estimate the fundamental grid frequency and phase angle under grid disturbances, which largely reduces the frequency and phase error. Conventional synchronous reference frame (SRF) offers considerable results for balanced grid conditions but has poor performance under grid disturbances with improper phase detection. In this regard, gravitational search algorithm (GSA)‐based optimization is utilized to optimally tune the proportional and integral (PI) gain values of conventional SRF PLL, which ensures the proper tracking of fundamental phase angle and frequency even during abnormal grid conditions, that is, voltage unbalance, frequency variations, high‐frequency harmonics, and phase variations. Further, integral square error (ISE) criteria, settling time, and overshoot are considered as objective functions to obtain the optimal value of current gain, present in the control loop of a grid‐tied solar photovoltaic (PV) system. The supremacy of the proposed work, compared to SRF and optimal SRF PLL, is tested with MATLAB®/Simulink studies and verified by dSPACE‐1104‐based hardware‐in‐loop (HIL) results for real‐time validation.

Shunt Active Power Filter Based on Savitzky-Golay Filter: Pragmatic Modelling and Performance Validation

This manuscript introduces a novel reference current generation technique based on the Savitzky-Golay Filter (SGF) for Shunt Active Power Filter (SAPF). Although the existing and conventional SAPF can mitigate harmonics under grid disturbances and nonlinear load environments, they have numerous performance deficiencies including computational complexity, average filtration ability, and slow dynamic response. The proposed SAPF based on SGF can generate a harmonic-free fundamental reference current that can eventually improve the overall harmonic profile and performance compared to existing SAPFs. In addition, an SGF-based Phase-Locked Loop (PLL) is introduced to generate reference phases directly from the distorted grid voltages by retaining the fundamental information of the signal. Thus, it does not induce any phase delay or distortions in the output, unlike the conventional PLLs utilized in the SAPFs. Comparative analysis of performance evaluation is carried out with other SAPFs, and the findings represent the principal achievements of this manuscript. This includes a substantial improvement in performance and harmonic profile under transient conditions. The results are further validated through simulation analysis and hardware implementation.

Phase Demodulation Strategy Based on Kalman Filter for Sinusoidal Encoders

Phase demodulation strategy based on Kalman filter for sinusoidal encoders is proposed in this paper. For the state equation and observation equation in the constructed phase demodulation model, the phase angle, the phase angular speed, and the speed fluctuation are the system states, and the sine and cosine signals output by the encoder are the system observations. In addition, due to the nonlinear relationship between the observations and the system states, the observation function is linearized by the extended Kalman approach. In order to implement the Kalman filter on the hardware platform with a field programmable gate array (FPGA), the matrix model of the Kalman filter is further derived into an algebraic model, which only contains sine, cosine, and basic algebraic operations. Compared to the arctangent method, the proposed method has the noise suppression capability, and compared to the conventional phase-locked loop (PLL) method, the proposed method has the better dynamic performance without the acceleration-associated phase error. Both simulation and experimental results can prove the effectiveness of the proposed method.

Improved Single-phase PLL Based on All-Pass Filter

The detection accuracy of a conventional phase-locked loop for a single phase is affected by the interference of the DC component and harmonic component when the grid has a lot of problems such as harmonic interference and DC offset, and It will be unable to accurately track the grid voltage frequency and phase. The traditional APF-PLL is improved to address this problem. An improved phase-locking algorithm is proposed, combining a CSOGI and a FLL with the conventional single-phase phase-locked loop. The method incorporates CSOGI into the APF-PLL pre-stage to reduce interference from DC and harmonic components, while FLL achieves the frequency tracking of the input signal and improves the adaptivity and dynamic response speed of the phase-locked loop. Through simulation verification, the proposed new phase-locked loop can improve the frequency tracking capability, dynamic performance, and precision of the locking phase of the PLL.

Optimized MASH-SR Divider Controller for Fractional-N Frequency Synthesizers

The divider controller in a conventional phase-locked loop fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> frequency synthesizer modulates the instantaneous division ratio of the feedback divider. The divider controller is typically a digital circuit that performs quantization of its input signal. Multi-stage noise shaping digital delta-sigma modulators (MASH DDSMs) and successive requantizer (SRs) are two representative divider controller architectures offering lower complexity and better spur performance, respectively. The MASH-SR, as a hybrid of these two classes of divider controllers, can achieve both lower hardware cost than the SR and better performance against spurs than a MASH DDSM. In this work, we present an optimized MASH-SR hybrid and compare the design with its conventional MASH DDSM and SR counterparts.

A Calibration-Free Digital-to-Time Converter for Phase Interpolation-Based Fractional-N PLLs

In this paper, a fractional frequency division phase-locked loop based on phase interpolation is proposed and implemented using the TSMC 0.11 μm CMOS process. Compared with the conventional phase-locked loop, a digital time converter (DTC) module is added to this phase-locked loop, and the DTC module can reduce the fractional spurious by phase interpolation. The circuit and analysis method of this DTC module are given in this paper. Unlike the existing approaches, the proposed DTC is calibration-free, and the error introduced by it is only related to the DAC adopted in the DTC. In addition, the accuracy of the DTC is 8 bits. Finally, this paper verifies the proposed quantization noise reduction technique using a 0.11 μm CMOS process. The proposed FNPLL achieves the overall power consumption of 20.3 mW, the noise of −117dBc/Hz@1 MHz and −138dBc/Hz@10 MHz, and the RMS jitter of 0.860ps. The area of the proposed FDIV is 60×245μm2, and the power consumption is 1.356mW. The phase noise of the proposed FNPLL in the fractional division mode is just 2dB higher than that in the integer division mode.

DC-AC Converter with Dynamic Voltage Restoring Ability Based on Self-Regulated Phase Estimator-DQ Algorithm: Practical Modeling and Performance Evaluation

A self-regulated phase estimator (SRPE)-based DQ algorithm for a DC-AC converter with dynamic voltage restoring (DVR) ability is presented in this paper. When compared to the conventional phase-locked loop (PLL), the provided controller can significantly reduce phase distortions and low-order harmonics from the load voltage while attaining quicker dynamic response. Furthermore, the fundamental attribute of the load voltage allows the integrated DC-AC converter to operate at a consistent frequency eliminating frequency oscillations. The SRPE is utilized primarily in the DQ control theory as the reference voltage generator which can compensate for the grid voltage. SRPE has good band-pass filtering properties and a mathematically simple structure that can thoroughly attenuate voltage imbalance and has quick dynamic response. The SRPE has been made to be frequency-adaptive using a damping factor and robust grid frequency estimation. The SRPE can maintain the fundamental frequency at 50 Hz and keep the total harmonic distortions (THD) within the 5% limit even during grid disruptions. The DC-AC converter and SRPE-DQ’s stability are thoroughly examined. The experiment is carried out to show the efficacy of the suggested complete control system. There are also comparative simulation studies to show the benefits of the suggested technique. The results reveal that the suggested approach can immediately identify and correct for any grid voltage imbalance while also assisting in maintaining the constant voltage at the load side despite voltage sag/swell and distortions.

Small-signal Stability Analysis and Improvement with Phase-shift Phase-locked Loop Based on Back Electromotive Force Observer for VSC-HVDC in Weak Grids

Voltage source converter based high-voltage direct current (VSC-HVDC) transmission technology has been extensively employed in power systems with a high penetration of renewable energy resources. However, connecting a voltage source converter (VSC) to an AC weak grid may cause the converter system to become unstable. In this paper, a phase-shift phase-locked loop (PS-PLL) is proposed wherein a back electromotive force (BEMF) observer is added to the conventional phase-locked loop (PLL). The BEMF observer is used to observe the voltage of the infinite grid in the stationary <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\alpha\beta$</tex> frame, which avoids the problem of inaccurate observations of the grid voltage in the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$dq$</tex> frame that are caused by the output phase angle errors of the PLL. The VSC using the PS-PLL can operate as if it is facing a strong grid, thus enhancing the stability of the VSC-HVDC system. The proposed PS-PLL only needs to be properly modified on the basis of a traditional PLL, which makes it easy to implement. In addition, because it is difficult to obtain the exact impedance of the grid, the influence of short-circuit ratio (SCR) estimation errors on the performance of the PS-PLL is also studied. The effectiveness of the proposed PS-PLL is verified by the small-signal stability analysis and time-domain simulation.

Robust Frequency-Adaptive Quadrature Phase-Locked-Loops With Lyapunov-Certified Global Stability

This work describes and compares two phase-locked-loop (PLL) algorithms aimed at tracking a biased sinusoidal signal with unknown frequency, amplitude, and phase, with inherent robustness to dc offset. The proposed methods endow quadrature PLLs, renowned for their excellent tracking performance, with frequency-adaptation capability, while providing robust global stability certificates. The large-gain global stability, proved by Lyapunov-like arguments borrowed from adaptive control theory, represents a major benefit when compared to the conventional PLLs, whose convergence instead can be proved only locally by small-signal analysis or small-gain assumptions. In this connection, the proposed algorithms represent the first frequency-adaptive and dc-bias rejecting PLL-type architectures with Lyapunov-certified global stability. When used for signal tracking, the proposed methods are shown to outperform the adaptive observer, especially in noisy conditions. Moreover, they provide more accurate frequency estimates than existent frequency-adaptive PLLs, showing enhanced robustness in facing both phase-noise and measurement perturbations.

Improved AVF-PLL-Based Position Estimation Scheme for SPMSM Sensorless Drives

The combination of a high-performance filter and phase-locked loop (PLL) has been presented as an effective alternative for the position estimation of a permanent magnet synchronous motor (PMSM) drive. However, the feedback delays existing in the practical implementation of the filter and PLL usually lead to position estimation deviation. To enhance the accuracy of position estimation, this paper proposes a sensorless control technology based on an improved adaptive vectorial filter (AVF) and PLL. First, the effect of feedback delay on the filtering performance of the AVF and the tracking performance of the PLL are analyzed. Then, corresponding delay compensation methods for the AVF and PLL are proposed. A compensation term based on the prediction of the filtered back electromotive force (EMF), which can repress the filtering performance degradation caused by feedback delays, is introduced and combined with the conventional AVF. As a result, the amplitude and phase shifts with the filtered back EMF can be effectively eliminated before applying it to the PLL. A differential calculation structure, which can ensure that the closed-loop transfer function of the equivalent ideal PLL is the same as the ideal PLL under the condition of feedback delay, is proposed to replace the cascade calculation structure of the conventional PLL. In addition, an open-loop deviation compensation method is integrated to eliminate the position estimation static deviation. The effectiveness of the proposed sensorless control technology is investigated by experimental tests.

A Robust Control for Solar and SyRG Based Hydro Generation Microgrid With Grid Synchronization

The control of a microgrid is quite challenging thus this work implements a robust and fast control technique based on an enhanced second-order generalized integrator with a modified frequency locked loop (ESOGI-MFLL) for switching operation between an islanded and the grid-connected mode. For phase angle estimation, a circular limited cycle oscillator frequency locked loop with an inner loop filter (CLO-FLL-WIF) is implemented instead of a conventional phase-locked loop technique to provide better synchronization performance for polluted grid voltages. This microgrid is combing a solar photovoltaic (PV) generation, a synchronous reluctance generator for pico-hydro generation, and the battery, which works in both standalone and grid-connected modes while feeding local loads uninterruptedly. The output power conversion of a PV array is influenced by irradiation of the solar PV array; therefore, a maximum power point tracking namely an incremental conductance method is used. The implemented control techniques are used for fundamental extraction of load components of voltage and currents for assessment of reference currents with their respective phases of synchronization while maintaining the required IEEE power quality standard-519. In addition, the comparative results validate the faster response of ESOGI-MFLL control algorithm to the existing control algorithm. Simulated and test results of a microgrid for islanded, switching mode, and grid-connected mode demonstrate its performance under load unbalance and generation perturbation.

Modified LMS synchronization technique for distributed energy resources with DC-offset and harmonic elimination capabilities

Grid synchronization techniques are needed to improve the distribution system’s power quality with the Shunt Active Power Filter (SAPF). The traditional synchronization technique or the Phase Locked Loop (PLL) works well under ideal grid conditions; however, its performance deteriorates under non-ideal grid conditions. In this paper, a new scheme has been proposed to function as PLL. The Modified Least Mean Square (MLMS)-PLL has been proposed for tracking the phase angle under non-ideal grid conditions such as phase shift, frequency deviation, harmonics in the signal, DC offset and combinations of these grid voltage issues. The proposed method has added the advantage of DC-offset estimation and perfect synchronization template generation over conventional PLL. The MLMS-PLL algorithm precisely estimates phase, amplitude and frequency information and generates a synchronizing signal under abnormal grid conditions. The designed algorithm is extensively tested and shows advantages such as least steady-state error, faster dynamics and DC-offset rejection capability. Experimental findings of the proposed synchronizing technique show the effectiveness of the proposed technique and experimental results are also compared with other modern synchronization techniques. The application of MLMS-PLL for synchronization, reactive power compensation and harmonic elimination in a grid-tied PV system has been validated in the experimental prototype.

Improved Grid Impedance Compensation for Phase-Locked Loop to Stabilize the Very-Weak-Grid Connection of VSIs

Voltage source inverters (VSIs) with vector control based on phase-locked loop (PLL) suffer instability when connecting to a very weak AC grid (short circuit ratio (SCR) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$ &lt; $</tex-math></inline-formula> 1.3). The conventional inductive grid impedance compensation for the PLL by virtually reducing the grid impedance can stabilize this connection. However, the analysis in this paper indicates that its stabilization effectiveness is sensitive to grid impedance variance and, indeed, overcompensation causes the PLL instability. Therefore, in this paper, an improved grid impedance compensation for the PLL is proposed to achieve the same stabilization for very-weak-grid connection and possess a good tolerance of grid impedance variance and overcompensation. A comprehensive small-signal model of the VSI using the proposed PLL’s grid impedance compensation is derived for stability analysis and parameter design. The time-domain simulation for this VSI is built to validate the stability analysis. Comparison studies for both proposed and conventional PLL’s grid impedance compensation are conducted including the stability effectiveness, VSI performance and grid impedance variance.

Small-Signal Synchronization Stability Enhancement of Grid-Following Inverters via a Feedback Linearization Controller

This paper proposes a feedback linearization controller for a grid-following inverter (GFLI) that uses a conventional Phase-Locked Loop (PLL) as the synchronization unit. The proposed controller enhances the GFLI synchronization by expanding the PLL domain of attraction to the whole plane that is limited to a small region around the equilibrium point in a conventional PLL, provided that the grid impedance and voltage are known. Linearizing the overall closed-loop system, the proposed controller provides linear system attributes for the PLL, leading to an infinite domain of attraction and only one equilibrium point. Additionally, a state-feedback controller is integrated within the feedback linearization controller so that it enables the system to have an adjustable dynamic response. Finally, it is shown that the system is robust against parametric uncertainties. The performance of the proposed control design is validated in Matlab/Simulink and experiment. It is verified that the proposed controller expands the domain of attraction and enhances the system dynamic response.