Conventional Metal-oxide-semiconductor Field-effect Transistor Research Articles

Fabrication of lateral diamond MOSFET with buried pn-junctions by diamond surface planarization based on carbon solid solution into nickel

New fabrication processes for buried p+-type diamond using etching techniques based on the solid-solution reaction of carbon with nickel were proposed and demonstrated. Specifically, an inversion-channel diamond metal-oxide-semiconductor field-effect transistors (MOSFETs) with source and drain regions buried in the body were fabricated, and their operation were confirmed. An etching process using etching techniques based on the solid-solution reaction of carbon with nickel was applied to realize trench formation and planarization after the growth of a p+-type diamond. The fabricated MOSFET exhibited drain current density equivalent to that of conventional MOSFET with source and drain p+-type regions deposited as islands on an n-type body, and ideal field-effect transistor characteristics with linear and saturation regions, and the drain current density was controlled by the gate voltage. However, the surface protrusion structure owing to the incomplete planarization process limited the device characteristics. The proposed fabrication processes for buried layers are expected to function as an important selective doping technique for diamond electronic devices such as ion implantation.

A Novel Deep-Trench Super-Junction SiC MOSFET with Improved Specific On-Resistance.

In this paper, a novel 4H-SiC deep-trench super-junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a split-gate is proposed and theoretically verified by Sentaurus TCAD simulations. A deep trench filled with P-poly-Si combined with the P-SiC region leads to a charge balance effect. Instead of a full-SiC P region in conventional super-junction MOSFET, this new structure reduces the P region in a super-junction MOSFET, thus helping to lower the specific on-resistance. As a result, the figure of merit (FoM, BV2/Ron,sp) of the proposed new structure is 642% and 39.65% higher than the C-MOS and the SJ-MOS, respectively.

A Study on the Design Method of Hybrid MOSFET-CNTFET Based SRAM – A Secondary Publication

More than 10,000 carbon nanotube field-effect transistors (CNTFETs) have been successfully integratedinto one semiconductor chip using conventional semiconductor design procedures and manufacturing processes. Thesetransistors offer advantages such as high carrier mobility, large saturation velocity, low intrinsic capacitance, flexibility, andtransparency. The three-dimensional multilayer structure of the CNTFET semiconductor chip, along with ongoing researchin CNTFET manufacturing processes, increases the potential for creating a hybrid MOSFET-CNTFET semiconductorchip. This chip combines conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) and CNTFETs inone integrated system. This paper discusses a methodology to design 6T binary static random-access memory (SRAM)using a hybrid MOSFET-CNTFET. This paper introduces a method for designing a hybrid MOSFET-CNTFET SRAMby leveraging existing MOSFET SRAM or CNTFET SRAM design approaches. Additionally, this paper compares itsperformance with conventional MOSFET SRAM and CNTFET SRAM designs.

Design and Performance Analysis of Logic Circuits using FinFET Technology

As the dimensions of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) decreases, the short channel effect (SCE) becomes a dominating concern in VLSI. The Short channel effect causes an exponential increase in the leakage current. To reduce the SCE and hence leakage current, a new technology has been developed in recent years. In this recent technology a 3D multiple gate MOSFETs like FinFET (Fin Field Effect Transistor) has been developed which possess numerous advantages over conventional MOSFETs and has attracted many engineers and designers. FinFET is the new growing technology that works in the nm range to minimize short channel effects. Many companies (like Intel) have started using FinFET technology. This document is a review paper of current research on FinFET technology and discusses how it can be used in future to design new logic devices (like Adder, Comparator, MUX and De-MUX etc.) and memory devices. Various parameters of FinFET like reduced short channel effects, less leakage current, low power consumption, less propagation delay and less time delay are discussed. Various mathematical models and software (HSpice) were used to simulate power, delay, power delay product, average power dissipation and energy delay product. Thus, FinFET technology was designed to eliminate the problem of SCE by permitting transistors to be scaled down into sub 20nm range.

Synergic Effect of Misaligned Gate and Temperature on Hetero‐Dielectric Double‐Gate Junctionless Metal–Oxide‐Semiconductor Field‐Effect Transistors for High‐Frequency Application

Junctionless metal–oxide‐semiconductor field‐effect transistors (MOSFETs) have emerged as a promising alternative to conventional MOSFETs, offering simplified fabrication and potential performance improvements. The novelty of this research lies in the selection of hetero‐dielectric material to optimize the performance of junctionless transistors under the misaligned gate and high‐temperature conditions, and the aim is to explore its capability for low‐power high‐frequency application. The results reveal that the proposed junctionless field effect transistor exhibits increased transconductance (17 mS), which enables higher gain (311 dB) and diminishes capacitive effects, leading to a broader range of cutoff frequencies (154 GHz) with gain frequency product and gain transconductance frequency product are 31 and 95.9 THz, respectively. Moreover, this research article investigates critical reliability issues related to junctionless MOSFET, focusing on gate misalignment and thermal stability. The study reveals that gate misalignment reduces on‐current and degrades device performance. Additionally, the study examines thermal stability over a wide temperature range (300 to 500 K), exploring the impact of temperature on performance. These valuable findings provide crucial insights to overcome fabrication challenges and drive the practical adoption of junctionless MOSFETs in future integrated circuits. To assess device performance in high‐frequency applications, Silvaco ATLAS TCAD tools are employed.

Study of Solar Cells Using FISH MOSFETs as a Constructive Element to Generate Photocurrent in the Longitudinal Direction

According to a study by the International Energy Agency (IEA), solar energy could reach 30% in 2023 in countries with the most excellent installed generation capacity, such as China, Germany, Japan, and the United States of America. In other countries, like Brazil (mainly in Paraiba state), for instance, the volume of investments in the solar energy sector is equal to 4.17 billion Reais of private investments in 2022 to implement a photovoltaic module factory to reach an installed capacity of 1.6GW. In this context, several efforts have been made to boost the electrical performance of solar cells in terms of using new materials, fabrication processes, and constructive essential elements to produce electric energy with more efficiency. Thus, this paper performs, by three-dimensional numerical simulations, a comparative study between solar cells implemented with constructive elements based on Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), N channel, depletion type, with two types of gate geometries, in which one is layouted with the typical rectangular (Rectangular MOSFET, RM) and other is implemented with the FISH layout style (FISH MOSFET, FM). The main results have shown that the solar cell implemented with the FISH MOSFET has an efficiency of approximately 57% higher than that presented in the solar cell implemented with the Conventional MOSFET. Therefore, the solar cells implemented with FISH MOSFETs can be considered an alternative constructive essential element to improve the electrical performance of solar cells.

SiC trench MOSFET with dual shield gate and optimized JFET layer for improved dynamic performance and safe operating area capability

A novel silicon carbide (SiC) trench metal–oxide–semiconductor field-effect transistor (MOSFET) with a dual shield gate (DSG) and optimized junction field-effect transistor (JFET) layer (ODSG-TMOS) is proposed. The combination of the DSG and optimized JFET layer not only significantly improves the device’s dynamic performance but also greatly enhances the safe operating area (SOA). Numerical analysis is carried out with Silvaco TCAD to study the performance of the proposed structure. Simulation results show that comparing with the conventional asymmetric trench MOSFET (Con-ATMOS), the specific on-resistance (R on,sp) is significantly reduced at almost the same avalanche breakdown voltage (BV av). Moreover, the DSG structure brings about much smaller reverse transfer capacitance (C rss) and input capacitance (C iss), which helps to reduce the gate–drain charge (Q gd) and gate charge (Q g). Therefore, the high frequency figure of merit (HFFOM) of R on,sp ⋅ Q gd and R on,sp ⋅ Q g for the proposed ODSG-TMOS are improved by 83.5% and 76.4%, respectively. The switching power loss of the proposed ODSG-TMOS is 77.0% lower than that of the Con-ATMOS. In addition, the SOA of the proposed device is also enhanced. The saturation drain current (I d,sat) at a gate voltage (V gs) of 15 V for the ODSG-TMOS is reduced by 17.2% owing to the JFET effect provided by the lower shield gate (SG) at a large drain voltage. With the reduced I d,sat, the short-circuit withstand time is improved by 87.5% compared with the Con-ATMOS. The large-current turn-off capability is also improved, which is important for the widely used inductive load applications.

A SiC asymmetric cell trench MOSFET with a split gate and integrated p+-poly Si/SiC heterojunction freewheeling diode

A new SiC asymmetric cell trench metal–oxide–semiconductor field effect transistor (MOSFET) with a split gate (SG) and integrated p+-poly Si/SiC heterojunction freewheeling diode (SGHJD-TMOS) is investigated in this article. The SG structure of the SGHJD-TMOS structure can effectively reduce the gate-drain capacitance and reduce the high gate-oxide electric field. The integrated p+-poly Si/SiC heterojunction freewheeling diode substantially improves body diode characteristics and reduces switching losses without degrading the static characteristics of the device. Numerical analysis results show that, compared with the conventional asymmetric cell trench MOSFET (CA-TMOS), the high-frequency figure of merit (HF-FOM, R on,sp × Q gd,sp) is reduced by 92.5%, and the gate-oxide electric field is reduced by 75%. In addition, the forward conduction voltage drop (V F) and gate-drain charge (Q gd) are reduced from 2.90 V and 63.5 μC/cm2 in the CA-TMOS to 1.80 V and 26.1 μC/cm2 in the SGHJD-TMOS, respectively. Compared with the CA-TMOS, the turn-on loss (E on) and turn-off loss (E off) of the SGHJD-TMOS are reduced by 21.1% and 12.2%, respectively.

The Advantages and Applications of IGBT Compared with Conventional BJT and MOSFET

Nowadays, the power semiconductor devices have been used in many fields like wind power generation systems, the rail transit. Bipolar junction transistors (BJTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs) as well as some other devices are the dominating the market. The insulated gate bipolar transistor (IGBT) as a mixed device of the BJT and the MOSFET, has a preeminent performance. In this paper, the characteristics of the punch through IGBT (PT-IGBT), the MOSFET and the BJT will be investigated by TCAD. Then the PT-IGBT is compared with the BJT and the MOSFET, for concluding its advantages. According to the simulation result, the PT-IGBT has the on-state current of 9*10-4A and the forward blocking voltage of 1200V, which are much higher than the other two devices. In the end of the paper, the development of the semiconductor devices is predicted, about the research trends.

High Performance 3.3 kV SiC MOSFET Structure with Built-In MOS-Channel Diode

Built-in freewheeling diode metal–oxide–semiconductor field-effect transistors (MOSFETs) that ensure high performance and reliability at high voltages are crucial for chip integration. In this study, a 4H–SiC built-in MOS-channel diode MOSFET with a center P+ implanted structure (CIMCD–MOSFET) is proposed and simulated via technology computer-aided design (TCAD). The CIMCD–MOSFET contains a P+ center implant region, which protects the gate oxide edge from high electric field crowding. Moreover, the region also makes it possible to increase the junction FET (JFET) and N-drift doping concentration of the device by dispersing the high electric field. Consequently, the CIMCD–MOSFET is stable even at a high voltage of 3.3 kV without static degradation and gate oxide reliability issues. The CIMCD–MOSFET also has higher short-circuit withstanding capability owing to the low saturation current and improved switching characteristics due to the low gate-drain capacitance, compared to the conventional MOSFET (C–DMOSFET) and the built-in Schottky barrier diode MOSFET (SBD–MOSFET). The total switching time of a CIMCD–MOSFET is reduced by 52.2% and 42.2%, and the total switching loss is reduced by 67.8% and 41.8%, respectively, compared to the C–DMOSFET and SBD–MOSFET.

Second Generation of Layout Styles to Further Boosting the Electrical Performance and Reducing the Die Area of Analog MOSFETs

Previous studies have been showing that the first generation of layout styles composed by the Diamond (hexagonal), Octo (octagonal) and Ellipsoidal gate shapes for implementing of the planar and three-dimensional MOSFETs are is capable of boosting their analog and digital electrical performances and also by reducing used die areas, when we replace conventional Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), that present rectangular gate shape, by those implemented by these innovative layout styles. In order to further boosting these features obtained by the use of first generation of layout styles, we are introducing one of elements of the second generation of layout styles for MOSFETs, intitled Half-Diamond. This new proposal is an evolution of Diamond layout style, in which it is able to preserve the Longitudinal Corner Effect (LCE), the Parallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivation of Parasitic MOSFETs in Bird’s Beaks Regions (DEMPAMBBRE) effects of the first generation and also of further reducing the dimensions of conventional MOSFETs (CM) in which the Diamond MOSFETs have gotten to do. Thus, this work performs an experimental comparative study between the electric performances of MOSFETs implemented with the Half-Diamond, Diamond and Conventional layout styles, regarding the analog Complementary MOS (CMOS) integrated circuits (ICs) applications, which their channel lengths are not usually designed with the minimum dimension (Lmin) allowed by the CMOS ICs manufacturing processes. The results obtained show that, for instance, the saturation drain current normalized by the aspect ratio and low-frequency open-loop voltage gain, in dB, of MOSFET implemented with the Half-Diamond layout style (HDM) are 17% and 3.5% higher, respectively, than those found in CM counterparts. Besides, by using Half-Diamond layout style, it is possible of further reducing the die areas of analog CM and consequently of the analog CMOS ICs applications, in comparison to those reached by the use of Diamond layout styles, regarding a 180 nm Bulk CMOS ICs technology node.

Failure Mechanism of Aluminum Diffusion in Low-Voltage Trench MOSFET With High Cell Density

In this paper, a low-voltage trench metal oxide semiconductor field effect transistor (MOSFET) with high cell density is researched on the process design. The experimental device pitch is reduced to 0.5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mu }\text{m}$ </tex-math></inline-formula> by three-dimensional (3-D) design of P plus region and self-aligned process, while the contact between silicon and metal is convex rather than the concave in conventional trench MOSFET. BV failure was founded because of the particularity of this structure and the failure is caused by the diffusion of aluminum (Al) into the drift region during the final alloy step in the metal forming process. This paper reveals the mechanism of Al / Silicon (Si) double diffusion and presents the refined surface metal film, which can suppress reverse diffusion and forward diffusion simultaneously. The risk of failure is reduced and functional devices are obtained by the application of the proposed surface metal film. Furthermore, it is recommended to use TiN layers in a total 50 nm as the barrier layer in the metallization process to provide a certain diffusion length and the fabricated device achieves a low specific on-resistance of 3.58 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega \cdot $ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with a corresponding breakdown voltage of 26.2 V eventually.

High-performance vertical GaN field-effect transistor with an integrated self-adapted channel diode for reverse conduction

A vertical GaN field-effect transistor with an integrated self-adapted channel diode (CD-FET) is proposed to improve the reverse conduction performance. It features a channel diode (CD) formed between a trench source on the insulator and a P-type barrier layer (PBL), together with a P-shield layer under the trench gate. At forward conduction, the CD is pinched off due to depletion effects caused by both the PBL and the metal–insulator–semiconductor structure from the trench source, without influencing the on-state characteristic of the CD-FET. At reverse conduction, the depletion region narrows and thus the CD turns on to achieve a very low turn-on voltage (V F), preventing the inherent body diode from turning on. Meanwhile, the PBL and P-shield layer can modulate the electric field distribution to improve the off-state breakdown voltage (BV). Moreover, the P-shield not only shields the gate from a high electric field but also transforms part of C GD to C GS so as to significantly reduce the gate charge (Q GD), leading to a low switching loss (E switch). Consequently, the proposed CD-FET achieves a low V F of 1.65 V and a high BV of 1446 V, and V F, Q GD and E switch of the CD-FET are decreased by 49%, 55% and 80%, respectively, compared with those of a conventional metal–oxide–semiconductor field-effect transistor (MOSFET).

An enhanced high frequency performance SiC MOSFET with self-adjusting P-shield region potential

An enhanced high frequency (HF) performance SiC metal oxide semiconductor field effect transistor (MOSFET) with self-adjusting P-shield region potential (SA-MOS) is proposed and characterized in this paper. The potential of P-shield region (ground or floating potential) can be adjusted by a depletion P-channel metal oxide semiconductor field effect transistor (PMOS) structure integrated in the SA-MOS. During turn-on of SA-MOS, the channel of integrated PMOS is pinched off and the P-shield region can be at a floating potential. Therefore, SA-MOS shows about 21% specific on-resistance (R on,sp) reduction as compared to the conventional trench gate SiC MOSFET with grounded P-shield (GP-MOS) due to the retraction of depletion layer in drift region. During turn-off of SA-MOS, the integrated PMOS is turned on and the P-shield region is grounded to the source contact. Thus, the high on-state oxide electric field and slower switching speed caused by the floating P-shield region could be eliminated by SA-MOS structure. Furthermore, the gate-to-drain charge (Q gd) of SA-MOS is only 217 nC cm−2 owing to smaller overlap area between drift region and trench gate, which is about 40% lower than that of GP-MOS. The HF figures of merit (HF-FOM= R on,sp × Q gd) for SA-MOS can be as low as 50% or more of GP-MOS. Finally, an analytical model is also developed to describe the variation of P-shield potential in SA-MOS. With the overall improved performance, SA-MOS shows a significant advantage in HF field in comparison with the GP-MOS.

A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance

An optimized silicon carbide (SiC) trench metal-oxide-semiconductor field-effect transistor (MOSFET) structure with side-wall p-type pillar (p-pillar) and wrap n-type pillar (n-pillar) in the n-drain was investigated by utilizing Silvaco TCAD simulations. The optimized structure mainly includes a p+ buried region, a light n-type current spreading layer (CSL), a p-type pillar region, and a wrapping n-type pillar region at the right and bottom of the p-pillar. The improved structure is named as SNPPT-MOS. The side-wall p-pillar region could better relieve the high electric field around the p+ shielding region and the gate oxide in the off-state mode. The wrapping n-pillar region and CSL can also effectively reduce the specific on-resistance (R on,sp). As a result, the SNPPT-MOS structure exhibits that the figure of merit (FoM) related to the breakdown voltage (V BR) and R on,sp () of the SNPPT-MOS is improved by 44.5%, in comparison to that of the conventional trench gate SJ MOSFET (full-SJ-MOS). In addition, the SNPPT-MOS structure achieves a much faster-witching speed than the full-SJ-MOS, and the result indicates an appreciable reduction in the switching energy loss.

High-performance SiC MOSFET embedded heterojunction diode with electric field protection region

In this study, we proposed high-performance SiC metal-oxide-semiconductor field effect transistors (MOSFETs) embedded heterojunction diode (HJD) with an electric field protection (EFP) region and analyzed it using a Sentaurus TCAD simulation. The proposed device features an HJD positioned at the trench side wall in the middle of the junction field effect transistor region and a highly doped EFP region under the P+ polysilicon to features excellent static performance and high reliability. The simulation results revealed that the maximum oxide electric field (E MOX) and the Baliga’s figure-of-merit improved by 54% and 12%, respectively, compared with those of conventional SiC MOSFETs (C-MOSFETs). In addition, the EFP region suppressed the drain induced barrier lowering effect and leakage current in the HJD interface sufficiently. The HJD suppressed the bipolar degradation of the PiN body diode effectively due to its low V F (1.75 V). In addition, the proposed device demonstrated superior reverse-recovery characteristics, thereby improving t rr and Q rr by 35% and 57%, respectively, compared to the corresponding values in C-MOSFET. Moreover, the input capacitance (C ISS) was reduced by 17.5%, and C GD was reduced by 96%. Therefore, the high-frequency figure-of-merit improved by a factor of 25.8 in terms of R ON × C GD. As a result, the proposed device is a promising structure for high-frequency and high-reliability applications.

Asymmetric Split-Gate 4H-SiC MOSFET with Embedded Schottky Barrier Diode for High-Frequency Applications

4H-SiC Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) with embedded Schottky barrier diodes are widely known to improve switching energy loss by reducing reverse recovery characteristics. However, it weakens the static characteristics such as specific on-resistance and breakdown voltage. To solve this problem, in this paper, an Asymmetric 4H-SiC Split Gate MOSFET with embedded Schottky barrier diode (ASG-MOSFET) is proposed and analyzed by conducting a numerical TCAD simulation. Due to the asymmetric structure of ASG-MOSFET, it has a relatively narrow junction field-effect transistor width. Therefore, despite using the split gate structure, it effectively protects the gate oxide by dispersing the high drain voltage. The Schottky barrier diode (SBD) is also embedded next to the gate and above the Junction Field Effect transistor (JFET) region. Accordingly, since the SBD and the MOSFET share a current path, the embedded SBD does not increase in RON,SP of MOSFET. Therefore, ASG-MOSFET improves both static and switching characteristics at the same time. As a result, compared to the conventional 4H-SiC MOSFET with embedded SBD, Baliga′s Figure of Merit is improved by 17%, and the total energy loss is reduced by 30.5%, respectively.

Implementation of 20 nm Graphene Channel Field Effect Transistors Using Silvaco TCAD Tool to Improve Short Channel Effects over Conventional MOSFETs

In recent years, demands for high speed and low power circuits have been raised. As conventional metal oxide semiconductor field effect transistors (MOSFETs) are unable to satisfy the demands due to short channel effects, the purpose of the study is to design an alternative of MOSFETs. Graphene FETs are one of the alternatives of MOSFETs due to the excellent properties of graphene material. In this work, a user-defined graphene material is defined, and a graphene channel FET is implemented using the Silvaco technology computer-aided design (TCAD) tool at 100 nm and scaled to 20 nm channel length. A silicon channel MOSFET is also implemented to compare the performance. The results show the improvement in subthreshold slope (SS) = 114 mV/dec, ION/IOFF ratio = 14379, and drain induced barrier lowering (DIBL) = 123 mV/V. It is concluded that graphene FETs are suitable candidates for low power applications.

A critical evaluation based on Lattice Boltzmann method of nanoscale thermal behavior inside MOSFET and SOI-MOSFET

In recent years, the world has witnessed a huge technological revolution in terms of manufacturing electronic devices and reducing their size, which has reached nanoscale. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is one of these devices. However, with its downsizing, it affects the efficiency of its associated devices due to the generated heat. In this paper, two-dimensional heat transfer inside a Silicon on Insulator (SOI) MOSFET and traditional MOS transistor is investigated using the Lattice Boltzmann Method (LBM) . It was found that the temperature reaches 340 K and 332 K for SOI-MOSFET and MOSFET at a Knudsen number (Kn=Λ/Lc) of 10, respectively, while the heat flux reaches 21.5 × 1011 W/m2 for SOI transistor and 18.7 × 1011 W/m2for MOS device. The insulating layer (SiO2)in the SOI transistor restrains heat release in the channel region. So, the conventional MOSFET at Kn =10 is thermally more stable, compared to SOI-MOSFET.

Mobility Extraction in 2D Transition Metal Dichalcogenide Devices-Avoiding Contact Resistance Implicated Overestimation.

Schottky barrier (SB) transistors operate distinctly different from conventional metal-oxide semiconductor field-effect transistors, in a unique way that the gate impacts the carrier injection from the metal source/drain contacts into the channel region. While it has been long recognized that this can have severe implications for device characteristics in the subthreshold region, impacts of contact gating of SB in the on-state of the devices, which affects evaluation of intrinsic channel properties, have been yet comprehensively studied. Due to the fact that contact resistance (RC ) is always gate-dependent in a typical back-gated device structure, the traditional approach of deriving field-effect mobility from the maximum transconductance (gm ) is in principle not correct and can even overestimate the mobility. In addition, an exhibition of two different threshold voltages for the channel and the contact region leads to another layer of complexity in determining the true carrier concentration calculated from Q = COX * (VG -VTH ). Through a detailed experimental analysis, the effect of different effective oxide thicknesses, distinct SB heights, and doping-induced reductions in the SB width are carefully evaluated to gain a better understanding of their impact on important device metrics.