Conventional LFSR Research Articles

A Low Latency and Compact GCD Design Using an Intelligent Seed-Selection Scheme of LL-PRNG

Stochastic computing has shown great promise for a variety of applications, including image processing circuits, due to its design simplicity and low power consumption. This work proposes a hardware efficient and low latency implementation of Greatest Common Divisor (GCD) circuit. It uses a Low Latency Parallel Random Number Generator (LL-PRNG) architecture with an intelligently chosen seed value that eliminates the use of correlators and decorrelators in the circuit, reducing the hardware overhead to a great extent. The proposed approach is compared with the conventional LFSR based design showing reasonable accuracy while the latency in computation greatly reduced. The circuit is evaluated for blind image deconvolution employing GCD and has shown encouraging results.

Fsm Driven NON-Linear Transistion Based Lfsr TPG for Improved Fault Coverage in BIST Application

The Test pattern generator (TPGs) is one of the computationally intensive and performance centric computational block in BIST applications and has been investigated in many existing works to maximize its contribution towards testing the digital circuits; however, design constraints associated to the system leads significant improvements in TPG model. This paper proposes energy efficient FSM state transition-based LFSR TPG to formulate test patterns with maximum length and randomness. Here LFSR generated test patterns generated from conventional LFSR reseeding model with fixed polynomial configuration is decomposed into smaller units and follows FSM encoding to convert into multiple independent test vector blocks. The concatenation of these encoded vector blocks offers improved test vectors which includes transitional and non- transitional encoded values to regulate the overall switching activity. According to the power constrains each binary positions of test vectors are weighted to control certain bit transitions which can significantly optimize the dynamic power consumption during testing process. Finally, FSM controller is used to control state transition in addition to the variable clock to maximize the randomness randomization characteristics of LFSR. Here both clock rate and number state in FSM machine can be dynamically changed to modify the LFSR statistics in accordance with BIST requirements.

Power Optimization by Using Reconfigurable LFSR with Gated Clock

LFSR are the most commonly used test pattern generators due to its efficiency than any binary counters. This paper presents the design of a novel reconfigurable LFSR with clock gating for VLSI testing. The technology advancement in VLSI has increased the complexity of chip testing. This complexity in testing has made the Logic BIST (LBIST) more popular than Automatic Test Equipment. This helps the testing with an additional hardware added inside the circuit. ATE does not apply any test patterns but the test patterns are generated by the testing circuits which are inbuilt in the hardware. Thus the cost of testing is greatly reduced. In the LBIST, reconfigurable LFSR are used for the test pattern generation which improves the fault coverage in IC testing. This increases the generation of random test pattern. To increase the speed of testing and reduce the power required a clock gating is introduced in the reconfigurable LFSR. In traditional testing more transistors are required in the circuits resulting in consumption of more power than power required for the functioning of the circuit. Conventional clock circuit consumes 70% of the clock buffer. This reduces the number of switching activities in the BIST. The power consumption of the proposed reconfigurable LFSR with gated clocking is significantly reduced when compared with the conventional LFSR with clocking circuits.

Area-Efficient Error Detection Structure for Linear Feedback Shift Registers

This paper presents a novel error detection linear feedback shift register (ED-LFSR), which can be used to realize error detection with a small hardware overhead for various applications such as error-correction codes, encryption algorithms and pseudo-random number generation. Although the traditional redundancy methods allow the incorporation of the error detection/correction capability in the original LFSRs, they suffer from a considerable amount of hardware overheads. The proposed ED-LFSR alleviates such problems by employing the parity check technique. The experimental results indicate that the proposed ED-LFSR requires an additional area of only 31.1% compared to that required by the conventional LFSR and it saves 39.1% and 31.9% of the resources compared to the corresponding utilization of the hardware and time redundancy methods.

센서네트워크 활용을 위한 경량 병렬 BCH 디코더 설계

Abstract This paper presents a new byte-wise BCH (4122, 4096, 2) decoder, which treats byte-wise parallel operations so as to enhance itsthroughput. In particular, we evaluate the parallel processing technique for the most time-consuming components such as syndrome gen-erator and Chien search owing to the iterative operations. Even though a syndrome generator is based on the conventional LFSR archi-tecture, it allows eight consecutive bit inputs in parallel and it treats them in a cycle. Thus, it can reduce the number of cycles that areneeded. In addition, a Chien search eliminates the redundant operations to reduce the hardware complexity. The proposed BCH decoderis implemented with VHDL and it is verified using a Xilinx FPGA. From the simulation results, the proposed BCH decoder can enha ncethe throughput as 43% and it can reduce the hardware complexity as 67% compared to its counterpart employing parallel processingarchitecture.Keywords: BCH code, Parallel BCH decoder, Syndrome generator, Chien search

Logic Built-In Self-Test for Core-Based Designs on System-on-a-Chip

A system-on-a-chip (SoC) built with embedded intellectual property (IP) cores offers attractive methodology design reuse, reconfigurability, and customizability. However, the integration of the design-for-testability (DfT) structures of the IP cores in these complex SoCs presents daunting challenges to designers and ultimately affects the time-to-market goals. In this paper, we introduce a design methodology to reduce the time to market by taking core test data from the design environment and automatically generating DfT structures that can easily be integrated into the SoC. A novel automated synthesis methodology to generate an SoC built-in self-test (BIST) to test the IP and custom logic cores is proposed. The proposed technique, i.e., NonExclusive Xor Test of 2D linear feedback shift register (NEXT 2D LFSR), is modeled after the principle of configurable 2D LFSR design, which generates a deterministic sequence of test vectors for random-vector-resistant faults and then random test vectors for random-vector-detectable faults. The basis of this method is to explore the design solution space for optimal 2D LFSR while embedding the test patterns by nonexclusively considering xor gates as the conventional LFSR does but including a simple logic solution for minimal hardware optimization. Moreover, the proposed approach is capable of optimizing the 2D LFSRs with consideration of the don't-care bits in the incompletely specified test patterns.

A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment

A new scan architecture for both low power testing and test volume compression is proposed. For low power test requirements, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the distribution of unspecified bits in the test cubes. In order to optimize the proposed process, a novel graph-based heuristic is proposed to partition the scan chains into several segments. For test volume reduction, a new LFSR reseeding based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, s max, virtually. The performance of a conventional LFSR reseeding scheme highly depends on s max. In this paper, by using different clock phases between an LFSR and scan chains, and grouping the scan cells by a graph-based grouping heuristic, s max could be virtually reduced. In addition, the reduced scan rippling in the proposed test compression scheme can contribute to reduce the test power consumption, while the reuse of some test results as the subsequent test stimulus in the low power testing scheme can reduce the test volume size. Experimental results on the largest ISCAS89 benchmark circuits show that the proposed technique can significantly reduce both the average switching activity and the peak switching activity, and can aggressively reduce the volume of the test data, with little area overhead, compared to the previous methods.

Configurable 2-D Linear Feedback Shift Registers for VLSI Built-in Self-test Designs

Recently a multiple-sequence test generator was presented based on two-dimensional linear feedback shift registers (2-D LFSR). This generator can generate a set of precomputed test vectors obtained by an ATPG tool for detecting random-pattern-resistant faults and particular hard-to-detect faults. In addition, it can generate better random patterns than a conventional LFSR. In this paper we describe an optimized BIST scheme which has a configurable 2-D LFSR structure. Starting from a set of stuck-at faults and a corresponding set of test vectors detecting these faults, the corresponding test pattern generator is determined automatically. A synthesis procedure of designing this test generator is presented. Experimental results show that the hardware overhead is considerably reduced compared with 2-D LFSR generators.

GLFSR-a new test pattern generator for built-in-self-test

A new and effective pseudorandom test pattern generator, termed GLFSR, is introduced. These are linear feedback shift registers (LFSR's) over a Galois field GF(2/sup /spl delta//), (/spl delta/>1). Unlike conventional LFSR's, which are over GF(2), these generators are not equivalent to cellular arrays and are shown to achieve significantly higher fault coverage. Experimental results are presented in this paper depicting that the proposed GLFSR can attain fault coverage equivalent to the LPSR, but with significantly fewer patterns. Specifically, results obtained demonstrate that in combinational circuits, for both stuck-at as well as transition faults, the proposed GLFSR outperforms all conventional pattern generators. Moreover, these experimental results are validated by certain randomness tests which demonstrate that the patterns generated by GLFSR achieve a higher degree of randomless.

Pseudorandom Arrays for Built-In Tests

Parallel pseudorandom sequences for use in built-in test are discussed. The two-dimensional nature of these sequences-makes it natural to consider the resulting binary arrays. Some of the desired properties of such arrays are discussed, as well as some of the problems. Generators for such arrays are described. A conventional LFSR with parallel output is shown to be a poor choice for such a generator. Several compact generators are described, which are shown to be compromises between complexity and varying degrees of implementation of the desired properties in the resulting sequences. One of the compact generators produces sequences which have the desired properties for built-in tests.