Conventional Digital Signal Processing Research Articles

Optical BEAMTAP beam-forming and jammer-nulling system for broadband phased-array antennas

We present an approach to receive-mode broadband beam forming and jammer nulling for large adaptive antenna arrays as well as its efficient and compact optical implementation. This broadband efficient adaptive method for true-time-delay array processing (BEAMTAP) algorithm decreases the number of tapped delay lines required for processing an N-element phased-array antenna from N to only 2, producing an enormous savings in delay-line hardware (especially for large broadband arrays) while still providing the full NM degrees of freedom of a conventional N-element time-delay-and-sum beam former that requires N tapped delay lines with M taps each. This allows the system to adapt fully and optimally to an arbitrarily complex spatiotemporal signal environment that can contain broadband signals of interest, as well as interference sources and narrow-band and broadband jammers--all of which can arrive from arbitrary angles onto an arbitrarily shaped array--thus enabling a variety of applications in radar, sonar, and communication. This algorithm is an excellent match with the capabilities of radio frequency (rf) photonic systems, as it uses a coherent optically modulated fiber-optic feed network, gratings in a photorefractive crystal as adaptive weights, a traveling-wave detector for generating time delay, and an acousto-optic device to control weight adaptation. Because the number of available adaptive coefficients in a photorefractive crystal is as large as 10(9), these photonic systems can adaptively control arbitrarily large one- or two-dimensional antenna arrays that are well beyond the capabilities of conventional rf and real-time digital signal processing techniques or alternative photonic techniques.

DDMPs: self-timed super-pipelined data-driven multimedia processors

This paper describes the world's first commercial data-driven multimedia processors (DDMPs), developed jointly by Osaka University Kochi University of Technology, and Sharp Corporation. The data-driven principle underlying the structure of these processors was realized in a super-pipelined implementation, which was in turn based on a self-timed clocking scheme. This design made it possible to realize single chip DDMPs capable of executing tens of billions of signal processing operations per second with power consumption as low as 2 W. In terms of operations per watt, the processors exhibit threefold to tenfold improvement over conventional sequential digital signal processors (DSPs). The structure of this paper is as follows: 1) a brief introduction to the data-driven processing principle; 2) a detailed description of elementary modules for the realization of self-timed pipeline microprocessors; and 3) a description of the DDMP's developed thus far in the research project, which has continued for more than a decade. Also outlined here are the numerous advantages, in terms of both function and power consumption, of the self-timed pipeline over its synchronous counterparts. Commercially available DSP-oriented asynchronous data-driven processors and their practical applications to consumer appliances such as digital TV receivers are discussed; some programming examples are provided.

Targeted processor architectures for high-performance controller implementation

The requirements for hardware implementation of complex linear time-invariant controllers are addressed. This includes the basic formulation of the equations and their associated numerical properties. Hardware architectures which are directly targeted to these formulations are designed, and their performance is compared with a conventional digital signal processor for a relatively high-end controller task.

Targeted Processor Architectures for High-Performance Controller Implementation

The requirements for hardware implementation of complex linear time-invariant controllers are addressed. This includes the basic formulation of the equations and their associated numerical properties. Hardware architectures which are directly targeted to these formulations are designed, and their performance compared with a conventional digital signal processor for a relatively high-end controller task.

Engine Control using Neural Networks: A New Method in Engine Management Systems

To be able to meet the demands of low emissions and fuel consumption ofmodern combustion engines, new ways have to be found to control thecombustion. We use new sensors to measure the pressure in the combustionchamber and analyze this signal with a neural network in order to receiveseveral form factors which can be used to control the ignition timing. Theneural network is trained off line with measured data and used on line toderive the form factors. The proposed algorithm can be computed in real timeon conventional digital signal processors and adapted to new engines withvery little effort.

Design of a Parallel Processor for Visual Feedback Control Based on the Reconfiguration of Word Length

In the sensor feedback control of intelligent robots, the delay time must be reduced for a large number of multioperand multiply-additions. To reduce the delay time for the multiply-additions, switch circuit is used to change the direct connection between the multipliers and adders, so that the overhead in data transfer is reduced. To change the word-length of the multi-operand multiply-adders, in addition, the switches are also provided in multipliers and adders. By changing to the short wordlength, the numbers of multiplier and adders can be increased. The performance evaluation shows that the delay time for visual feedback control becomes about 6 times faster than that of a parallel processor approach using conventional digital signal processor (DSPs).

Reconfigurable parallel VLSI processor for dynamic control of intelligent robots

In the sensor feedback control of intelligent robots, the delay time must be reduced for a large number of multiply-additions. To reduce the delay time for multi-operand multiply additions, the architecture of the reconfigurable parallel processor is proposed. In each PE, a switch circuit (SC) is used to change the connection between multipliers and adders. By changing the switch elements in the SC using the very-long-instruction-word (VLIW) control method, the multiply-adders having desired numbers of multipliers can be reconfigured every clock cycle. Since the data transfer is performed by the direct connection between multipliers and adders, the overhead for data transfer is greatly reduced. In addition, the utilised ratio of the multipliers and the adders is increased. The chip evaluation based on 0.8 /spl mu/m CMOS design rule shows that the delay time for dynamic control of a seven-degrees-of-freedom (DOF) redundant robot manipulator becomes about 10 /spl mu/s which is about 7.7 times faster than that of a parallel-processor approach using conventional digital signal processors (DSPs).

Digital signal processor supporting two types of instruction sets

AbstractAn architecture for a general purpose digital signal processor has been developed that enables the specification of peripherals and the core part to be easily changed for specific applications. an evaluation chip LSI providing 24‐bit fixed‐point arithmetic was created in order to verify the performance. This digital signal processor (DSP) basically uses RISC‐type architecture in order to simplify the hardware structure and provides two types of instruction sets, called RISC‐type and DSP‐type instructions, to maintain the benefit of the original DSP. the RISC‐type instruction set consists of several types of single‐task operating commands: arithmetic, logical, data transfer, branch, etc. It provides wide operand flexibility. On the other hand, the DSP‐type instruction set consists of parallel operating commands as provided for conventional DSP which execute several data processing and data transfer operations. However, operand flexibility is restricted by providing these two types of instruction sets in one LSI and a higher performance can be achieved than with conventional DSPs which have the same bit length and only one instruction set.

A low complexity video subband coder for ATM

This paper discusses a low complexity, very good visual quality video subband coder fully compatible with ATM networks. The coder is designed to compress an incoming video signal bit-rate by a factor of 9–13 and it is applicable to ‘ Head & Shoulders’ as well as ‘ Full Motion’ sequences. Such results being obtainable in a 17 Mips calculation complexity environment allow the coder implementation on a conventional digital signal processor. The system exploits the characteristics of subband decomposed image through a ‘multiresolution’ quantization methodology. This new resource allocation technique enables the coder to be layered and variable bit-rate. These two properties are essential for optimal use of the coder on a fast packet switching network.

Real time pitch detection using a digital signal processor.

Pitch detection is an essential technique in the various speech processing systems. The pitch period is useful for applications such as the speaker recognition, the speech synthesis and so on. A new frequency-time domain method in order to obtain a fundamental fre quencyof speech is presented in this paper. The paper also describes the results of the computer simulations and a real time pitch period detector using a conventional Digital Signal Processor. The algorithm uses the Discrete Running Fourier Series (DRFS) for emphasis of the peaks of the speech signal corresponding to the pitch and a new simple rule for the determination of the pitch period.

A high‐speed parallel FFT‐processor for a radio astronomy telescope

AbstractA radio astronomy telescope with a wide field of view is an efficient tool for locating such transient radio sources in space as supernova explosions. A promising method of designing this type of telescope is to apply Fourier transformation to the output signals from a phased array antenna. the implementation of a high‐speed parallel FFT processor to an eight‐element linear phased array antenna output is reported in this paper. Small size and low‐power con sumption are achieved by utilizing conventional digital video signal processing LSIs. In the present pilot system, arithmetic operation up to a speed of 2.7 COPS (giga operations per second) has been attained. the basic operation has been confirmed by solar observation.

Coding of Real-Number Sequences for Error Correction: A Digital Signal Processing Problem

Error-correcting codes defined over the real-number and complex-number fields are introduced. The possibility of utilizing realnumber arithmetic permits the codes to be implemented with operations normally available in standard programmable digital signal processors by methods which are discussed. Hadamard and discrete Fourier transform codes are presented for block coding, and the latter are seen to be cyclic and to include the class of BCH codes. It is shown that maximum distance separable real-number BCH ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N, K</tex> ) codes exist for all nontrivial values of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">K</tex> . A large class of block and convolutional real-number single-error-correcting codes, derived from similar codes over <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GF(p)</tex> , are presented. Both block and convolutional codes are seen to be describable by the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">z</tex> -transform in a manner which emphasizes their similarities to conventional digital signal processing structures such as digital filters and digital filter banks. Methods for correcting weight <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t + 1</tex> errors in a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</tex> error-correcting code are demonstrated and interpreted; in particular, the use of a VLSI digital signal processor for implementation of an algorithm for correcting almost all double adjacent error patterns in a single-error-correcting convolutional code is discussed.