Conventional Current Mirror Research Articles

Compensated Current Mirror Neuron Circuits for Linear Charge Integration with Ultralow Static Power in Spiking Neural Networks

For energy‐ and time‐efficient artificial intelligence (AI) computing, implementing hardware‐based spiking neural networks (SNNs) has become a core technology. In SNNs, synaptic devices store weights in memory, and neurons process received weighted information and generate spike signals. Upon feeding spike signals into synaptic arrays, the synaptic weights multiply the signals, which subsequently sum up to perform vector‐matrix multiplication (VMM). Simultaneous access to multiple synaptic devices, however, reduces the equivalent resistance of these synaptic arrays. This reduction alters the voltage division between the pre‐synaptic array and the input resistance of the neuron circuit, distorting the read voltage across synaptic devices. This phenomenon is known as the fan‐in problem, which leads to non‐ideal VMM operations and degrades system accuracy. To address this issue, a novel compensated current mirror (CCM) neuron circuit is proposed, which incorporates a single additional transistor into a conventional current mirror. This CCM neuron achieves exceptional current linearity (R2 > 0.999) and efficiently compensates for VMM error with low complexity and energy consumption (3.33 pJ spike−1). Furthermore, the CCM neuron demonstrates ≈7‐%p higher inference accuracy than conventional ones when integrated with a 512 × 512 large‐scale synaptic array, which is comparable to the accuracy of software‐based SNNs.

Precise method for accuracy and sensitivity improvement of a current mirror for very low current measurement on a dissolved oxygen biosensor

Dissolved oxygen measurements using an electrochemical biosensor and conventional current mirror with accurate results and the desired sensitivity are difficult to achieve, though this type of current mirror is used frequently to processbiosensor signals, providing a good response. However, it exhibits some drawbacks particularly due to mismatched transistors, which will lead to asymmetry between input and output currents. This asymmetry causes unwanted offset and gain error, reducing its accuracy, especially at very low current. A modified current mirror utilizing precise gate voltage adjustment of FETs is applied to match the transistors’ currents. The results show accuracy improvement of the modified current mirror compared to the conventional current mirror, where the improvements provide a very low accuracy error of 0.01%. In addition, the current mirror’s sensitivity can be adjusted by implementing this modification without increasing noise significantly.

Precise realization of one-staged 2-D DCT using analog current mode architecture in compressed sensing front-end

Analog discrete cosine transform (DCT) with CMOS image sensor is an advantageous alternative in low power wireless Compressed Sensing (CS) Systems. The researchers have made some attempts in the recent past behind analog 2D-DCT using switched-capacitor (SC) and current mirror that follow conventional cascaded DCT technique. But these techniques lack accuracy due to capacitor mismatch and circuit-level noises on the DCT symbol. This approach presents a novel algorithm (using product-to-sum method and periodicity of cosine function) to obtain a computational block for current-mode circuit realization of 2D-DCT in a single stage. Cascoded current mirror in the circuit ensures higher accuracy in computation. Rigorous simulation of proposed circuit in SPICE with 65 nm CMOS process showed the supremacy of the architecture. The power consumption can be kept minimal to 12.1 mW for 8*8 2-D DCT during the computation of 64 output symbols using conventional class-AB current mirror. With dynamic biasing strategy, this can be reduced to even less than 3 mW. The circuit simulated DCT symbols were tested in a CS block model at different compression ratios (CR).

A DTMOS-based power efficient recycling folded cascode operational transconductance amplifier

The focus of the present study is on a recycling folded cascode (RFC) operational transconductance amplifier (OTA) in which the transconductance, as well as the slew rate of OTA, are enhanced. RFC OTA, proposed in this study, is employed using a Dynamic Threshold Voltage MOSFET (DTMOS) based differential pair with class AB operation. To achieve class AB operation, an adaptive biasing technique comprising a flip voltage follower is used which boosts the dynamic current and gain-bandwidth product of OTA. Conventional current mirrors are replaced with source degenerated non-linear current mirrors to achieve a better slew rate. The conventional and proposed RFC structures are designed and simulated in a standard 180 nm CMOS process at 1 V supply voltage. The proposed RFC OTA demonstrates a significant enhancement in the performance parameter as 11 dB improvement in the gain as well as 290% more GBW and achieves a slew rate that is nine times better compared to the conventional RFC.

Design of an Ultra-Low Voltage Bias Current Generator Highly Immune to Electromagnetic Interference

The paper deals with the immunity to Electromagnetic Interference (EMI) of the current source for Ultra-Low-Voltage Integrated Circuits (ICs). Based on the properties of IC building blocks, such as the current-splitter and current correlator, a novel current generator is conceived. The proposed solution is suitable to provide currents to ICs operating in the sub-threshold region even in the presence of an electromagnetic polluted environment. The immunity to EMI of the proposed solution is compared with that of a conventional current mirror and evaluated by analytic means and with reference to the 180 nm CMOS technology process. The analysis highlights how the proposed solution generates currents down to nano-ampere intrinsically robust to the Radio Frequency (RF) interference affecting the input of the current generator, differently to what happens to the output current of a conventional mirror under the same conditions.

A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation

We have proposed a current mirror-based level shifter (LS) with a logic error detection (CMLS-LED), which is capable of converting a near-threshold signal to a super-threshold signal. The proposed CMLS-LED resolves the current contention problem observed in the conventional cross-coupled pFET-based LS (CPLS) by using the current mirror and removes the static current in the conventional current mirror LS with adopting the feedback pFET controlled by the output node. Compared with Wilson's current mirror-based LS (WCMLS), CMLS-LED offers an enhanced speed by avoiding the threshold voltage drop of the feedback pFET and is free from the stability issue due to an incomplete output swing. Measurement results obtained from the test chip fabricated with 14-nm finFET technology, in which CMLS-LED is implemented with WCMLS, CPLS, and Osaki's LS, shows that the proposed CMLS-LED can widen the operating voltage range by 200 mV compared wth the CPLS, along with a speed improvement of 80%, when compared to WCMLS.

Design and PVT Analysis of Robust, High Swing Folded Cascode Operational Amplifier

The folded cascode operational amplifier (FCOA) designed in this paper is the single-pole operational amplifier (op amp). In this design, the conventional current mirror is replaced with wide swing current mirror to overcome the essential drawback of cascode configuration. In this paper, negative feedback is used to improve the small-signal gain and to ensure better stability than multistage amplifiers. This paper also aims at improving the output voltage swing, power dissipation and robustness of the op amp. The designed FCOA is proficient in achieving 67.44dB gain and 1.77V output swingat typical voltage for 180nm CMOS technology. The FCOA is highly stable with phase margin of 62.58º while dissipating 0.5mW power. This amplifier is further verified for variability analysis for Process, Voltage and Temperature (PVT) variations to check robustness. All together testing is done at 45 different PVT combinations and results are tabulated accordingly. At each corner temperature and voltage are varied for all together nine combinations to properly address the effect of PVT variations. The results shows that the op amp exhibits desired response at four corners (FF, TT, SS, and FS) of process, over -40º to 125º C temperature range. Also it is capable of operating at very low voltage up to 0.9V adequately showing reduction in power dissipation. Thus the designed op amp is low power, high swing and robust towards process, voltage and temperature variations.

Tunable CMOS Active Inductor Using Widlar Current Source

A novel tuning principle for simple gyrator-based CMOS active inductor (AI) circuit is presented. The method makes use of Widlar current source to enhance the quality factor. The simulation of the proposed AI provides a maximum quality factor of 1819 at 2.88[Formula: see text]GHz. The AI shows the inductive bandwidth of 1.66[Formula: see text]GHz to 3.16[Formula: see text]GHz and power consumption of 6.87[Formula: see text]mW. The other characterization factors such as linearity, supply voltage sensitivity and noise analysis are discussed. The performance of the tunable AI using Widlar current source are compared with the same using a simple current mirror. An AI using a conventional current mirror (CCM) and Widlar current source have been implemented in the 0.18[Formula: see text][Formula: see text]m CMOS technology.

A Design of Low-dropout Regulator with Adaptive Threshold Voltage Technique

In this paper, the characteristics of Low Dropout Regulators to which the adaptive threshold voltage technique was applied were analyzed. For this analysis, fore types of LDO were fabricated. Also Proposed LDO is fabricated in 0.18 um BCD process. The first was a conventional LDO. For the second type of LDO, the adaptive threshold voltage technique was applied to the error AMP and voltage buffer; for the third type of LDO, the adaptive threshold voltage technique was applied to the pass TR and for the fourth type of LDO, the adaptive threshold voltage technique was applied to the error AMP, voltage buffer, and pass TR. The adaptive threshold voltage technique applies a separate voltage to the body terminal of transistor to reduce the threshold voltage (Vth) and increase the drain current. In this paper, the adaptive threshold voltage technique was applied to each block. Then the characteristics and areas of the four types were comparatively analyzed. The area of the current-mirror of the error AMP and voltage buffer proposed in this paper decreased by about 61% compared to the conventional current-mirror. Furthermore, the area of the pass TR proposed in this paper decreased by 5.5% compared to the conventional pass TR and the regulation characteristic of the LDO improved

Low voltage low power FGMOS based current mirror

This paper presents the comparison of a conventional current mirror with the one utilizing floating gate MOSFET transistors (FGMOS) to achieve low power (LP) and low voltage (LV) design. The device structure has been simulated with 0.1μ CMOS technology and 1.2V voltage supply by using SAED 90nm PDK with the Synopsys Custom Designer tool. The FGMOS circuit has shown to have low power consumption of 9.62mW, smaller threshold voltage of 0.2V and Iout of 20 mA. The improvement of 40.1% from conventional current mirror has shown the LV and LP capability of FGMOS transistor.

Design of a New CMOS TRA

A new complementary metal oxide semiconductor transresistance amplifier that is very suitable for high-gain and low-voltage analog application is presented in this paper presents. The designed transresistance amplifier features common-source and gain-boosting topology to improve the gain of the transresistance amplifiers. The complementary metal oxide semiconductor transresistance amplifier provides low input and output impedances, which are required for the design of I-V analog circuits. Conventional common-drain, current-mirror, and common-gate transresistance amplifiers are analyzed through small signal analysis and simulation, and the results are compared with those of the proposed transresistance amplifiers. HSPICE simulation confirmed that the proposed transresistance amplifier has a gain of 83.9 dBΩ and provides higher gain by up to 30.1dBΩ compared to the other transresistance amplifiers.

Bandwidth Extension of High Compliance Current Mirror by Using Compensation Methods

Due to the huge demand of high-speed analog integrated circuits, it is essential to develop a wideband low input impedance current mirror that can be operated at low power supply. In this paper, a novel wideband low voltage high compliance current mirror using low voltage cascode current mirror (LVCCM) as a basic building block is proposed. The resistive compensation and inductive peaking methods have been used to extend the bandwidth of the conventional current mirror. By replacing conventional LVCCM in a high compliance current mirror with the compensated LVCCM, the bandwidth extension ratio of 3.4 has been achieved with no additional DC power dissipation and without affecting its other performances. The circuits are designed in TSMC 0.18 μm CMOS technology on Spectre simulator of Cadence.

LED 구동회로를 위한 새로운 과열방지회로 설계

본 논문에서는 1 <TEX>${\mu}m$</TEX> CMOS 공정을 사용하여 LED 구동회로용 과열방지회로를 제안하였다. 제안하는 과열 방지회로는 <TEX>$120^{\circ}C$</TEX>에서 동작하며 <TEX>$90^{\circ}C$</TEX>에서 차단되도록 설계하였으며, 공정 오차에 따른 과열방지회로의 특성 변화가 많이 감소되었다. 세 가지 공정변화에 따른 특성 변화를 본 결과 제안하는 과열방지회로의 시뮬레이션 결과는 기존의 BJT 전류미러 방식의 과열방지회로보다 공정에 따른 온도변화가 약 7 % 줄어드는 것을 확인하였다. 또한 가상의 LED 구동회로에 연결하였을 때 과열로부터 LED 구동회로를 보호하는 것을 확인하였다. In this paper, we designed a thermal shutdown block for LED applications using a 1 <TEX>${\mu}m$</TEX> CMOS process. The proposed thermal shutdown protection circuit has been designed with a shut-off temperature of <TEX>$120^{\circ}C$</TEX> and a restart temperature of <TEX>$90^{\circ}C$</TEX> which are suitable conditions for LED driver IC. Also, we got SPICE simulation results of the circuit about process variation of the semiconductor fabrication. From simulation data, process variation rate of the proposed circuit are within 7 % which are good results compared with conventional BJT current mirror type circuit. Finally, we confirmed that the thermal shutdown circuit has good thermal protection function within a LED driver IC.

A Novel Current-Scaling a-Si:H TFTs Pixel Electrode Circuit for AM-OLEDs

Hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) pixel electrode circuit with a function of current scaling is proposed for active-matrix organic light-emitting displays (AM-OLEDs). In contrast to the conventional current mirror pixel electrode circuit, in this circuit a high data-to-organic light-emitting device (OLED) current ratio can be achieved, without increasing the a-Si:H TFT size, by using a cascade structure of storage capacitors. Moreover, the proposed circuit can compensate for the variations of TFT threshold voltage. Simulation results, based on a-Si:H TFT and OLED experimental data, showed that a data-to-OLED current ratio larger than 10 and a fast pixel programming time can be accomplished with the proposed circuit.

P-143: A Novel Current-Scaling a-Si:H TFTs Pixel Electrode Circuit for Active-Matrix Organic Light-Emitting Displays

Hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) pixel electrode circuit with a function of current scaling is proposed for active-matrix organic light-emitting displays (AM-OLEDs). In contrast to the conventional current mirror pixel electrode circuit, in this circuit a high data-to-organic light-emitting device (OLED) current ratio can be achieved, without increasing the a-Si:H TFT size, by using a cascade structure of storage capacitors. Moreover, the proposed circuit can compensate for the variations of TFT threshold voltage. Simulation results, based on a-Si:H TFT and OLED experimental data, showed that a data-to-OLED current ratio larger than 10 and a fast pixel programming time can be accomplished with the proposed circuit.

A New Current Scaling Pixel Circuit for AMOLED

A new active-matrix organic light-emitting diode (AMOLED) pixel design, composed of four polycrystalline silicon thin-film transistor (poly-Si TFT) and one capacitor, is proposed by employing a novel current scaling scheme. The simulation results, based on the measured characteristics of an OLED and poly-Si TFTs, show that the proposed pixel design would scale down the data current more effectively, so as to guarantee a lower charging time compared with the conventional current mirror structure, as well as successfully compensate the variation of the electrical characteristics of the poly-Si TFTs, such as the threshold voltage and mobility.

P‐71: OLED Pixel Design Employing a Novel Current Scaling Scheme

AbstractA new active matrix organic light emitting diode (AMOLED) pixel design is proposed by employing a novel current scaling scheme and verified by SPICE simulation. The new pixel design scales down the data current more effectively to guarantee less charging time, compared with conventional current mirror structure, as well as compensates the variation of the electrical characteristics of poly‐Si TFTs, such as threshold voltage and mobility.

Leveraged current mirror op amp

A small change to the standard current mirror op amp configuration is shown to improve performance, with few, if any, disadvantages. Adding a pair of fixed current sources allows reduced operating-point current in the output stage, while the resulting "leveraging" effect increases slew rate. For equal total power dissipation, the new configuration improves DC gain and gain-bandwidth (GBW) over conventional current-mirror and folded cascode op amps, as shown by hand analyses and SPICE simulations. Also, because of increased input stage transconductance, the new configuration reduces thermal and flicker noise.

Very wide range tunable CMOS/bipolar current mirrors with voltage clamped input

In low power current mode signal processing circuits it is often necessary to use current mirrors to replicate and amplify/attenuate current signals and clamp the voltage of nodes with high parasitic capacitances so that the smallest currents do not introduce unacceptable delays. The use of tunable active-input current mirrors would meet both requirements. In conventional active-input current mirrors, stability compensation is required. Furthermore, once stabilized, the input current cannot be made arbitrarily small. In this paper we introduce two new active-input current mirrors that clamp their input node to a given voltage. One of them does not require compensation, while the other may under some circumstances. However, for both, the input current may take any value. The mirrors can operate with their transistors biased in strong inversion, weak inversion, or even as CMOS compatible lateral bipolar devices. If it is biased in weak inversion or as lateral bipolars, the current mirror gain can be tuned over a very wide range. According to the experimental measurements provided in this paper, the input current may spawn beyond nine decades and the current mirror gain can be tuned over 11 decades. As an application example, a sinusoidal g/sub m/-C-based VCO has been fabricated, whose oscillation frequency could be tuned for over seven decades, between 73 mHz and 1 MHz.

Analysis and improvements of accurate dynamic current mirrors

The possibility of realizing highly accurate dynamic current mirrors based on dynamic analog techniques and improvements thereof is considered. These current mirrors, which memorize the input current, are insensitive to transistor mismatch, whereas for conventional current mirrors, the accuracy is limited by the achievable matching. Different current mirror structures are presented, the interfacing parameters are shown, and their influence is explained. The dominant transients occurring during switching are shown. Improvements which allow for increases in the performance of dynamic current mirrors are proposed, and experimental results are shown.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>