Conventional Coordinate Rotation Digital Computer Research Articles

Restrained Latency Universal Modulator Outlay Adaptive CORDIC Algorithm for Digital Communication

Digital communication plays a vital role in today’s communication system in this electronic world. However, the applications of digital communication are limited due to the requirements of antenna with fully programmable circuits having modulators and de-modulators. It may also end with hardware complexities. In order to overcome such complexities, a universal modulator is designed with an efficient iterative method named as CORDIC algorithm in prior methods. Although, the CORDIC (Coordinate Rotation Digital Computer) algorithm works efficiently, it leads to computational as well as memory complexities. Additionally it creates a need for latency reduction strategy. Therefore, to compete with all these issues faced with the prior method, we proposed an amended CORDIC algorithm in universal modulator working with the principle of the harmonized Stone–Weierstrass theorem. In addition, the Newton–Raphson method and Remz algorithm are introduced here to reduce the memory complexity by doubling the number of iterations and to select the best carrier signal, respectively. Thus, our proposed work effectively unravels all the notorious issues caused with the conventional CORDIC algorithm and the proposed universal modulator is implemented in Xilinx.

A Noniterative Radix-8 CORDIC Algorithm with Low Latency and High Efficiency

An efficient, noniterative Radix-8 (NR-8) coordinate rotation digital computer (CORDIC) algorithm is proposed for low-latency and high-efficiency computation of the functions of sine, cosine, or the phase shift, with which the values of the functions are precisely computed by only using the angle in a narrow range of [0, π/12] rather than in a wide angle range of [0, π/2]. This algorithm is expressed by a formula that simplifies the traditional iterative processes by using a complex multiplier. The results obtained from the simulation and the experiment on an FPGA show that the NR-8 CORDIC algorithm operates well, with which the 16-bit precision output is extremely precise, with only 0.012% of the absolute error for computing the sine or cosine function with a step of 0.001°. Compared with the best conventional CORDIC algorithm, the clock latency of this algorithm significantly decreases down to less than 50%, only needs half of the logic resources and consumes half of the power. This algorithm also takes advantages over other newly improved CORDIC algorithms and requires less than half of the clock latency, even for a 23-bit precision output. Therefore, this algorithm could provide a potential application in real-time systems such as radar digital beamforming.

Design of a precise subdivision system for gratings using a modified CORDIC algorithm

The authors have proposed a robust linearisation method for determining the angles of sinusoidal signals generated by gratings. This scheme solves the problem of non-linear subdivision by compensating sinusoidal signal. The conventional coordinate rotation digital computer (CORDIC) algorithm is optimised by double-rotation iteration, and the calculation accuracy of arcsine and arccosine functions is improved. A pipeline preprocessing circuit based on the CORDIC is designed for the signal compensation and digital subdivision. The two processes are implemented on a field-programmable gate array chip, which exhibits a wide input range and good dynamic response. A theoretical analysis using stable signals from a function generator verifies that the subdivision system achieves the ideal subdivision effect. The subdivision system is further applied to an angle-measuring device for a 16,384-line circular grating. The results of subdivision exhibit good linearity for the grating moire signal. Compared to the angular measurement by a laser interferometer within the three grating lines, the angle-measurement accuracy of ±0.000138° (0.5″) and the relative error is ±0.63% over a travel angle of three grating lines. Notably, the measurement error of the subdivision system is only half of that in a similar commercial product (MicroE system).

Configurable Rotation Matrix of Hyperbolic CORDIC for Any Logarithm and Its Inverse computation

In this paper, we propose a configurable rotation matrix for Hyperbolic COordinate Rotation DIgital Computer (CORDIC) to compute any logarithm and inverse logarithm. The rotation matrix of the conventional Hyperbolic CORDIC computes only natural logarithm and natural inverse logarithm whereas the proposed rotation matrix configures the Hyperbolic CORDIC to compute any logarithm and inverse logarithm. Subsequently, an architecture for configurable Hyperbolic CORDIC has been designed based on the proposed rotation matrix. An extensive vector matching is performed to validate the proposed architecture. Finally, an ASIC implementation for configurable Hyperbolic CORDIC has been performed using TSMC 45-nm CMOS technology @ 1 GHz frequency. The accuracy of the proposed configurable Hyperbolic CORDIC is same as conventional Hyperbolic CORDIC. The proposed approach saves 19.22% on chip area and 17.52% power consumption for decimal logarithm computation and 18.55% on chip area and 16.12% power consumption for inverse logarithm computation when compared with the state of the art approaches.

Design of Cascaded CORDIC Based on Precise Analysis of Critical Path

A conventional coordinate rotation digital computer (CORDIC) has a low throughput rate due to its recursive implementation of micro-rotations. On the contrary, a fully-pipelined cascaded CORDIC provides a very high throughput rate at the cost of high complexity and large area. In this paper, possible design choices of cascaded CORDIC are explored over a wide range of operating frequencies, throughput rates, latency, and area complexity. For this purpose, we present a fine-grained critical path analysis of the cascaded CORDIC in terms of bit-level delay. Based on the propagation delay estimate, we propose an algorithm for determining the required number of pipeline stages and locations of the pipeline registers in order to meet the time constraint in a particular application. A hybrid cascaded-recursive CORDIC is also proposed to increase the throughput rate, and to reduce the latency and energy per sample (EPS). From synthesis results, we show that the proposed pipelined cascaded CORDIC with only four pipeline stages requires 31.1% less area and 29.0% less EPS compared to a fully-pipelined CORDIC. An eight stage pipelined recursive cascaded CORDIC provides 18.3% less EPS and 40.4% less area-delay product than a conventional CORDIC.

A Low-Power and High-PSNR Unified DCT/IDCT Architecture Based on EARC and Enhanced Scale Factor Approximation

The Discrete cosine transform (DCT) and inverse Discrete cosine transform (IDCT) have been widely used in image and video compression standards, and more and more researchers focus on the method that taking use of the coordinate rotation digital computer (CORDIC) to execute the DCT and IDCT, the reason is that CORDIC can realize the complex transcendental functions only by using shifters and adders, and is easily suitable implemented in a parallel way. However, the conventional CORDIC has some drawbacks, such as low precision, long iteration number, scale factor and so on. In our previous paper, we have implemented an unified DCT/IDCT based on adaptive recoding CORDIC (ARC) to improve the performance. In this paper, compared with our previous work, we propose an enhanced unified architecture for DCT and IDCT based on the cooperation between the enhanced adaptive recoding coordinate rotation digital computer (EARC) and the conventional CORDIC, in which the radix-2 scale factor approximation proposed in our previous paper is also optimized significantly to achieve better performance in power consumption and PSNR. To conduct a fair competition, the proposed architecture is also validated on a Virtex 5 FPGA platform to evaluate the performance. Under DCT only mode, compared with the Huang and Lee architectures, the proposed architecture at least uses 3.3% less area, dissipates 9% less power at the nearly 2% cost of the critical path delay. Under DCT/IDCT mode, the proposed architecture also saves over 2% hardware resources, reduces more than 5.9% power dissipation when compared to the latest unified DCT/IDCT architectures. Meanwhile, the proposed architecture exceeds the state-of-the-art unified architectures over 0.98 dB in PSNR. Compared with 2S-8P-DCT and 3S-8P-DCT, the proposed unified DCT/IDCT architecture also achieves the best performance in accuracy, processing time and throughput.

RICO: A low power repetitive iteration CORDIC for DSP applications in portable devices

Abstract COordinate Rotation DIgital Computer (CORDIC) is a unit that is widely used in the applications such as scientific calculators, signal/image processing, communication systems, robotics, 3-D graphics etc. exhibits huge computations and requires large power. This paper presents an approximate low power Repetitive Iteration CORDIC (RICO) architecture that calculates sine/cosine values very efficiently. In the proposed RICO, number of iterations are fixed and a specific iteration is repeated to reduce the implementation complexity. An additional comparator based logic that evaluates direction of micro-rotation within RICO reduces the data dependency between each iterations. The efficiency of the proposed RICO is evaluated in Discrete Cosine Transform (DCT) by implementing DCT using only three RICO units. Post-synthesis simulation results show that the proposed RICO achieves area and power savings of 37.19% and 94.05% respectively over the Conventional CORDIC at the cost of 29.39% increase in latency.

An Enhanced Adaptive Recoding Rotation CORDIC

The Conventional Coordinate Rotation Digital Computer (CORDIC) algorithm has been widely used in many applications, particularly in Direct Digital Frequency Synthesizers (DDS) and Fast Fourier Transforms (FFT). However, CORDIC is constrained by the excessive number of iterations, angle data path, and scaling factor compensation. In this article, an enhanced adaptive recoding CORDIC (EARC) is proposed. It uses the enhanced adaptive recoding method to reduce the required iterations and adopts the trigonometric transformation scheme to scale up the rotation angles. Computing sine and cosine is used first to compare the core functionality of EARC with basic CORDIC; then a 16-bit DDS and a 1,024-point FFT based on EARC are evaluated to demonstrate the benefits of EARC in larger applications. All the proposed architectures are validated on a Virtex 5 FPGA development platform. Compared with a commercial implementation of CORDIC, EARC requires 33.3% less hardware resources, provides a twofold speedup, dissipates 70.4% less power, and improves accuracy in terms of the Bit Error Position (BEP). Compared to the state-of-the-art Hybrid CORDIC, EARC reduces latency by 11.1% and consumes 17% less power. Compared with a commercial implementation of DDS, the dissipated power of the proposed DDS is reduced by 27.2%. The proposed DDS improves Spurious-Free Dynamic Range (SFDR) by nearly 7 dBc and dissipates 21.8% less power when compared with a recently published DDS circuit. The FFT based on EARC dissipates a factor of 2.05 less power than the commercial FFT even when choosing the 100% toggle rate for the FFT based on EARC and the 12.5% toggle rate for the commercial FFT. Compared with a recently published FFT, the FFT based on EARC improves Signal-to-Noise Ratio (SNR) by 8.9 dB and consumes 7.78% less power.

Leading One Detection Hyperbolic CORDIC with Enhanced Range of Convergence

This paper focuses on developing an area efficient hyperbolic Coordinate Rotation Digital Computer (CORDIC) algorithm with performance improvement. The algorithm eliminates the need of scale factor calculation in the Range of Convergence (ROC). At the same time the range of convergence offered is higher than the conventional CORDIC ROC in the hyperbolic rotation mode. Being the only kind of algorithm in hyperbolic rotation with sign sequence μ?=?1 always, one complete operation requires just 5 iterations. Thus the pipelined implementation has 5 stages which provides a 50% increase in throughput in comparison to conventional CORDIC. As far as the area improvement is considered, 16-bit processor can be realized using 56% less number of full adders required by Flat-CORDIC. The x and y datapath are based on series expansion of hyperbolic functions. The complete algorithm design along with pipelined architecture implementation is detailed.

Adaptive recoding CORDIC

Conventional Coordinate Rotation Digital Computer (CORDIC) algorithm is an effective implementation of trigonometric function, and it has been widely applied in digital signal processing. In this paper, we propose a novel CORDIC architecture based on Scaling Free (SF) theory, which adopts adaptive recoding method to reduce the iterations and eliminate the scaling factor. The proposed scheme has been synthesized using 65nm CMOS technology with standard cell library. Compared with SFB4C, our scheme saves 21.11% to 34.64% hardware-overhead with no performance penalty.

Highly accurate reduced iteration CORDIC processor algorithm

In this study, we propose a COordinate Rotation Digital Computer (CORDIC) algorithm that gives highly accurate results in fewer iteration counts than previously published methods. The utilisation of a look-up table in the conventional CORDIC algorithm and the usage of the scaling factor is eliminated. The CORDIC algorithm is initiated from the first micro rotation. The accuracy of the micro rotation angle values and the vector coordinate components are improved. The number of iterations is reduced below the level of methods which use look-up tables in their algorithms while maintaining accuracy. In addition, the computation error is greatly reduced with respect to the other algorithms.

Efficient FPGA Realization of CORDIC With Application to Robotic Exploration

We present an area efficient method and field programmable gate array (FPGA) realization for two common operations in robotics, namely, the following: (1) rotating a vector in 2D and (2) aligning a vector in the plane with a specific axis. It is based on a new coordinate rotation digital computer (CORDIC) algorithm that is designed to work with a small set of elementary angles. Unlike conventional CORDIC, the proposed algorithm does not require a ROM and a full-fledged barrel shifter. The proposed CORDIC algorithm is used to design hardware efficient solutions for two mobile robotic tasks in an indoor environment without employing division and floating-point calculations. Experiments with a sole low end FPGA based robot in static as well as dynamic environments validate the power of the approach.

Low Latency Angle Recoding Methods for the Higher Bit-Width Parallel CORDIC Rotator Implementations

In this paper, a low latency angle recoding method for the higher bit-width parallel coordinate rotation digital computer (CORDIC) rotator implementations is proposed. In previous studies, parallel CORDIC (para-CORDIC) rotators have been used to reduce the computational bottleneck by precomputing the required rotation directions. However, the number of required microrotations increases with the bit-width of the input angle, leading to extra stages compared to the conventional CORDIC. To overcome this, our proposed method can obtain a reduced number of microrotations for larger bit-width implementations by recoding two bits of the input angle in the first few area-consuming stages concurrently. This leads to above 21% area/delay reduction compared to previously reported 64-bit para-CORDIC methods. We have implemented our proposed 64-bit para-CORDIC rotator implementations using 0.13- mum CMOS technology, and the operating speed can achieve 250 MHz.

Fixed-Point Error Analysis of CORDIC Arithmetic for Special-Purpose Signal Processors

CORDIC (COordinate Rotation DIgital Computer) is a well known algorithm using simple adders and shifters to evaluate various elementary functions. Thus, CORDIC is suitable for the design of high performance chips using VLSI technology. In this paper, a complete analysis of the computation error of both the (conventional) CORDIC algorithm and the CORDIC algorithm with expanded convergence range is derived to facilitate the design task. The resulting formulas regarding the relative and absolute approximation errors and the truncation error are summarized in the tabular form. As the numerical accuracy of CORDIC processors is determined by the word length of operands and the number of iterations, three reference tables are constructed for the optimal choice of these numbers. These tables can be used to facilitate the design of cost-effective CORDIC processors in terms of areas and performances. In addition, two design examples: singular value decomposition (SVD) and lattice filter for digital signal processing systems are given to demonstrate the goal and benefit of the derived numerical analysis of CORDIC.

Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture

In this paper, we proposed a novel Coordinate Rotation Digital Computer (CORDIC) rotator algorithm that converges to the final target angle by adaptively executing appropriate iteration steps while keeping the scale factor virtually constant and completely predictable. The new feature of our scheme is that, depending on the input angle, the scale factor can assume only two values, viz., 1 and 1//spl radic/2, and it is independent of the number of executed iterations, nature of iterations, and word length. In this algorithm, compared to the conventional CORDIC, a reduction of 50% iteration is achieved on an average without compromising the accuracy. The adaptive selection of the appropriate iteration step is predicted from the binary representation of the target angle, and no further arithmetic computation in the angle approximation datapath is required. The convergence range of the proposed CORDIC rotator is spanned over the entire coordinate space. The new CORDIC rotator requires 22% less adders and 53% less registers compared to that of the conventional CORDIC. The synthesized cell area of the proposed CORDIC rotator core is 0.7 mm/sup 2/ and its power dissipation is 7 mW in IHP in-house 0.25-/spl mu/m BiCMOS technology.

Fixed-Point Error Analysis of CORDIC Processor Based on the Variance Propagation Formula

This paper presents a fixed-point mean-square error (MSE) analysis of coordinate rotation digital computer (CORDIC) processors based on the variance propagation method, whereas the conventional approaches provide only the error bound which results in large discrepancy between the analysis and actual implementation. The MSE analysis is aimed at obtaining a more accurate analysis of digital signal processing systems with CORDIC processor, especially when the design specification is given by the signal-to-noise ratio or MSE. For the MSE analysis, the error source and models are first defined and the output error is derived in terms of MSE in the rotation mode of the conventional CORDIC processor. It is shown that the proposed analysis can also be applied to the modified CORDIC algorithms. As an example of practical application, a fast Fourier transform processor using the CORDIC processor is presented in this paper, and its output error variance is analyzed with respect to the wordlength of CORDIC. The results show a close match between the analysis and simulation.

A UNIDIRECTIONAL CORDIC ALGORITHM FOR ANGL COMPUTATION AND ROTATION

ABSTRACT An innovative approach to CORDIC(Coordinate Rotation Digital Computer) computing is presented. This method features unidirectional rotation, unlike most other more conventional methods, which are bidirectional. A specified angle zo is approached by this method so that the cosz0 and sinz0 are computed. Since no additional hardware components are required to decide the rotation direction for each iteration, the architecture is thus simple, and is expected to be reduced 20% of the area compared with conventional CORDIC techniques. Latency time is also reduced. Although a variable scaling factor should be used, only the first two or three iterations are required because after that, the scaling factor, cosa, approaches 1 as αi<2−8. This method guarantees rapid acceleration toward convergence in one direction during trigonometric function computation.