Conventional Complementary Metal-oxide Semiconductor Technology Research Articles

Memristor-Inspired Digital Logic Circuits and Comparison With 90-/180-nm CMOS Technologies

Compact low-power devices with ultrafast processing speed are the fundamental building blocks for the development of the state-of-the-art logic systems and memristor prominently fulfills these demands and plays a major role in digital circuit design. In this work, design, implementation, and performance evaluation of memristor-based logic gates, such as NOT, AND, NAND, OR, NOR, XOR, and XNOR, and combinational logic circuits, such as adder, subtractor, and 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 1 mux, are presented via SPECTRE in Cadence Virtuoso. Herein, we propose an optimized design of memristor-based logic gates and combinational logic circuits and draw a comparative analysis with the conventional 180-nm complementary metal–oxide–semiconductor (CMOS) technology. The utilized memristor model is thoroughly validated with the experimental results of a high-density Y <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula> O <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{3}}$</tex-math> </inline-formula> -based memristive crossbar array (MCA), which shows a significantly low values of coefficient of variabilities in device-to-device (D2D) and cycle-to-cycle (C2C) operation. The area, power, and delay calculated from these combinational circuits are found to be reduced by more than 71.4%, 40%, and 54%, respectively, as compared to the conventional 180-nm CMOS technology. The impact of multiple CMOS technology nodes (90 and 180 nm) on the power consumption at the chip-level logic circuit implementation has also been investigated. The adopted memristor-based design significantly improves the performance of various logic designs, which makes it area and power efficient and enables a major breakthrough in designing various low-power, low-cost, ultrafast, and compact circuits.

Broadband-Spectral-Responsivity of black silicon photodetector with high gain and sub-bandgap sensitivity by titanium hyperdoping

Silicon, as one of the most essential semiconducting materials, is widely applied in various photodetection applications due to its high portability, convenient preparation, and compatibility with conventional complementary metal–oxide–semiconductor technology. Nowadays, black silicon, prepared by enforcing ultrafast laser micro-structuring and hyperdoping techniques, has received considerable attention for developing next-generation silicon photonics and silicon optoelectronics devices. In this work, high-comprehensive-property black silicon photodetectors with broadband spectral responsivity and high gain were achieved by femtosecond laser irradiation and titanium hyperdoping. The proposed device can respond to the incident light from 400 nm to at least 1550 nm, demonstrating a high responsivity of 40.59 A/W for 950 nm under the application of −5 V bias, and the corresponding detectivity can reach 3.61 × 1012 cm·Hz1/2W−1. Moreover, the fabricated photodetector exhibits a stable sub-bandgap photocurrent at 1550 nm, with an average responsivity of 3.42 mA/W by applying a −5 V bias. These improvements were achieved by the hyperdoping of titanium in silicon, which shows deep impurity levels, low electroactivity, and increased effective carrier lifetimes, as well as the formation of shallow n-i heterojunction and trapping centers induced by the femtosecond laser irradiation. Our work provides significant insights into the applications of black silicon in various optical-related fields, including weak and infrared photon detection, silicon photonic chips, remote sensing, and large-scale optoelectronic integration.

Parallel perception of visual motion using light-tunable memory matrix.

Parallel perception of visual motion is of crucial significance to the development of an intelligent machine vision system. However, implementing in-sensor parallel visual motion perception using conventional complementary metal-oxide semiconductor technology is challenging, because the temporal and spatial information embedded in motion cannot be simultaneously encoded and perceived at the sensory level. Here, we demonstrate the parallel perception of diverse motion modes at the sensor level by exploiting light-tunable memory matrix in a van der Waals (vdW) heterostructure array. The optoelectronic characteristics of gate-tunable photoconductivity and light-tunable memory matrix enable devices in the array to realize simultaneous encoding and processing of incoming spatiotemporal light pattern. Furthermore, we implement a visual motion perceptron with the array capable of deciphering multiple motion parameters in parallel, including direction, velocity, acceleration, and angular velocity. Our work opens up a promising venue for the realization of an intelligent machine vision system based on in-sensor motion perception.

Hybrid CMOS-Memristor based operational transconductance amplifier for high frequency applications

This paper deals with designing an optimized hybrid Operational Transconductance Amplifier (OTA) employing a technique called source degeneration with adaptive biasing that can be used for high frequency applications. This work targets implementation of a simple technique with less number of circuit elements which reduces the die area and power consumption and gives rise to good results. The circuit has been designed to operate with a supply voltage of ±1 V along with a bias current. The linearity which is the major drawback of the conventional Complementary Metal Oxide Semiconductor (CMOS) OTA gets improved with source degeneration technique using a non-CMOS non-volatile memory (so-called memristor). The gain-bandwidth product gets improved for an 80pF load. A biquad OTA-C filter is designed and implemented utilizing the OTA designed in this work as an application example. The realization of a high pass filter has been demonstrated. All the simulations were carried out in the Cadence® Virtuoso environment using 180 nm CMOS technology. Another facet of this paper is the memristor compatibility with the CMOS process technology.

A novel design of nano router with high-speed crossbar scheduler for digital systems in QCA paradigm

PurposeThe nano-router would be a mastery device for providing high-speed data delivery. Here nano-router with a space-efficient crossbar scheduler is used for making absolutely less consumption in power.Design/methodology/approachIn the emerging modern technology, every one of us is expecting a delivery of data at a high speed. To achieve high-speed delivery the authors are using the router. The router used here is at nanoscale reading which provides a compact size.FindingsThis can be implemented using the modern tools called Quantum-dot Cellular Automata (QCA) which is operated without the use of a transistor. As conventional complementary metal oxide semiconductor (CMOS) designs have some limitations such as low density, high power consumption and requirement of a large area.Research limitations/implicationsTo overcome these limitations the QCA is used. It characterizes capability is used to substituting CMOS technology. The round-robin fashion is used in a high-speed space-efficient crossbar scheduler.Practical implicationsThe simulation of the planned circuit with notional information established the practical identity of the scheme.Social implicationsThe proposed nano router can be stimulated in the QCA environment using the QCADesigner tool and the power of the router can be calculated with the QCADesigner–E tool.Originality/valueThe proposed nano router can be stimulated in the QCA environment using the QCADesigner tool and the power of the router can be calculated with the QCADesigner–E tool. In this work, the performance of the router can be done in both the QCA environment and CMOS technology.

Characterization of through-silicon vias using laser terahertz emission microscopy

Three-dimensional (3D) complementary metal–oxide–semiconductor (CMOS) integration could enable device scaling beyond the limits of conventional 2D CMOS technology. Such integration requires vertical electrical connections that pass through silicon substrates and interconnect stacked chips. The fabrication of these through-silicon vias (TSVs) creates new challenges in metrology, including the characterization of the thin isolation film deposited on the sidewalls of the TSVs and thickness characterization for wafer thinning. Here, we show that laser-induced terahertz emission microscopy can be used to characterize TSVs. Terahertz emission is observed through the excitation of a transient electric dipole in the depletion field of the TSV using femtosecond laser pulses. The detected terahertz waveform provides information about the local depletion field and thus structural information about the isolation film. By performing a time-of-flight measurement of the terahertz pulse, we can also extract the silicon wafer thickness. Laser-induced terahertz emission, and time-of-flight measurements of the terahertz pulse, can be used to non-invasively characterize through-silicon vias, which are required for three-dimensional CMOS integration.

Single-photon avalanche diode detectors based on group IV materials

Today there are several types of photodetectors that can cope with the task of detecting a single photon, however, avalanche photodiodes are most widely used for applications in fiber-optic communication systems and quantum cryptography. In the past 5 years experimental fabrication of single-photon avalanche detectors within conventional complementary metal–oxide–semiconductor technology and by the method of molecular beam epitaxy have made possible many demonstrations of avalanche photodetectors with exceptional performance characteristics and opened wide perspectives for development of devices of new generation. In this work, we review state-of-the-art designs of single-photon avalanche photodiodes based on group IV materials, their operating characteristics, and achieved values of basic parameters, as well as the methods of their synthesis, and outline the perspectives of using such structures in emerging device applications.

Reconfigurable logic and neuromorphic circuits based on electrically tunable two-dimensional homojunctions

Reconfigurable logic and neuromorphic devices are crucial for the development of high-performance computing. However, creating reconfigurable devices based on conventional complementary metal–oxide–semiconductor technology is challenging due to the limited field-effect characteristics of the fundamental silicon devices. Here we show that a homojunction device made from two-dimensional tungsten diselenide can exhibit diverse field-effect characteristics controlled by polarity combinations of the gate and drain voltage inputs. These electrically tunable devices can achieve reconfigurable multifunctional logic and neuromorphic capabilities. With the same logic circuit, we demonstrate a 2:1 multiplexer, D-latch and 1-bit full adder and subtractor. These functions exhibit a full-swing output voltage and the same supply and signal voltage, which suggests that the devices could be cascaded to create complex circuits. We also show that synaptic circuits based on only three homojunction devices can achieve reconfigurable spiking-timing-dependent plasticity and pulse-tunable synaptic potentiation or depression characteristics; the same function using complementary metal–oxide–semiconductor devices would require more than ten transistors. A homojunction device made from two-dimensional tungsten diselenide can be used to create circuits that exhibit multifunctional logic and neuromorphic capabilities with simpler designs than conventional silicon-based systems.

Gain Enhancement of Millimeter-Wave On-Chip Antenna Through an Additively Manufactured Functional Package

The antenna-on-chip (AoC) presents an excellent solution for applications requiring higher integration levels and lower cost; however, its radiation performance is poor due to the inherent lossy Si substrate in conventional complementary metal–oxide–semiconductor (CMOS) processes. It is well known that every chip requires a package to protect it from the environment; however, this package does not provide any functionality, despite adding to the cost and required space. In this article, we propose a functional package that has been designed to enhance the gain of the AoC. A 71 GHz coplanar waveguide (CPW)-fed on-chip monopole antenna, driven by a voltage-controlled oscillator (VCO) and frequency doubler, was realized in the standard 0.18 $\mu \text{m}$ CMOS technology. As a first step to enhance its gain, the AoC was designed on top of an artificial magnetic conductor (AMC) surface. Further gain enhancement was achieved by transforming the chip package into a combination of a superstrate layer and a Fresnel lens, qualifying this as a system-on-package (SoP). The package has been realized through additive manufacturing to maintain the low-cost aspect. Overall, the measured gain of the packaged AoC is 6.8 dBi, which has been enhanced by ~20 dBs compared to the unpackaged antenna without an AMC layer.

A comparative study on the effects of technology nodes and logic styles for low power high speed VLSI applications

Carbon nanotubes (CNT) field-effect transistor (CNTFET) could be a possible alternative to CMOS technology for future VLSI applications. In this work, a comparative study has been carried out on the effects of technology nodes and logic styles on power dissipation, delay, leakages, etc. The technology nodes that are considered here are 90 nm and 32 nm MOSFET technology, and 32 nm CNTFET technology. The logic families considered here are the conventional complementary metal-oxide-semiconductor (CMOS), complementary pass transistor logic (CPL) and transmission gate (TG). The digital circuits considered are NAND, NOR, XOR and MUX gates. HSPICE simulations have been carried out and observed that at 32 nm CNTFET technology, the least power, worst-case delay and least PDP are found as 15.5 nW, 3.11 ps and 0.048 aJ, respectively. It is witnessed that CNTFET-based logics are superior compared to other logic families at different technology nodes.

A comparative study on the effects of technology nodes and logic styles for low power high speed VLSI applications

Carbon nanotubes (CNT) field-effect transistor (CNTFET) could be a possible alternative to CMOS technology for future VLSI applications. In this work, a comparative study has been carried out on the effects of technology nodes and logic styles on power dissipation, delay, leakages, etc. The technology nodes that are considered here are 90 nm and 32 nm MOSFET technology, and 32 nm CNTFET technology. The logic families considered here are the conventional complementary metal-oxide-semiconductor (CMOS), complementary pass transistor logic (CPL) and transmission gate (TG). The digital circuits considered are NAND, NOR, XOR and MUX gates. HSPICE simulations have been carried out and observed that at 32 nm CNTFET technology, the least power, worst-case delay and least PDP are found as 15.5 nW, 3.11 ps and 0.048 aJ, respectively. It is witnessed that CNTFET-based logics are superior compared to other logic families at different technology nodes.

An Optimized Counter Design using T Flip-Flop in Quantum-Dot Cellular Automata Technology

Conventional CMOS technology have lot of limitations and serious challenges threat this technology when scaled to a nano-level. Several alternative technologies have been proposed as solutions to overcome limitations and challenges encountered by CMOS. Quantum dot-cellular automata (QCA) is an emerging nanotechnology for the development of logic circuits such as combinational and sequential circuits.QCA seems to be best alternative to the conventional complementary metal-oxide semiconductor (CMOS) technology.QCA is a new computing paradigm in nanotechnology that can implement digital circuits with outstanding features such as ultralow power consumption, faster switching speed and extremely density structure . In this paper , a novel area efficient and optimized QCA layout design of sequential circuit T flip flop is proposed by which the QCA layout area has reduced by 57% , cell count improved by 56% in comparison with the earlier best designs. The use of proposed T flip flop in designing sequential circuits like synchronous 2 bit up counter,3 bit up counter and 4 bit up counter has reduced the QCA layout area by 65%,64% and 68% respectively where as QCA cell count are reduced by 53%, 62% and 59%.. The sequential circuits flip flop and counters are designed using three input XOR gate and are implemented by QCA layout. The paper also present the use of proposed T flip flop designed with 3 input XOR gate in designing not only synchronous binary up counters but also in synchronous binary down counter provides a significant reduction in the hardware and complexity than the existing methods. These circuits are simulated using computer aided design tool QCA Designer 2.0.3, which is a design and simulation tool for quantum dot cellular automata. The aim is to maximize the circuit density and focus on a QCA layout that uses minimal number of cells

Nonvolatile, Spin-Based, and Low-Power Inexact Full Adder Circuits for Computing-in-Memory Image Processing

Deep submicron conventional complementary metal oxide semiconductor (CMOS) technology is facing various issues such as high static power consumption due to the increasing leakage currents. In recent years, spin-based technologies like magnetic tunnel junctions (MTJ) have emerged and shown some fascinating features to overcome the aforesaid issues of CMOS technology. The hybrid MTJ/CMOS circuits offer low power consumption, nonvolatility, and high performance. This paper proposes two novel hybrid MTJ/CMOS approximate full-adder circuits (AXMA) for low power approximate computing-in-memory architectures. The proposed AXMAs offer low area, high sensing speed, considerable lower energy consumption, and the lowest power delay product (PDP) than the considered antecedent counterparts. The proposed AXMAs also introduce the advantage of full nonvolatility to the systems. This feature allows the system to be powered off during the idle modes in order to reduce the static power without the need for any retention parts or loss of data. Applications of the proposed AXMAs in digital image processing and their effect on the quality of images considering some relevant metrics like peak signal-to-noise ratio (PSNR) and mean structural similarity (MSSIM) are also investigated using the MATLAB software.

Resistive random-access memory with an a-Si/SiNx double-layer

Resistive random-access memory (RRAM) with a Ni/SiNx/a-Si/p+-Si structure is presented. In contrast to RRAM devices based on high-k materials, the proposed Si-based device is more attractive and promising because the SiNx and a-Si layers have full compatibility with conventional complementary metal-oxidesemiconductor technology. The proposed device is compared to a control device with a single layer of SiNx. A conduction path containing Si dangling bonds (traps) can be generated in both the SiNx and a-Si layers. The conduction path in each layer can be controlled by the compliance current during the forming process. For high compliance current mode, the double-layer device has a higher ON/OFF ratio (∼104) and lower leakage current (∼10-9 A) than the single-layer device. For low compliance current mode, better non-linearity (∼103) can be obtained when a 1/2 read bias scheme is applied to the cross-point array.

New efficient designs of reversible logic gates and circuits in the QCA technology

Quantum-dot cellular automata (QCA) is a developing nanotechnology, which seems to be a good candidate to replace the conventional complementary metal-oxide-semiconductor (CMOS) technology. The QCA has the advantages of very low power dissipation, faster switching speed, and extremely low circuit area, which can be used in designing nanoscale reversible circuits. In this paper, the new efficient QCA implementations of the basic reversible Gates such as: CNOT, Toffoli, Feynman, Double Feynman, Fredkin, Peres, MCL, and R Gates are presented based on the straight interactions between the QCA cells. Also, the designs of 4-Bit reversible parity checker and 3-bit reversible binary to Grey converter are introduced using these optimized reversible Gates. The proposed layouts are designed and simulated using QCADesigner software. In comparison with previous QCA designs, the proposed layouts are implemented with the minimum area, minimum number of cells, and minimum delay without any wire-crossing techniques. Also, in comparison with the CMOS technology, the proposed layouts are more efficient in terms of the area and power. Therefore, our designs can be used to realize quantum computation in ultralow power computer communication.

Fully Nonvolatile and Low Power Full Adder Based on Spin Transfer Torque Magnetic Tunnel Junction With Spin-Hall Effect Assistance

As technology node scales down below 90 nm, the conventional complementary metal oxide semiconductor (CMOS) logic circuits suffer from various problems such as high standby power due to increase in leakage current. Spintronic devices based on magnetic tunnel junction (MTJ) is one of the most promising technology candidates for the future of the digital circuits. MTJ-based logic circuits can offer nonvolatility, high endurance, high density, low standby power dissipation, and 3-D integration capability with the CMOS technology. In recent years, several full-adder circuits are proposed based on MTJs that are not fully nonvolatile since they use MTJs to store only one of their inputs. This paper proposes a fully nonvolatile magnetic full-adder (MFA) circuit offering the capability of power gating with no loss of data. The proposed circuit stores all the inputs in MTJs using the spin-transfer torque (STT) method assisted by the spin-Hall effect (SHE). Thanks to the SHE assistance, delay and power consumption of the MTJ switching are reduced significantly. Moreover, as a result of lower write current, the endurance of the oxide barrier can be increased. Using a three-terminal SHE–STT–MTJ model and a 45 nm CMOS SPICE model, we simulated and validated the functionality of our design and compared it with some recent previous MFAs. Simulation results reveal that the proposed MFA offers considerable superiorities over the recent counterparts.

Silicon nanowire CMOS NOR logic gates featuring one-volt operation on bendable substrates

In this study, we propose complementary metal-oxide−semiconductor (CMOS) NOR logic gates consisting of silicon nanowire (NW) arrays on bendable substrates. A circuit consisting of two p-channel NW field-effect transistors (NWFETs) in series and two n-channel NWFETs in parallel is constructed to operate a two-input CMOS NOR logic gate. The NOR logic gates operate at a low supply voltage of 1 V with a rail-to-rail logic swing and a high voltage gain of approximately −3.0. The exact NOR logic functionality is achieved owing to the superior electrical characteristics of the well-aligned p- and n-NWFETs, which are obtained using conventional Si-based CMOS technology. Moreover, the NOR logic gates exhibit stable characteristics and have good mechanical properties. The proposed bendable NW CMOS NOR logic gates are promising building blocks for future bendable integrated electronics.

Post-layout simulation of an ultra-low-power OTA using DTMOS input differential pair

ABSTRACTIn this paper, an ultra-low-power dynamic threshold voltage metal-oxide-semiconductor (DTMOS) amplifier is presented. In order to have a high open-loop gain and keep power consumption as low as possible, DTMOS differential pair at input stage technique has been used to improve the specifications of a conventional complementary metal-oxide-semiconductor (CMOS) amplifier such as power supply voltage and power consumption with a proper open-loop gain and unity gain bandwidth. The gain-stage compensation method has been used to overcome the stability problem. The proposed amplifier has been successfully validated and verified in TSMC 0.18 µm CMOS technology and post-layout simulated with Cadence Virtuoso. The post-layout simulation results show that the proposed operational transconductance amplifier (OTA) has 82.77 dB open-loop gain and total power consumption is about 163 nW with 0.4 V voltage supply which is suitable for low-power applications. In the final section in order to evaluate the OTA prefabrication performances, Monte Carlo and corner processes analysis have been performed. Acceptable output swing of 0.37 V is one of the additional features of the proposed OTA.

Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications

To allow fast communication—at several Gb/s—of multimedia content among processors and memories in a multi-processor system-on-chip, a new approach is emerging in literature: Wireless Network-on-Chip (WiNoC). With reference to this scenario, this paper presents the design of the key element of the WiNoC: the antenna. Specifically, a bow-tie antenna is proposed, which operates at mm-waves and can be implemented on-chip using the top metal layer of a conventional silicon CMOS (Complementary Metal Oxide Semiconductor) technology. The antenna performance is discussed in the paper and is compared to the state-of-the-art, including the zig-zag antenna topology that is typically used in literature as a reference for WiNoC. The proposed bow-tie antenna design for WiNoC stands out for its good trade-off among bandwidth, gain, size and beamwidth vs. the state-of-the-art.

Double gate symmetric tunnel FET: investigation and analysis

In this work, using calibrated 2D simulations, the authors first demonstrate that the OFF-state current and subthreshold swing (SS) are significantly high for the double gate Ge source/drain symmetric p-n-p tunnel field effect transistor (TFET) with a silicon channel without n + pockets at the source- and drain-channel interfaces. They further establish that using $n^{+}$n+ pockets at the source- and drain-channel interface, the Ge source/drain symmetric p-n-p TFET exhibits a 130 times improvement in I ON / I OFF ratio and a 26% reduction in SS due to the two orders of magnitude reduction in its OFF-state current when compared with the one without the n + pockets. The results also indicate that the Ge source/drain symmetric p-n-p TFET suffers from a low output conductance at low drain voltages. Since the proposed device exhibits bidirectional current flow, it can be easily integrated with the conventional complementary metal-oxide semiconductor technology.