Conventional Clock And Data Recovery Research Articles

Secondary Side-Channel Wireline Communication Using Transmitter Clock Frequency Modulation

A secondary communication link, or side-channel, is proposed, which uses binary frequency shift keying to modulate the frequency of a high-speed wireline transmitter clock. This side-channel data is then received using the corresponding receiver’s conventional clock and data recovery (CDR) circuit. An analysis of the CDR loop parameters demonstrates that, within certain limits, the side-channel does not impact the signal integrity of the primary high-speed data. Measurements were made on a side-channel prototype using a 56-Gb/s PAM-4 (half-rate 14-GHz clock) transceiver in 7-nm FinFET technology through a 15-dB loss channel. Over 104 side-channel bits were transmitted at 50 kb/s, and the side-channel remained error-free with no visible impact on the high-speed link.

A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition

A continuous-rate digital clock and data recovery (CDR) with automatic frequency acquisition is presented. The proposed automatic frequency acquisition scheme implemented using a conventional bang–bang phase detector (BBPD) requires minimum additional hardware, is immune to input data transition density, and is applicable to subrate CDRs. A ring-oscillator-based two-stage fractional-N phase-locked loop (PLL) is used as a digitally controlled oscillator (DCO) to achieve wide frequency range, low noise, and to decouple the tradeoff between jitter transfer (JTRAN) bandwidth and ring oscillator noise suppression in conventional CDRs. The CDR is implemented using a digital D/PLL architecture to decouple JTRAN bandwidth from jitter tolerance (JTOL) corner frequency, eliminate jitter peaking, and remove JTRAN dependence on BBPD gain. Fabricated in a 65 nm CMOS process, the prototype CDR achieves error-free operation (BER ${\rm{ ) from 4 to 10.5 Gb/s with pseudorandom binary sequence (PRBS) data sequences ranging from PRBS7 to PRBS31. The proposed automatic frequency acquisition scheme always locks the CDR loop within 1000 ppm residual frequency error in worst case. At 10 Gb/s, the CDR consumes 22.5 ${\rm{\,mW}}$ power and achieves a recovered clock long-term jitter of 2.2 ${\rm ps_{rms}}$ /24.0 ${\rm{ ps_{pp}}}$ with PRBS31 input data. The measured JTRAN bandwidth and JTOL corner frequencies are 0.2 and 9 MHz, respectively.

A Study on Fully Digital Clock Data Recovery Utilizing Time to Digital Converter

Conventional clock and data recovery (CDR) using a phase locked loop (PLL) suffers from problems such as long lock time, low frequency acquisition and harmonic locking. Consequently, a CDR system using a time to digital converter (TDC) is proposed. The CDR consists of simple arithmetic calculation and a TDC, allowing a fully digital realization. In addition, utilizing a TDC also allows the CDR to have a very wide frequency acquisition range. However, deterministic jitter is caused with each sample, because the system's sampling time period is changing slightly at each data edge. The proposed system does not minimize jitter, but it tolerates small jitter. Therefore, the system offers a faster lock time and a smaller sampling error. This proposed system has been verified on system level in a Verilog-A environment. The proposed method achieves faster locking within just a few data bits. The peak to peak jitter of the recovered clock is 60 ps and the RMS jitter of the recovered clock is 30 ps, assuming that the TDC resolution is 10 ps. In applications where a small jitter error can be tolerated, the proposed CDR offers the advantage of fast locking time and a small sampling error.

A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-<tex>$muhbox m$</tex>CMOS

A clock and data recovery (CDR) architecture featuring a parallel phase detector is proposed for speeding up linear-type CDRs. A cause of speed limit in conventional CDRs is very short UP pulses in its phase detector circuit. The parallel phase detector expands UP pulsewidth by adding fixed-width using a half-rate clock. The parallel phase detector is used in the CDR with a couple of unbalanced charge-pump. The bandwidth of decision latches of the PD is extended by 1.7 times by using both shunt-peaking and capacitance coupling. The monolithic CDR implemented in 0.13-mum CMOS shows 1.7 times wider phase linear response region of 0.56UI than that of a conventional CDR. It operates at 12.5-Gb/s with PRBS 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> -1 input data. Measurements show large jitter tolerance of over 0.5 UIpp for 4-8 MHz jitter frequency as well as jitter transfer characteristics independent on input-jitter amplitudes of 0.1, 0.3, and 0.5 UIpp