Conventional Carrier-based Pulse Width Modulation Research Articles

XTMS: A Pulse Generator for Exploring Transcranial Magnetic Stimulation Therapies.

A cascaded H-bridge based pulse generator for transcranial magnetic stimulation is introduced. The system demonstrates complete flexibility for producing different shape, duration, direction, and rate of repetition of stimulus pulses within its electrical limits, and can emulate all commercial and research systems available to-date in this application space. An offline model predictive control algorithm, used to generate pulses and sequences, shows superior performance compared to conventional carrier-based pulse width modulation. A fully functioning laboratory prototype delivers up to 1.5 kV, 6 kA pulses, and is ready to be used as a research tool for the exploration of transcranial magnetic stimulation therapies by leveraging the many degrees-of-freedom offered by the design.

A Carrier-Based Discontinuous PWM Strategy of NPC Three-Level Inverter for Common-Mode Voltage and Switching Loss Reduction

For the conventional carrier-based pulse width modulation (CBPWM) strategies of neutral point clamped (NPC) three-level inverters, the higher common-mode voltage (CMV) is a major drawback. However, with CMV suppression strategies, the switching loss is relatively high. In order to solve the above issue, a carrier-based discontinuous PWM (DPWM) strategy for NPC three-level inverter is proposed in this paper. Firstly, the reference voltage is modified by the twice injection of zero-sequence voltage. Switching states of the three-phase are clamped alternatively to reduce both the CMV and the switching loss. Secondly, the carriers are also modified by the phase opposite disposition of the upper and lower carriers. The extra switching at the border of two adjacent regions in the space vector diagram is reduced. Meanwhile, a neutral-point voltage (NPV) control method is also presented. The duty cycle of the switching state that affects the NPV is adjusted to obtain the balance control of the NPV. Still, the switching sequence in each carrier period remains the same. Finally, the feasibility and effectiveness of the proposed DPWM strategy are tested on a rapid control prototype platform based on RT-Lab.

Real time simulation of reduced switch multilevel inverter with PWM switching sequence control

<span lang="EN-US">Reduction of switch count in symmetrical and asymmetrical reduced switch multilevel inverter designs has been proposed regularly with operation of conventional carrier-based pulse width modulation technique. In this study, a novel structure of symmetrical Hexa shaped model reduced switch seven level output inverter is proposed without any auxiliary switch and H-bridge. Proposed structure offers a smaller number of switch count and voltage sources which results in the cost and complexity reduction of its implementation. To operate the switching sequence of inverter from carrier based APOD, POD and PD methods, suitable logical expression to be realize which gained more prominence. Active utilization of two voltage sources in each mode of operation results in significant reduction of voltage stress across each switch is achieved. A comparative study of proposed MLI with various reduced switch MLIs has been presented. Initially, simulation model implementation has been carried out with MATLAB/Simulink and observed the performance parameters and THD. Simulation results are carried for the comparison of the results obtained in the real time work performed on OPAL-RT 5700 simulator</span><span lang="EN-US">.</span>

Simultaneous Switching Loss Reduction and Neutral-Point Voltage Balance Scheme for Single-Phase Three-Level T-Type Inverter

Single-phase three-level T-type inverter (3LT <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> I) has revealed superior performances in many applications. However, it inevitably faces the challenge of high switching loss and imbalanced neutral-point voltage with conventional carrier based pulsewidth modulation (CBPWM). To address these issues, an improved CBPWM strategy with maximum offset voltage injection is proposed to reduce the switching loss and balance the neutral voltage simultaneously. Neutral-point voltage balance is maintained by selecting P-type or N-type switching sequence, which depends on the sign of offset voltage. Also, switching loss is mitigated by reducing the number of total switching commutation. First, the restriction of injected offset voltage is investigated and when the offset voltage is maximum, the switching commutation is reduced. Then, to further reduce the number of switching commutation, a new set of carrier signals are proposed to realize zero switching commutation between P-type and N-type switching sequences. After the analysis, the proposed modulation method also has better common-mode voltage restriction and faster response of neutral-point voltage balance. Simulation and experiment have been conducted to verify the theoretical analysis.

Band-Limited Three-Level Modulation for Balancing Capacitor Voltages in Neutral-Point-Clamped Converters

In this article, a band-limited three-level modulation scheme is proposed for a three-phase neutral-point-clamped (NPC) converter with an aim to balance the average capacitor voltages under all operating conditions. When conventional carrier-based pulsewidth modulation is applied, the amplitude of neutral point (NP)-voltage ripple tends to increase under linear imbalances, while the NP voltage can shift, leading to instability in the presence of nonlinear loads. A previously proposed three-level modulation scheme was able to eliminate all low-frequency capacitor voltage ripple by switching a phase between three levels in each switching period. This approach significantly increased the switching loss. The proposed modulation scheme limits the increase in switching loss by employing two operational bands, one fixed band applied to the capacitor voltages and another variable band applied to the phase currents. If the instantaneous capacitor voltages exceed the voltage band, then an appropriate phase-leg is switched in three levels to guarantee that the capacitor voltages cannot diverge further. If the instantaneous capacitor voltages reside within the voltage band, a variable current band is used to regulate switching in three voltage levels in order to obtain lower switching losses as compared to the conventional three-level modulation scheme. Therefore, the proposed modulation scheme presents a tradeoff between switching losses and capacitor voltage ripple. The experimental results are obtained under different loading conditions for validating the performance of the proposed modulation scheme.

Feedforward Proportional Carrier-Based PWM for Cascaded H-Bridge PV Inverter

In this paper, a feedforward proportional carrier-based pulsewidth modulation (PWM) is proposed for the dc link control of the single-phase cascaded H-bridge multilevel photovoltaic inverter. The conventional carrier-based PWM techniques, such as the phase-shifted PWM and the level-shifted PWM, require multiple individual dc voltage controllers for the individual maximum power point tracking (MPPT). Thus, the control structure and the controllers’ designs are quite complex. Several noncarrier-based PWM techniques, such as the feedforward space vector modulation, the sorting-algorithm-based modulation, and the lookup table-based modulation, have the capability of individual dc voltage regulation. Although these noncarrier-based PWM techniques require only one total dc voltage controller in the outer voltage loop, the implementations of them are much more complicated than those of the carrier-based PWM techniques. In this paper, with the proposed feedforward proportional carrier-based PWM, each individual modulation signal is directly generated by multiplying the current loop controller’s output and the modulation signal’s feedforward proportional factor. With the feedforward PWM and the total dc voltage control, the individual dc voltage regulation is achieved. This carrier-based PWM combines the strengths of both the traditional carrier-based PWM and the noncarrier-based PWM. It is not only easy for implementation, but also requires only one total dc voltage controller in the outer voltage loop. The detailed description, derivation, and analysis of this modulation are included in this paper. In addition, the simulations and experiments demonstrate the performance of the dc link control and the individual MPPT using the proposed PWM and the control strategy.

Reduced carrier PWM scheme with unified logical expressions for reduced switch count multilevel inverters

The significant reduction in switch count of symmetrical/asymmetrical reduced switch count multilevel inverters (RSC-MLI) topologies has modified the operation of inverter such that the conventional carrier-based pulse width modulation (PWM) schemes such as level-shifted PWM and phase-shifted PWM can no more realise them. To control these RSC-MLI topologies, reduced carrier PWM schemes with modified switching logic gained more prominence. These schemes involve suitable logical expressions to realise the switching states of the inverter. However, these logical expressions vary with topological arrangement and number of levels. Moreover, these schemes produce high total harmonic distortion (THD) in line-voltages. Therefore, to improve the line-voltage THD and generalise the switching logic, a modified reduced carrier PWM scheme with unified logical expressions is presented here. The proposed PWM scheme is directly valid for any topology and can be easily scalable to any number of levels in the inverters. To validate the implementation of the proposed PWM to control any RSC-MLI, experimental studies of various asymmetrical RSC-MLI topologies with the proposed PWM scheme are carried out. Further, to verify the superiority of the proposed scheme in terms of THD, complexity, scalability, and computation burden, its performance is compared with carrier-based PWM schemes reported in the literature.

A Modified Phase Disposition Pulse Width Modulation to Suppress the Leakage Current for the Transformerless Cascaded H-Bridge Inverters

Transformerless cascaded H-bridge inverters have the advantages of low cost and high efficiency in low-power applications. However, the leakage currents resulting from the parasitic capacitors may increase system losses, electromagnetic interference, and safety concerns. To reduce the leakage current, this paper first establishes the equivalent common-mode circuit of the inverter with the parasitic capacitance and analyzes the characteristics of leakage current in the symmetrical and asymmetrical filter inductance circuit, respectively. The analysis shows that the traditional phase disposition pulse width modulation or phase-shift pulse width modulation cannot solve the leakage current issues, but modifying the modulation methods can eliminate the system leakage current in the symmetrical circuit, and it has a little effect in the asymmetrical circuit. For this reason, a modified phase disposition pulse width modulation for the symmetrical circuit, which can eliminate the leakage current effectively with simple implementation, is proposed. Simulation and experimental results are reported, along with evaluation and comparison results, against a conventional carrier-based pulse width modulation method.

Finite control set predictive control of shunt hybrid power filter

ABSTRACTThis paper proposes a finite control set predictive control (FCS-PC) scheme for the shunt hybrid power filter (SHPF) to reduce the power loss while maintaining satisfactory power quality at the utility’s grid terminals. By means of the instantaneous power theory, the controller for the proposed method can generate the reference voltage for the SHPF voltage source inverter (VSI) for the future sampling time. Therefore, during a sampling time, the vector of the reference voltage is compared with the finite number of voltage vectors existent in the VSI to select the vector that best fits the cost function of the controller. The proposed method, compared with the conventional pulse width modulation (PWM) carrier method, has the capability of suppressing similarly the harmonic currents at grid terminals and controlling VSI DC-link voltage while maintaining low switching frequencies in the devices. This method shows simplicity in digital implementation because it does not need a PWM block to obtain the VSI gating signals. In addition, a comparison of the proposed FCS-PC method with the conventional carrier-based PWM method is presented and discussed. Parameter errors in the controller are studied and their effects on system performance are explained. The effectiveness of the proposed method is demonstrated with simulation and experimental results during steady-state operation and transient response of the system.

Closed-Loop Discontinuous Modulation Technique for Capacitor Voltage Ripples and Switching Losses Reduction in Modular Multilevel Converters

In this paper, a new discontinuous modulation technique is presented for the operation of the modular multilevel converter (MMC). The modulation technique is based on adding a zero sequence to the original modulation signals so that the MMC arms are clamped to the upper or lower terminals of the dc-link bus. The clamping intervals are controlled according to the absolute value of the output current to minimize the switching losses of the MMC. A significant reduction in the capacitor voltage ripples is achieved, especially when operating with low modulation indices. Furthermore, a circulating current control strategy suitable for this modulation technique is also proposed. Simulation and experimental results under various operating points are reported along with evaluation and comparison results against a conventional carrier-based pulse width modulation method.

A Carrier-Based PWM Technique for Capacitor Voltage Balancing of Single-Phase Three-Level Neutral-Point-Clamped Converters

In this paper, a pulsewidth-modulation (PWM) technique with neutral point capacitor voltage balancing in single-phase neutral-point-clamped converters is presented. The technique is based on the injection of a common-mode voltage signal into the sinusoidal modulating signals of the conventional carrier-based PWM. Although several strategies have been reported for such a problem by using the voltage signal injection, the proposed method is very simple with easy implementation. A set of equations is presented to demonstrate how the injected voltage signal introduces a dc component on the neutral-point current, which can be controlled in order to allow the capacitor voltages balancing.

A Carrier-Based PWM Strategy With the Offset Voltage Injection for Single-Phase Three-Level Neutral-Point-Clamped Converters

Single-phase three-level neutral point clamped (NPC) converters are widely applied in high-speed railway electrical traction drive systems. A significant problem related to the single-phase three-level NPC converters is the fluctuation of the neutral-point voltage. In this paper, a capacitor voltage balancing technique is proposed that injects an offset voltage into the sinusoidal modulating signals of the conventional carrier-based pulsewidth modulation (CBPWM) method. Furthermore, when the injected offset voltage is maximized, it cannot only balance the dc-link capacitors voltages, but also reduce switching losses. Theoretical analysis has shown that both methods can control the neutral point voltage effectively, but the neutral point voltage controller in the CBPWM with maximum offset voltage injection (CBPWM-MOVI) has a faster dynamic response. It was observed that the high-order harmonics frequencies of the line current are centered around the twice switching frequency in the CBPWM with the offset voltage injection (CBPWM-OVI) but are centered around the switching frequency in the CBPWM-MOVI. And also, the CBPWM-MOVI has switching commutations number at least 25% below that of the CBPWM-OVI in one modulating signal period. The performances of the two strategies were verified by simulation and experimental tests.

Current-fed three-phase and voltage-fed three-phase active converters with optimum PWM pattern scheme and their performance evaluations

This paper describes a new approach to select the optimum sinewave pulsewidth modulation (PWM) patterns suitable for a large-capacity current-fed active PWM power converter and a practical design procedure to determine circuit constants of a low-pass filter connected to suppress higher line current harmonics flowing into the utility-grid AC power source. A feasible test is implemented by building a prototype 500 kW three-phase current-fed PWM power converter which is designed and controlled on the basis of the proposed considerations. It is verified from a practical point of view that these new conceptual considerations are more effective and acceptable to minimize higher harmonic current components flowing into the utility-grid AC power source. This experimental setup provides highly efficient steady-state characteristics of the current-fed three-phase PWM power converter under the operating condition of a unity power factor correction and sinewave line current shaping schemes. Furthermore, this unique optimum PWM pattern derived from the theoretical method proposed here is conveniently applicable to a voltage-fed three-phase PWM converter. It is verified that this optimum PWM pattern provides excellent switching performance with a lower switching frequency mode than the conventional carrier-based PWM scheme.