Conventional CNTFET Research Articles

A Study on the Design Method of Hybrid MOSFET-CNTFET Based SRAM – A Secondary Publication

More than 10,000 carbon nanotube field-effect transistors (CNTFETs) have been successfully integratedinto one semiconductor chip using conventional semiconductor design procedures and manufacturing processes. Thesetransistors offer advantages such as high carrier mobility, large saturation velocity, low intrinsic capacitance, flexibility, andtransparency. The three-dimensional multilayer structure of the CNTFET semiconductor chip, along with ongoing researchin CNTFET manufacturing processes, increases the potential for creating a hybrid MOSFET-CNTFET semiconductorchip. This chip combines conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) and CNTFETs inone integrated system. This paper discusses a methodology to design 6T binary static random-access memory (SRAM)using a hybrid MOSFET-CNTFET. This paper introduces a method for designing a hybrid MOSFET-CNTFET SRAMby leveraging existing MOSFET SRAM or CNTFET SRAM design approaches. Additionally, this paper compares itsperformance with conventional MOSFET SRAM and CNTFET SRAM designs.

Energy efficient design of unbalanced ternary logic gates and arithmetic circuits using CNTFET

The emergence of multi-valued logic (MVL) is a substitute to binary logic approaches for realizing high-information density logic systems and high-operating speed systems. In this paper, a design for standard ternary inverter (STI), ternary NAND (TNAND), ternary NOR (TNOR) using carbon nanotube field effect transistors (CNTFETs) is proposed in which a p-type dynamic diode is used with the goal of lowering the energy consumption expressed as power delay product (PDP) and thereby reducing battery usage. Additionally, the basic arithmetic operations are then performed using proposed ternary logic circuits, which can be extended to realize more complex operations. The proposed designs are simulated in HSPICE using a 32 nm Stanford CNTFET model. With respect to variation in process parameters, the reliability of the proposed STI circuit is examined. Simulation results verify that the proposed designs show improvement in terms of power consumption and power delay product (PDP) compared to the other CNTFET based ternary logic circuits. Moreover, less variations are observed in power and PDP of the proposed logic gates with variation in process parameters, capacitance, temperature, frequency and supply voltage. The proposed circuit designs of STI, TNAND, TNOR, ternary half adder (THA), ternary multiplier (TMUL) show 78 %, 98 %, 99 %, 99 %, 99 % improvement in PDP respectively, as compared to the conventional CNTFET based circuit designs and 99 % PDP improvement in all proposed circuits compared to CNTFET based logic circuits with resistive load.

Semiconducting SWCNT Photo Detector for High Speed Switching Through Single Halo Doping

The method opted for accuracy, and no existing studies are based on this method. A design and characteristic survey of a new small band gap semiconducting Single Wall Carbon Nano Tube (SWCNT) Field Effect Transistor as a photodetector is carried out. In the proposed device, better performance is achieved by increasing the diameter and introducing a new single halo (SH) doping in the channel length of the CNTFET device. This paper is a study and analysis of the performance of a Carbon Nano Tube Field Effect Transistor (CNTFET) as a photodetector using the self-consistent Poisson and Green function method. The 2D self-consistent Poisson and Green’s function method for various optical intensities and wavelength simulate this proposed photodetector. The performance study is based on the simulation of drain current, transconductance, sub-threshold swing, cut-off frequency, gain, directivity, and quantum efficiency under dark and illuminated conditions. These quantum simulation results show that cut-off frequency increases while there is an increase in diameter. The proposed SH-CNTFET provides better performance in terms of higher gain and directivity than conventional CNTFET (C-CNTFET). This device will be helpful in optoelectronic integrated circuits (OEIC) receivers due to its superior performance.

Carbon Nanotube Field-Effect Transistor Biosensor for Ultrasensitive and Label-Free Detection of Breast Cancer Exosomal miRNA21.

Tumor-derived exosomal miRNAs may have important functions in the onset and progression of cancers and are potential biomarkers for early diagnosis and prognosis monitoring. Yet, simple, sensitive, and label-free detection of exosomal miRNAs remains challenging. Herein, an ultrasensitive, label-free, and stable field-effect transistor (FET) biosensor based on a polymer-sorted high-purity semiconducting carbon nanotube (CNT) film is reported to detect exosomal miRNA. Different from conventional CNT FETs, the CNT FET biosensors employed a floating gate structure using an ultrathin Y2O3 as an insulating layer, and assembled Au nanoparticles (AuNPs) on Y2O3 as linkers to anchor probe molecules. A thiolated oligonucleotide probe was immobilized on the AuNP surface of the sensing area, after which miRNA21 was detectable by monitoring the current change before and after hybridization between the immobilized DNA probe and target miRNA. This method achieved both high sensitivity (LOD: 0.87 aM) and high specificity. Furthermore, the FET biosensor was employed to test clinical plasma samples, showing significant differences between healthy people and breast cancer patients. The CNT FET biosensor shows the potential applications in the clinical diagnosis of breast cancer.

Darlington Based 8T CNTFET SRAM Cells with Low Power and Enhanced Write Stability

In this paper, a novel low power and high write margin Darlington based NCNTFET Darlington 8T SRAM cell is proposed. The power consumption of the proposed Darlington SRAM cell is compared with that of conventional 6T CNTFET and conventional 8T CNTFET SRAM cells. The power consumption of the proposed Darlington SRAM cells is very less as compared to that of conventional 6T and 8T CNTFET SRAM cells for all write, hold, and read operations. The write static noise margin (WSNM) of the proposed NCNTFET Darlington 8T cell is found to increase by 70.83% than that of both conventional 6T and 8T CNTFET SRAM cell. Effect of CNTFET parameters such as chiral vectors (m,n), gate oxide thickness (Hox), dielectric constant of gate oxide material (Kox), temperature, pitch value, number of carbon nano tubes (CNTs) and supply voltage (VDD), on the power performance, drain current (ID) and drain to source voltage (VDS) of the novel proposed Darlington SRAM cell are investigated. The write, hold, and read power consumption of proposed NCNTFET Darlington 8T SRAM cell is compared with that of some of the existing SRAM cells. The simulation is carried out using Stanford University 32 nm CNTFET model.

Design of Ternary Logic and Arithmetic Circuits Using GNRFET

Multiple valued logic (MVL) can represent an exponentially higher number of data/information compared to the binary logic for the same number of logic bits. Compared to the conventional and other emerging device technologies, Graphene Nano Ribbon Field Effect Transistor (GNRFET) appears to be very promising for designing MVL logic gates and arithmetic circuits due to some exceptional electrical properties of the GNRFET, e.g., the ability to control the threshold voltage by changing the width of the GNR. Variation of the threshold voltage is one of the prescribed techniques to achieve multiple voltage levels to implement the MVL circuit. This paper introduces a design approach for ternary logic gates and circuits using MOS-type GNRFET. The designs of basic ternary logic gates like inverters, NAND, NOR, and ternary arithmetic circuits like the ternary decoder, 3:1 multiplexer, and ternary half-adder are demonstrated using GNRFET. A comparative analysis of the GNRFET based ternary logic gates and circuits and those based on the conventional CMOS and CNTFET technologies is performed using delay, total power, and power-delay-product (PDP) as the metrics. The simulation and analysis are performed using the H-SPICE tool with a GNRFET model available on the Nanohub website.

High Stable and Low Power 10T CNTFET SRAM Cell

The ultimate aim of a memory designer is to design a memory cell which could consume low power with high data stability in the deep nanoscale range. The implementation of Very Large-Scale Integration (VLSI) circuits using MOSFETs in nanoscale range faces many issues such as increasing of leakage power and second-order effects that are easily affected by the PVT variation. Hence, it is essential to find the best alternative of MOSFET for deep submicron design. The Carbon Nanotube Field Effect Transistor (CNTFET) can eradicate all the demerits of MOSFET and be the best replacement of MOSFET for nanoscale range design. In this paper, a 10T CNTFET Static Random Access Memory (SRAM) cell is proposed. The power consumption and Static Noise Margin (SNM) are analyzed. The power consumption and stable performance of the proposed 10T CNTFET SRAM cell are compared with that of conventional 10T CNTFET SRAM cell. The power and stability analyses of the proposed 10T and conventional 10T CNTFET SRAM cells are carried out for the CNTFET parameters such as pitch and chiral vector ([Formula: see text]). The power and SNM analyses are carried out for [Formula: see text]20% variation of oxide thickness (Hox), different dielectric constant (Kox). The supply voltage varies from 0.9[Formula: see text]V to 0.6[Formula: see text]V and temperature varies from 27∘C to 125∘C. The simulation results show that the proposed 10T CNTFET SRAM cell consumes lesser power than conventional 10T CNTFET SRAM cell during the write, hold and read modes. The write, hold and read stability of the proposed 10T CNTFET SRAM cell are higher as compared with that of conventional 10T CNTFET SRAM. The conventional and proposed 10T SRAM cells are also implemented using MOSFET. The stability and power performance of proposed 10T SRAM cell is also as good as conventional 10T SRAM for MOSFET implementation. The proposed 10T SRAM cell consumes lesser power and gives higher stability than conventional 10T SRAM cell in both CNTFET and MOSFET implementation. The simulation is carried out using Stanford University 32[Formula: see text]nm CNTFET model in HSPICE simulation tool.

Design and analysis of dynamically configurable electrostatic doped carbon nanotube tunnel FET

This paper proposes a novel design of dynamically configurable electrostatic doped double gate carbon nanotube tunnel FET (ED CN-TFET). The proposed device consists of intrinsic carbon nanotube (CN) as channel and electrostatic doping is created using polarity gates. Polarity gate allows dynamic configuration of source/drain region with different bias conditions. As conventional doping techniques are not applicable to CN which makes fabrication costly, proposed device will offer reduced thermal budget and process complexity. 3-D simulations have been performed and results show that proposed device gives promising results over conventional CN-TFET in terms of ION/IOFF ratio and subthreshold swing (SS). Proposed device has been analysed for various device parameters and it has been demonstrated to give better results as compared to conventional CN-TFET.

Comparative Analysis of 6T, 7T Conventional CMOS and CNTFET Based SRAM Cell Design

Comparative Analysis of 6T, 7T Conventional CMOS and CNTFET Based SRAM Cell Design

Design and Optimization of Lightly Doped CNTFET Architectures Based on NEGF Method and PSO Algorithm

Optimized architectures for carbon nanotube field-effect transistors (CNTFETs) with lightly doped source and drain have been proposed. Simulations are based on self-consistent solution of two dimensional non-equilibrium Green's function (NEGF) with Poisson's equation. By utilizing special designs in the lightly doped regions of the CNTFETs, their characteristics could be improved. Four CNTFET structures have been designed and compared to the conventional CNTFET which are lightly doped source and drain (LD_CNTFET), double lightly doped source and drain (DLD_CNTFET), linear lightly doped source and drain (LLD_CNTFET) and step-linear lightly doped source and drain (SLLD_CNTFET). In order to get to the optimized electrical characteristics, for the first time, the geometry and the doping of the new designed CNTFETs have been optimized. The target of optimizations has been achieving the best Ion/Ioff, cutoff Frequency and transconductance independently. The proposed designs have been optimized based on particle swarm optimization (PSO) method. The optimized length and doping level of source and drain lightly doped regions then have been used and the features of the proposed optimized CNTFETs have been compared. The results show that with the help of the proposed designs, great improvements have been achieved in the dc and ac characteristics of CNTFETs compared to the conventional CNTFETs.

Design and analysis of electrostatic doped tunnel CNTFET for various process parameters variation

In this paper, electrostatic doped Tunnel carbon nano tube field effect transistor(ED-Tunnel CNTFET) is proposed. Additional gates in the source and drain regions draw an appropriate doping profile, which avoids the most severe issues: the tradeoff between screening and low Fermi energy in Tunnel CNTFETs and the deactivation of dopants in nanoscale transistors with conventional doping. ED-Tunnel CNTFET shows better results over conventional Tunnel CNTFET in terms of ION/IOFF ratio and subthreshold slope (SS). ED-Tunnel CNTFET is investigated for various performance parameters using Nano ViDES device simulator. The simulation results of drain current characteristics at different polarity gates (PGs) bias, drain voltages, diameters of CNT and channel lengths have been extracted. The SS value of ED-Tunnel CNTFET as low as 24 mV/dec at 0.1 V drain voltage for 20 nm channel length and 1 nm channel thickness has been achieved. The device shows improved ION/IOFF ratio and very low SS value demonstrated the potential of proposed device for switching and memory applications.

Electrostatically doped tunnel CNTFET model for low-power VLSI circuit design

With advantages such as low sub-threshold swing, low OFF-state current and the ability to attain a higher ON–OFF ratio, the tunnel CNTFET is one of the most comprehensively investigated devices for low-power application. The problems associated with this device are fabrication issues since conventional doping is not possible in CNTs. Therefore, a doping-less tunnel CNTFET is proposed which is free from problems associated with a conventional tunnel CNTFET. A mathematical model is developed for an electrostatically doped tunnel CNTFET, and to validate the model accuracy and the equation set, the simulation results are compared with NanoTCAD ViDES results. Finally, the developed model is deployed in an inverter design to verify the suitability of the model for circuit applications.

Modeling a Double-Halo-Doping Carbon Nanotube FET in DC and AC Operations

Double-Halo-Doping carbon nanotube field effect transistor (DH-CNTFET) has been recently suggested as a reliable and efficient device for the nanoscale applications which is a potential candidate to obsolete the conventional CNTFET (C-CNTFET), eventually. In this respect, the work aims to present an accurate compact analytical model for the drain current which is applicable in the different SPICE levels for circuit simulations. The paper captures the fundamental physic of a conventional CNTFET in order to develop a comprehensive and accurate analytical drain current model for the DH-CNTFET structure. Regarding the DH-CNTFET structure, important decision variables in the cases of ballistic carrier velocity, electron mobility, source/drain series resistance, threshold voltage, drain induced barrier lowering (DIBL) factor, fermi level to the band edge in the source region, subthreshold swing factor and band-to-band tunneling factor are introduced and globally searched by the PSO algorithm to achieve the most accurate relation for the drain current. The suggested compact analytical model is successfully compared with the realistic data extracted from the numerical simulation of the DH-CNTFET by full quantum mechanical Green's function approach. The results revealed that the compact analytical model predicts the drain current of the DH-CNTFET, accurately. As the other worthwhile effort, the work has proposed a compact analytical model for the gate-source and gate-drain capacitances providing it very attractive and suitable for the simulations under the circuit in the SPICE different levels.

Design and analysis of electrostatic doped Schottky barrier CNTFET based low power SRAM

In recent years, much emphasis is given for low power memory design by reducing leakage power. Carbon nanotube field effect transistor (CNTFET) based static random access memory (SRAM) provides better stability along with low static power consumption due to variable bandgap and threshold voltage as function of diameter. Electrostatic doped Schottky barrier carbon nanotube field effect transistor (ED-SBCNTFET) accounts for much low leakage current and hence can be used for low power SRAM design. This paper proposes a novel design of ED-SBCNTFET based low power SRAM which consists of additional polarity gates. 6-T SRAM cell is designed and simulated in HSPICE for both conventional CNTFET and ED-SBCNTFET. SRAM performance is analyzed on the basis of various figures of merit i.e. stability and power dissipation. ED-SBCNTFET SRAM shows advantage of low power over conventional CNTFET SRAM without loss of stability. Furthermore, SRAM is designed for smaller diameter which gives ultra low power cell with minute change in stability. Lastly dual chirality scheme is implemented and analyzed for ED-SBCNTFET 6-T SRAM cell.

A comprehensive analytical study of electrical properties of carbon nanotube field‐effect transistor for future nanotechnology

AbstractThis paper discusses a comprehensive analytical study of electrical properties of single‐wall conventional carbon nanotube field‐effect transistor (CNTFET) devices of subthreshold swing (SS), transconductance (gm), and extension resistance. The analytical expressions for SS and gm have been derived based on channel modulated potential. In the study, it was observed that SS value of the CNTFET device is equal to 60 mV/decade, which is smaller than the conventional and double gate metal‐oxide‐semiconductor field‐effect transistors. The subthreshold swing degrades at larger tube's diameter and gate‐source voltage due to increased source‐drain leakage current. Carbon nanotube field‐effect transistor devices achieve larger gm at large gate‐source voltage, which has a disadvantage of reducing the allowable voltage swing at the drain. The extension resistance of the device falls with diameter of the tube.

Analysis of electrostatic doped Schottky barrier carbon nanotube FET for low power applications

This paper presents the analysis of electrostatic doped Schottky barrier carbon nanotube FET (ED-SBCNTFET) for low power applications. Electrostatic doping is introduced in intrinsic CNT as a channel material which reduces the process complexity; moreover dynamic configuration provides symmetric transfer characteristics for n-type and p-type for ED-SBCNTFET. Simulation results demonstrate that ED-SBCNTFET is better than conventional CNTFET in terms of IOFF and subthreshold swing (SS) which makes it suitable for low power applications. Simulations are performed and sensitivity analysis is carried out for CNT diameter, effective oxide thickness (EOT), high-k dielectric and polarity gate bias. It is observed that CNTs are most sensitive to diameter, since CNT with diameter 0.85 nm exhibits ION/IOFF ratio of ~109 and SS of 60.8 mv/dec whereas diameter of 0.55 nm results into ION/IOFF ratio of ~1011 with SS of 58.5 mv/dec. Optimized parameters are proposed for low power applications in terms of IOFF and SS. ED-SBCNTFET has been analysed for various process parameters and it has been demonstrated to be less sensitive to process variations.

Performance analysis of junctionless carbon nanotube field effect transistors using NEGF formalism

This paper presents the simulation study of a junctionless carbon nanotube field effect transistor (JL-CNTFET) and a comparison is made with the conventional CNTFET using the atomistic scale simulation, within the non-equilibrium Green’s function (NEGF) formalism. In order to have a comprehensive analysis, both analog and digital parameters of the device are studied. Results have shown that JL-CNTFET with respect to C-CNTFET shows slightly higher [Formula: see text] ratio about two times larger than that of C-CNTFET, smaller electric field along channel more than three order of magnitude and reduced tunneling current about 100 times. In addition, the investigation of analog properties of both devices has exhibited that junctionless structure has a transconductance about two times and an intrinsic gain of 15 dB larger than C-CNTFET in same bias condition which makes JL-CNTFET a promising candidate for low voltage analog applications.

Performance analysis of an ultralow power circuit using single halo CNTFETs

This work presents a comprehensive study of the influence of channel engineering on the switching, high frequency characteristics, and circuit-level performance of carbon nanotube field-effect transistors (CNTFETs). At the device level, new CNTFETs with single halo doping (SH-CNTFETs) have been proposed. The impact of SH implantation on the cutoff frequency (fT), switching delay (τ), and on/off current ratio (Ion/Ioff) has been explored and it is revealed that SH-CNTFETs have improved radio frequency (RF) and switching characteristics. At the circuit level, using the Hailey Simulation Program with IC Emphasis (HSPICE) with lookup table (LUT)-based Verilog-A models, the performance parameters of the circuit have been calculated. Results show that compared to a conventional CNTFET (C-CNTFET)-based inverter, the SH-CNTFET-based inverter exhibits better performance. In addition, we evaluate the stability and performance of six-transistor (6T) CNTFET static random access memory (SRAM) cells with SH-CNTFETs. The performance parameters such as static noise margin (SNM) and write delay as well as power-delay product (PDP) and SNM/write delay (SWD) have been calculated and optimized. It is shown that SH-CNTFET SRAMs have an improved performance in SNM, PDP, and write power compared to C-CNTFET SRAMs and the optimum halo doping level has been concluded. Our results may be useful for designing and optimizing CNTFET devices and circuits.

Influence of Channel and Underlap Engineering on the High-Frequency and Switching Performance of CNTFETs

We have comprehensively studied the influence of the channel and underlap engineering on the switching and high-frequency performance of carbon nanotube field-effect transistors (CNTFETs). Various source/drain and channel-engineered CNTFETs have been investigated and optimized architectures have been concluded from simulations. Performance parameters such as switching time τ and cutoff frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> as well as ambipolarity and on/off ratio I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> / I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> have been calculated and optimized. New CNTFETs with staircase doping in the underlap region (SU-CNTFETs)] have been proposed and the optimized underlap length and doping level have been concluded. Adding this kind of underlaps to conventional CNTFETs improves f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> , τ, and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> and limits the leakage current simultaneously. For the first time, laterally asymmetric channel CNTFETs with a realistic staircase doping (SLAC-CNTFETs) have been proposed. It is shown that SLAC-CNTFET has an improved RF and switching performance while maintaining a good I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> . The effect of single halo implantation on the aforementioned parameters has been calculated and it is revealed that it degrades the figures of merit. Detailed reasoning of the aforementioned characteristics has been discussed based on the gate and channel electric field distributions and the quantum capacitance. The impact of fringing field capacitances on f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> has been computed and shown that it is not negligible. Finally, our calculations for an individual CNTFET with metallic contacts showed that the Schottky barriers at the contacts deteriorate almost all the figures of merits except I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> .

Design and Modelling of Different SRAM'S Based on CNTFET 32NM Technology

Carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. Since it was first demonstrated in 1998, there have been tremendous developments in CNTFETs, which promise for an alternative material to replace silicon in future electronics. Carbon nanotubes are promising materials for the nano-scale electron devices such as nanotube FETs for ultra-high density integrated circuits and quantum-effect devices for novel intelligent circuits, which are expected to bring a breakthrough in the present silicon technology. A Static Random Access Memory (SRAM) is designed to plug two needs: i) The SRAM provides as cache memory, communicating between central processing unit and Dynamic Random Access Memory (DRAM). ii) The SRAM technology act as driving force for low power application since SRAM is portable compared to DRAM, and SRAM doesn't require any refresh current. On the basis of acquired knowledge, we present different SRAM's designed for the conventional CNTFET. HSPICE simulations of this circuit using Stanford CNTFET model shows a great improvement in power saving.