Conventional Bulk Si Research Articles

Fabrication of strained-Si channel p-MOSFET’s on ultra-thin SiGe virtual substrates

In the ultra-thin relaxed SiGe virtual substrates, a strained-Si channel p-type Metal Oxide Semiconductor Field Effect Transistor (p-MOSFET) is presented. Built on strained-Si/240nm relaxed-Si0.8 Ge0.2/100nm Low Temperature Si (LT-Si)/10nm Si buffer was grown by Molecular Beam Epitaxy (MBE), in which LT-Si layer is used to release stress of the SiGe layer and made it relaxed. Measurement indicates that the strained-Si p-MOSFET’s (L-4.2 μm) transconductance and the hole mobility are enhanced 30% and 50% respectively, compared with that of conventional bulk-Si. The maximum hole mobility for strained-Si device is 140cm2/Vs. The device performance is comparable to devices achieved on several μm thick composition graded buffers and relaxed-SiGe layer virtual substrates.

Ring Oscillators for CMOS Process Tuning and Variability Control

Test structures utilizing ring oscillators to monitor MOSFET ac characteristics for digital CMOS circuit applications are described. The measurements provide information on the average behavior of sets of a few hundred MOSFETs under high speed switching conditions. The design of the ring oscillators is specifically tailored for process centering and monitoring of variability in circuit performance in the manufacturing line as well as in the product. The delay sensitivity to key MOSFET parameter variations in a variety of ring oscillator designs is studied using a compact model for partially depleted silicon on insulator(PD-SOI) technology, but the analysis is equally valid for conventional bulk Si technology. Examples of hardware data illustrating the use of this methodology are taken primarily from experimental hardware in the 90-nm CMOS technology node in PD-SOI. The design and data analysis techniques described here allow very rapid investigation of the sources of variations in circuit delays.

Leakage Power Analysis of 25-nm Double-Gate CMOS Devices and Circuits

Leakage power and input pattern dependence of leakage for extremely scaled (L/sub eff/=25nm) double-gate (DG) circuits are analyzed, compared with those of conventional bulk-Si counterpart. Physics-based numerical two-dimensional simulation results for DG CMOS device/circuit power are presented, identifying that DG technology is an ideal candidate for low-power applications. Unique DG device features resulting from gate-gate coupling are discussed and effectively exploited for optimal low-leakage device design. Design tradeoffs for DG CMOS power and performance are suggested for low-power and high-performance applications. Total power consumptions of static and dynamic circuits and latches for DG device, considering state dependency, show that leakage currents for DG circuits are reduced by a factor of over 10/spl times/, compared with bulk-Si counterpart.

Power analysis of strained-Si devices/circuits

The feasibility of nano-scale strained-Si technologies for low-power applications is studied. Static and dynamic power for strained-Si device is analyzed and compared with conventional bulk-Si technology. Optimum device design points are suggested, and strained-Si CMOS circuits are studied, showing substantially reduced power consumptions. The trade-offs for power and performance in strained-Si devices/circuits are discussed. Further, analysis and low-power design points are applied and extended to strained Si on SOI substrate (SSOI) CMOS technology.

Low-frequency noise analysis of Si/SiGe channel pMOSFETs

Low-frequency noise characteristics of 0.1 μm Si 1− x Ge x channel pMOSFETs were studied by numerical simulations in the framework of the carrier number fluctuation model as well as the correlated fluctuation in the mobility model. Simulation results predict that Si 1− x Ge x channel pMOSFETs could offer improved low-frequency noise performance as compared to the conventional bulk Si devices. This improvement in Si 1− x Ge x channel pMOSFETs could be attributed to less effective oxide trap density for noise generation due to the increasing separation of quasi-Fermi level and valence band edge at Si–SiO 2 interface by Ge-induced band offset.

Studies of charge collection mechanisms in SOI devices using a heavy-ion microbeam

Transient currents induced in silicon-on-insulator (SOI) devices by high energy-carbon or oxygen ions were evaluated using a focused ion microbeam and a wide bandwidth measurement system. The total amount of collected charge in the SOI pn junction with the 5.7μm thick top Si layer was found to be less than that in pn junctions fabricated in bulk Si. The charge collection was estimated to be limited in the top Si layer of the SOI devices. These findings give experimental evidence that SOI devices have higher resistance to soft error than conventional bulk Si devices.

Characterization of bond and etch-back silicon-on-insulator wafers by photoluminescence under ultraviolet excitation

Photoluminescence (PL) spectroscopy under the ultraviolet (UV) light excitation has been used for the characterization of bond and etch-back silicon-on-insulator (BESOI) wafers. Since the UV light can excite only the silicon-on-insulator (SOI) layer and the SOI structure prevents the photoexcited carriers from diffusing into the base wafer, the PL light is emitted only from the SOI layer. We have detected defects induced during the photoassisted chemical etching process in BESOI wafers. The defect-related emission disappears and the electron-hole droplet signal appears after annealing at 800 °C for 30 min. This allows us to suggest that the annealed SOI layer is comparable in crystalline quality with that of conventional bulk Si wafers and that the recombination velocity at the interfaces is low.

CAD-compatible high-speed CMOS/SIMOX gate array using field-shield isolation

A specific 0.5 /spl mu/m CMOS/SIMOX technology was developed for a gate array/sea of gate (SOG) using field-shield (FS) isolation to overcome a pending problem of source-to-drain breakdown voltage (BV/sub ds/) lowering. FS isolation is capable of improving BV/sub ds/ because surplus holes generated by impact ionization at the drain region are collected through the body region under the FS gate. BV/sub ds/ was maintained at a level of junction breakdown before reaching the punchthrough limitation at a gate length of around 0.3 /spl mu/m using the FS isolation. The FS isolation technique was successfully applied to an SOG gate array on a SIMOX substrate. The gate array has the same area as that on the bulk-Si and is compatible to a conventional bulk-Si CAD system because the layout is basically the same. A 53-stage ring oscillator fabricated on the FS isolated SOG gate array exhibited 1.7 times higher speed operation than that on a bulk-Si counterpart, keeping low power consumption characteristics up to a drain voltage of 3 V. >