Conventional BiCMOS Research Articles

A SiGe BiCMOS analog SISO decoder with I/O interface

Although recent implementations of analog iterative decoders have proven their potential for higher decoding speed and less power consumption than their digital counterparts, the CMOS or conventional BiCMOS technologies used so far seem to be incapable to cope with the need for high throughput that high-speed applications require. Within this context this work presents the design and test results of a high-speed analog SISO (Soft-Input Soft-Output) channel decoder for an 8-bit trellis code by exploiting the high-speed features of SiGe heterojunction bipolar transistors (HBTs). It is one of the first successful implementations of an error-correcting decoder in SiGe BiCMOS technology, which incorporates a high-speed I/O interface. A high-level model of the mismatch effects indicates that there is no significant performance penalty. Moreover, simulations and performance evaluations of an analog Turbo decoder based on the designed SISO decoder are provided. Even though the IC of the SISO module was tested at a throughput up to 3 Mbps, simulation results show that the decoder is capable to operate at 50 Mbps. The measured power consumption is 860 mW and the die area is 3.4 × 3 mm2.

BiCMOS domino: a novel high-speed dynamic BiCMOS logic

A new BiCMOS dynamic logic family is presented. The logic gates provide a significant speed-up over existing logic families, such as, CMOS, BiCMOS and dynamic CMOS for the same feature size. The proposed logic family provides a high drive capability to drive large loads at higher speeds compared with the CMOS domino logic family. The proposed logic family has power advantages, due to dynamic operation, compared with the conventional fully complementary CMOS and BiCMOS devices. It also has an area advantage compared with conventional BiCMOS gates. The proposed high-speed BiCMOS domino family provides speed improvement with existing feature size, using the existing fabrication technology. The novel high-speed dynamic BiCMOS logic implementations can significantly affect the speed of VLSI circuits including microprocessors, memories and signal processors.

Effects and modeling of simultaneous switching noise for BiCMOS off-chip drivers

A model of simultaneous switching noise (SSN) for the conventional BiCMOS driver including the influence of negative feedback is presented. Level 1 SPICE-type MOSFET and Gummel-Poon BJT device models are used for the analysis. The model accounts for a reduction in forward current gain, /spl beta//sub F/, that is attributed to high-level injection effects. Closed-form expressions are presented that predict the maximum SSN encountered in low-level and high-level injection. Solutions of the first equation are combined with the second in order to model the complete SSN transient. Model predictions are compared to SPICE simulation results for 5 V, 1 /spl mu/m drivers and 3.5 V, 0.5 /spl mu/m drivers with close agreement. The effects of BJT parasitic resistance, junction capacitance, and forward transit time on reducing induced ground noise are also explored. With the introduction of these parasitics, SPICE predictions of the maximum SSN are approximately 20% lower than closed-form model results. Immunity of the quiet BiCMOS driver to noise present at the ground and power connections is also investigated. It is found that the quiet driver is highly immune to adverse effects caused by SSN at the power connection and partially immune to SSN present at the ground. Coupling between ground noise and the output occurs when the ground noise is greater than two forward diode drops above ground, in which case the output tracks the ground noise with a negative offset of one diode drop.

A BiCMOS wired-OR logic

This paper proposes a BiCMOS wired-OR logic for high-speed multiple input logic gates. The logic utilizes the bipolar wired-OR to circumvent the use of a series connection of MOS transistors. The BiCMOS wired-OR logic was found to be the fastest compared with such conventional gates as CMOS NOR, BiCMOS multiemitter logic and CMOS wired-NOR logic, when the number of inputs was more than four and the supply voltage was 3.3 V. The BiCMOS wired-OR logic was also determined to be the fastest of the four when the fan-out number was below 20 and the number of inputs was eight. In addition, the speed was more than twice as faster when the fan-out number was less than 10. The BiCMOS wired-OR logic was applied to a 64-b 2-stage carry look-ahead adder, and was fabricated with a 0.5-/spl mu/m BiCMOS process technology. A critical path delay time of 3.1 ns from an input to a sum output was obtained at the supply voltage of 3.3 V. This is 35% faster than that of conventional BiCMOS adders. >

Schottky merged BiCMOS structures

A new merged BiCMOS structure is presented. It incorporates a Schottky diode between the base and the collector of the n-p-n bipolar transistor. The structure offers the same reduced area advantage of merged over conventional BiCMOS, and is shown to have granted latchup immunity to BiCMOS circuits. The device simulations using HSPICE verify the latchup immunity. >

A delay model and optimization method of a low-power BiCMOS logic circuit

A new delay model and optimization method is proposed for a low-power BiCMOS driver. A transient overdrive, base directly-tied complementary BiCMOS logic circuit operates faster than conventional BiCMOS and CMOS circuits for supply voltage down to 1.5 V by using a speed-power-area optimization approach. An analytical delay expression is derived for the first time for a full-swing BiCMOS circuit with short-channel effects. The circuit is simulated with a HSPICE model using 0.8-/spl mu/m BiCMOS technology with a 6-GHz n-p-n and a 1-GHz p-n-p transistor. The simulation results have verified the analytical results and demonstrated that the circuit can work up to 200 MHz operating frequency for a load capacitance of 1 pF at 1.5 V of supply voltage.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Study of BiCMOS logic gate configurations for improved low-voltage performance

A simple BiCMOS configuration employing the source-well tie PMOS/n-p-n pull-down combination is proposed for low-voltage, high-performance operations. The improved BiCMOS gate delay time over that of the NMOS/n-p-n (conventional) BiCMOS gate is confirmed by means of inverter simulations and measured ring oscillator data. The source-well tie PMOS/n-p-n BiCMOS gate outperforms its conventional BiCMOS counterpart in the low-voltage supply range, at both high and low temperatures. A critical speed path from the 68030 internal circuit is used as a benchmark for the proposed BiCMOS design technique. The measured propagation delay of the BiCMOS speed path is faster than its CMOS counterpart down to 2.3 V supply voltage at -10 degrees C and sub-2 V at 110 degrees C. >

Multiemitter BiCMOS logic circuit family

A new multiemitter BiCMOS circuit using half-micrometer BiCMOS technology with a 3.6-V supply provides 85 % improvement in delay over CMOS design and 40 % improvement over conventional BiCMOS. This benefit is demonstrated in a 64-b carry look-ahead adder where most of the gates have a high number of inputs. A complete logic circuit family based on the multiemitter (ME) concept is proposed in a gate-array structure.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Quasi-complementary BiCMOS for sub-3-V digital circuits

The authors describe a quasi-complementary BiCMOS (QC-BiCMOS) circuit scheme for the low-supply-voltage deep-submicrometer regime. A QC-BiCMOS performs twice as fast as a CMOS even at a 2.5-V supply without a p-n-p bipolar transistor. Key circuits for this low-voltage performance are a separation between the base of the pull-up bipolar and the base of a quasi-p-n-p and the carefully designed base discharging circuit. A quasi-p-n-p combination of a pMOS and an n-p-n bipolar based on these circuits shows an equivalent cutoff frequency of over 10 GHz. The delay expressions for the QC-BiCMOS are analyzed and compared with the conventional BiCMOS. A 0.3- mu m fully loaded three-input NAND gate was fabricated, verifying that the QC-BiCMOS has more than twice the performance leverage over the conventional BiCMOS and the CMOS at a sub-3-V supply. >

New full-voltage-swing BiCMOS buffers

Circuit techniques are presented for increasing the voltage swing of BiCMOS buffers through active charging and discharging using complementary bipolar drivers. These BiCMOS circuits offer near rail-to-rail output voltage swing, higher noise margins, and higher speed of operation at scaled-down power supply voltages. The circuits are simulated and compared to BiCMOS and CMOS buffers. The comparison shows that the conventional BiCMOS and the complementary BiCMOS buffers are efficient for power supply voltages greater than 3V and that if the power supply voltage is scaled down (<3 V) and the load capacitance is large (>1 pF), the complementary BiCMOS buffers would be the most suitable choice. They provide high speed and low delay to load sensitivity and high noise margins. The first implementation is favorable near a 2.5-V power supply for its smaller area.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Substrate current reduction techniques for BiCMOS DRAM

Substrate current (I/sub BB/) reduction techniques useful to BiCMOS DRAM's are proposed through a comparison of the I/sub BB/ characteristics for a BiCMOS driver and a CMOS driver and through a clarification of the I/sub BB/ generation mechanism. Four key results are obtained. One is that the I/sub BB/ of conventional BiCMOS drivers is unacceptably high, i.e, three times larger than that of CMOS drivers. Another is that the excessive I/sub BB/ of BiCMOS drivers is generated by the saturation of bipolar transistors, which results from a collector voltage decrease caused by large amounts of collector current flowing through the collector saturation resistance r/sub cs/. The third result concerns proposals for I/sub BB/ reduction techniques. One features two collector outputs terminals for avoiding the r/sub cs/ effect and the other features application of a low supply voltage for the base. The last result is that BiCMOS drivers using the I/sub BB/ reduction techniques make it possible to achieve 1-Mbit BiCMOS DRAM'S with I/sub BB/ levels comparable to those of conventional CMOS DRAM's. >

Bidirectional lateral insulated gate transistors operated in controlled latchup mode

The use of the lateral insulated transistor (LIGT) as an integrable MOS controlled power switch has been reported recently. The mode of operation is based on a MOS transistor turning on and subsequently saturating a bipolar transistor. Latchups of the parasitic thyristor are to be avoided so that the gate exerts full control at all times. It is shown that the latchup mode of operation can be controlled by the gate with proper design of the device structure. The advantages of operating the device in latchup mode are higher current capabilities and lower 'on' voltages than available in other modes of operation. The bidirectional LIGT is symmetrical in that it conducts current and block voltage in both directions. It can be readily implemented with conventional BICMOS process without any additional process steps. The operation, fabrication, and performance of the bidirectional device are briefly described. >