A SiGe BiCMOS analog SISO decoder with I/O interface

Abstract

Although recent implementations of analog iterative decoders have proven their potential for higher decoding speed and less power consumption than their digital counterparts, the CMOS or conventional BiCMOS technologies used so far seem to be incapable to cope with the need for high throughput that high-speed applications require. Within this context this work presents the design and test results of a high-speed analog SISO (Soft-Input Soft-Output) channel decoder for an 8-bit trellis code by exploiting the high-speed features of SiGe heterojunction bipolar transistors (HBTs). It is one of the first successful implementations of an error-correcting decoder in SiGe BiCMOS technology, which incorporates a high-speed I/O interface. A high-level model of the mismatch effects indicates that there is no significant performance penalty. Moreover, simulations and performance evaluations of an analog Turbo decoder based on the designed SISO decoder are provided. Even though the IC of the SISO module was tested at a throughput up to 3 Mbps, simulation results show that the decoder is capable to operate at 50 Mbps. The measured power consumption is 860 mW and the die area is 3.4 × 3 mm2.