Control Data Flow Graph Research Articles

High-Level Controllability and Observability Analysis for Test Synthesis

In this study, we present a high-level testability analysis technique that evaluates the testability of a design based on the proposed controllability and observability measures. The control-data flow graph (CDFG) constructed from the VHDL description of a design is first analyzed to identify hard-to-control conditional branches and hard-to-control/observe register transfer statements. After the hard-to-test areas of the design are identified, the proposed testability enhancement methods can be applied to improve the testability of the circuit. Unlike many recent studies in the area of high-level test synthesis (HLTS) that focus on improving the testability of data paths, our approach also improves the testability of synthesized circuits by enhancing the controllability of the control flow. Experimental results on several high-level synthesis benchmarks show that when this approach is used prior to logic synthesis, the test generation complexities are reduced while better fault coverage and ATPG efficiency are often achieved. Implementation of this technique requires minimal logic and performance overheads and allows test vectors to be applied at clock-speed.

Premonoidal categories and flow graphs

We give two presentations of the semantics of programs: a categorical semantics based on Power and Robinson's symmetric premonoidal categories and Joyal, Street and Verity's traced monoidal categories, and a graphical semantics based on mixed control flow and data flow graphs. We show how these semantics are related, and sketch how the 2-categorical versions could be used to give an operational semantics for programs. The semantics is similar to Hasegawa's presentation of Milner and Gardner's name-free action calculi.

Optimal algorithms for recovery point insertion in recoverable microarchitectures

This paper considers the problem of automatic insertion of recovery points in recoverable microarchitectures. Previous work on this problem provided heuristic nonoptimal algorithms that attempted either to minimize computation time with a bounded hardware overhead or to minimize hardware overhead with a bounded computation time. In this paper, we present polynomial-time algorithms that provide provably optimal solutions for both of these formulations of the problem. These algorithms take as their input a scheduled control-data flow graph describing the behavior of the system, and they output either a minimum time or a minimum cost set of recovery point locations. We demonstrate the performance of our algorithms using some well-known benchmark control-data flow graphs. Over all parameter values for each of these benchmarks, our optimal algorithms are shown to perform as well as, and in many cases better than, the previously proposed heuristics.

Real time pipelined system design through simulated annealing

This paper is concerned with automatic pipeline implementation of a program subject to some real time (RT) constraints; the program is described through a Control Data Flow Graph (CDFG). We have developed a mapping methodology which assigns to each instruction of CDFG a time step and a HW resource for its execution. We have defined the space Ω of all the possible feasible mappings, as well as an adjacency criterion on it and a cost function evaluating the quality of the mappings. We have minimized the cost function through a Simulated Annealing algorithm. The minimization process returns a mapping which satisfies all RT constraints, has minimal schedule length and minimal HW resource requirement. In order to show the capabilities of the proposed mapping methodology, we apply it to a graph with 50 nodes and several RT constraints: the obtained mapping gives a pipelined execution modality of the graph which satisfies all the given RT constraints.

Scheduling and allocation in high-level synthesis using stochastic techniques

High-level synthesis is the process of automatically translating abstract behavioral models of digital systems to implementable hardware. Operation scheduling and hardware allocation are the two most important phases in the synthesis of circuits from behavioral specification. Scheduling and allocation can be formulated as an optimization problem. In this work, a unique approach to scheduling and allocation problem using the genetic algorithm (GA) is described. This approach is different from a previous attempt using GA (Wehn et al., IFIP Working Conference on Logic and Architecture Synthesis, Paris, 1990, pp. 47–56) in many respects. The main contributions include: (1) a new chromosomal representation for scheduling and for two subproblems of allocation; and (2) two novel crossover operators to generate legal schedules. In addition the application of tabu search (TS) to scheduling and allocation is also implemented and studied. Two implementations of TS are reported and compared. Both genetic scheduling and allocation (GSA) and tabu scheduling and allocation (TSA) have been tested on various benchmarks and results obtained for data-oriented control-data flow graphs are compared with other implementations in the literature. (A discussion on GSA was presented at the European Design Automation Conference Euro-DAC'94 in Grenoble, France, and TSA at the International Conference on Electronics, Circuits and Systems — ICECS'94 in Cairo, Egypt.) A novel interconnect optimization technique using the GA is also realized.

From VHDL to efficient and first-time-right designs

In this article we provide a practical transformational approach to the synthesis of correct synchronous digital hardware designs from high-level specifications. We do this while taking into account the complete life cycle of a design from early prototype to full custom implementation. Besides time-to-market, both flexibility with respect to target architecture and efficiency issues are addressed by the methodology. The utilization of user-selected behavior-preserving transformation steps ensures first-time-right design while exploiting the experience, flexibility, and creativity of the designer.To ensure that design transformations are indeed behavior-preserving a novel mechanized approach to the specification and verification of design transformations on control data flow graphs which is independent of a specific behavioral model or graph size has been developed.As a demonstration of an industrial application we use a video processing algorithm needed for the conversion from a line-interlaced to progressively scanned video format. Both a video signal processor-based prototype implementation as well as a very efficient full custom implementation are developed starting from a single high-level behavioral specification of the algorithm in VHDL. Results are compared with those previously obtained using different tools and methodologies.

A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits

This paper describes a new scheduling algorithm for automatic synthesis of the control blocks of control-dominated circuits. The proposed scheduling algorithm is distinctive in its approach to partition a control/data flow graph (CDFG) into an equivalent state transition graph. It works on the CDFG to exploit operation relocation, chaining, duplication, and unification. The optimization goal is to schedule each execution path as fast as possible. Benchmark data shows that this approach achieved better results over the previous ones in terms of the speedup of the circuit and the number of states and transitions.

The determination of the cycle length in high level synthesis

In high level synthesis, previously presented systems [1–5] have always determined the cycle length of one control step by straightforward strategies. In this paper, we explore how altering the magnitude of the cycle length influences the scheduled result in terms of resources needed, total execution time and the complexity of the control unit. This paper first clearly formulates the problem of determining the cycle length as a system of integer equations. Then, based on number theory, an efficient and effective algorithm is developed to determine the optimal cycle length such that the scheduled result of the given CDFG (Control Data Flow Graph) in the majority of cases can be markedly improved. Finally, some experiments including benchmarks are given to demonstrate our results.

SALSA: a new approach to scheduling with timing constraints

An approach to scheduling in high-level synthesis that meets timing constraints while attempting to minimize hardware resource costs is described. The approach is based on a modified control/data-flow graph (CDFG) representation called SALSA. SALSA provides a simple move set that allows alternative schedules to be quickly explored while maintaining timing constraints. It is shown that this move set is complete in that any legal schedule can be reached using some sequence of move applications. In addition, SALSA provides support for scheduling with conditionals, loops, and subroutines. Scheduling with SALSA is performed in two steps. First, an initial schedule that meets timing constraints is generated using a constraint solution algorithm adapted from layout compaction. Second, the schedule is improved using the SALSA move set under control of a simulated annealing algorithm. Results show the scheduler's ability to find good schedules which meet timing constraints in reasonable execution times.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A high level synthesis algorithm including control constraints

Data path synthesis and control part synthesis are strongly interdependent. This fact vindicates a novel approach for early control optimization in terms of the number of commands, while data path is still at the very beginning stage of its synthesis. The scheduling algorithm is based on stochastic searching guided by a cost function to be minimized. In order to take into account the control aspect optimization a simple term is added to the cost function used in the scheduling process. This term is merely a statistical measure of the Control Data Flow Graph regularity, since our conjecture is that the more regular the CDFG, the simpler the Control Part. Moreover, this simple extra measure of regularity during scheduling permits to perform scheduling and binding, in sequence, without decreasing the solution quality.

Applicability of a Subset of Ada as an Algorithmic Hardware Description Language for Graph-Based Hardware Compilation

The requirements of an algorithmic level hardware description language can be met by a software language with only limited feature enhancement. This paper discusses the feasibility of using a subset of Ada as a hardware description language. Methods are presented for realizing the extra features required for hardware description within the syntax of Ada. This allows the compiled Ada program to act as a functional simulator. Our particular context for hardware description is as a source language for a hardware compiler. Rules are presented for translating a circuit described in the Ada subset onto a control/data-flow graph (CDFG), our intermediate level form.