Si Control Devices Research Articles

Metal insulator semiconductor field effect transistors with thin strained Ge film

This paper focuses on a strained Ge channel N type metal-insulator semiconductor transistor and demonstrates the biaxial compressive strain thin Ge films grown on Si substrates by ultra-high vacuum chemical vapor deposition. The performance enhancement is also exhibited. The drive current and subthreshold swing of the strained Ge transistor is seen to be better than the Si control device. The on-off current ratio reaches an order of eight without sacrificing the leakage current. For mobility enhancement, the Ge device exhibits an enhancement greater than 100% compared with the Si device. The development of strained Ge N type and P type metal-insulator semiconductor transistors with thin Ge film for complementary metal-oxide semiconductor (CMOS) technology without the III-V material may allow nanoscale feasibility for future generations and be compatible with current CMOS processes.

Characterization of silicon–carbon alloy materials for future strained Si metal oxide semiconductor field effect transistors

N type metal oxide semiconductor field effect transistors (NMOSFETs) using strained silicon–carbon alloy (Si1−xCx) surface channels are reported in this work. Tensile-strained Si1−xCx layers with substitutional carbon content up to ~1% were epitaxially grown on (100) Si substrates by ultra-high vacuum chemical vapor deposition, using silane and methylsilane as the silicon and carbon sources, respectively. NMOSFETs were fabricated using standard MOS processing with reduced thermal treatment in order to minimize the possibility of strain relaxation. A reciprocal space mapping method was used to analyze strain distribution in the silicon–carbon alloy thin films on Si substrates. The election inversion layer mobilities of the Si1−xCx and Si control devices at room temperature are comparable. This is in contrast to the electron mobility enhancement observed in NMOSFETs fabricated using tensile-strained Si grown on relaxed Si1−xGex layers. At low temperatures, the electron inversion layer mobility of Si1−xCx devices is lower than that of the Si controls, and appears to be affected by Coulomb as well as possibly by random alloy scattering.

High-Mobility TaN/$\hbox{Al}_{2}\hbox{O}_{3}$/Ge(111) n-MOSFETs With RTO-Grown Passivation Layer

We report the fabrication of high-electron-mobility Ge(III) n-MOSFETs using a novel and simple approach to passivate a Ge surface by rapid thermal oxidation (RTO). A thin interfacial GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer is formed by RTO, which passivates the high-k/Ge interface. The GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -passivated n-MOSFETs fabricated using a gate-first self-aligned process with high-k/metal gate demonstrate a high peak effective mobility (μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ~ 713 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> · V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> · s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> ) with ~2x enhancement over control Si(100) devices. Moreover, at a drain bias of 1 V and at a gate overdrive of 1.2 V, Ge MOSFETs (L ~ 75 μm) show a drive current of ~1.1 mA/ mm, which is ~1.6 X higher than that of the control Si devices. In addition, a good subthreshold slope of ~130 mV/decade and an Jon/-Toff ratio ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> were achieved using the GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interfacial layer formed by RTO.

Wire textured, multi-crystalline Si solar cells created using self-assembled masks

We have developed an inexpensive and scalable method to create wire textures on multi-crystalline Si solar cell surfaces for enhanced light trapping. The wires are created by reactive ion etching, using a monolayer high self-assembled array of polymer microspheres as an etch mask. Chemical functionalization of the microspheres and the Si surface allows the mask to be assembled by simple dispensing, without spin or squeegee based techniques. Surface reflectivities of the resulting wire textured multi-crystalline solar cells were comparable to that of KOH etched single crystal Si (100). Electrically, the solar cells exhibited a 20% gain in the short circuit current compared to planar multicrystalline Si control devices, and a relative increase of 7-16% in the "pseudo" efficiencies when the series resistance contributions are extracted out.

Improved self-gain in deep submicrometer strained silicon–germanium pMOSFETs with HfSiO x/TiSiN gate stacks

The self-gain of surface channel compressively strained SiGe pMOSFETs with HfSiO x /TiSiN gate stacks is investigated for a range of gate lengths down to 55 nm. There is 125% and 700% enhancement in the self-gain of SiGe pMOSFETs compared with the Si control at 100 nm and 55 nm lithographic gate lengths, respectively. This improvement in the self-gain of the SiGe devices is due to 80% hole mobility enhancement compared with the Si control and improved electrostatic integrity in the SiGe devices due to less boron diffusion into the channel. At 55 nm gate length, the SiGe pMOSFETs show 50% less drain induced barrier lowering compared with the Si control devices. Electrical measurements show that the SiGe devices have larger effective channel lengths. It is shown that the enhancement in the self-gain of the SiGe devices compared with the Si control increases as the gate length is reduced thereby making SiGe pMOSFETs with HfSiO x /TiSiN gate stacks an excellent candidate for analog/mixed-signal applications.

Enhanced Hole Transport in Short-Channel Strained-SiGe p-MOSFETs

Hole mobility and velocity are extracted from scaled strained-Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.45</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.55</sub> channel p-MOSFETs on insulator. Devices have been fabricated with sub-100-nm gate lengths, demonstrating hole mobility and velocity enhancements in strained- Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.45</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.55</sub> channel devices relative to Si. The effective hole mobility is extracted utilizing the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dR</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dL</i> method. A hole mobility enhancement is observed relative to Si hole universal mobility for short-channel devices with gate lengths ranging from 65 to 150 nm. Hole velocities extracted using several different methods are compared. The hole velocity of strained-SiGe p-MOSFETs is enhanced over comparable Si control devices. The hole velocity enhancements extracted are on the order of 30%. Ballistic velocity simulations suggest that the addition of (110) uniaxial compressive strain to Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.45</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.55</sub> can result in a more substantial increase in velocity relative to relaxed Si.

Performance Enhancements in Scaled Strained-SiGe pMOSFETs With $ \hbox{HfSiO}_{x}/\hbox{TiSiN}$ Gate Stacks

The short-channel performance of compressively strained Si0.77Ge0.23 pMOSFETs with HfSiOx/TiSiN gate stacks has been characterized alongside that of unstrained-Si pMOSFETs. Strained-SiGe devices exhibit 80% mobility enhancement compared with Si control devices at an effective vertical field of 1 MV middotcm-1. For the first time, the on-state drain-current enhancement of intrinsic strained-SiGe devices is shown to be approximately constant with scaling. Intrinsic strained-SiGe devices with 100-nm gate lengths exhibit 75% enhancement in maximum transconductance compared with Si control devices, using only ~20% Ge (~0.8% strain). The origin of the loss in performance enhancement commonly observed in strained-SiGe devices at short gate lengths is examined and found to be dominated by reduced boron diffusivity and increased parasitic series resistance in compressively strained SiGe devices compared with silicon control devices. The effective channel length was extracted from I- V measurements and was found to be 40% smaller in 100-nm silicon control devices than in SiGe devices having the same lithographic gate lengths, which is in good agreement with the metallurgical channel length predicted by TCAD process simulations. Self-heating due to the low thermal conductivity of SiGe is shown to have a negligible effect on the scaled-device performance. These findings demonstrate that the significant on-state performance gains of strained-SiGe pMOSFETs compared with bulk Si devices observed at long channel lengths are also obtainable in scaled devices if dopant diffusion, silicidation, and contact modules can be optimized for SiGe.

1/ f noise study on strained Si 0.8Ge 0.2 p-channel MOSFETs with high-k/poly Si gate stack

The study of the low frequency (1/ f) noise of strained Si 0.8Ge 0.2 p-channel MOSFETs with poly Si/HfSiO x gate stacks is presented. Apart from the reduced threshold voltage, improved maximum transconductance and increased low-field mobility offered by the strained SiGe, the 1/ f noise was observed to be considerably lower than in the Si control devices. The 1/ f noise characteristics were likely originated by carrier number fluctuations (Δ n model) for both the strained SiGe and Si control pMOSFETs. This is consistent with the proposed model for high-k MOSFETs based on correlated number-mobility fluctuations theory. Despite the much worse high-k gate stack quality characterized by gate leakage and charge pumping, the relative reduction (up to 10×) in the noise for the strained SiGe over Si control with high-k is preserved, as was observed in the past for strained SiGe and Si control devices having SiO 2 gate dielectric, likely attributed to the existence of the Si cap layer.

Impact of Ge Content on Flicker Noise Behavior of Strained-SiGe p-Type Metal–Oxide–Semiconductor Field-Effect Transistors

The DC characteristic and low-frequency (1/ f) noise behavior of strained-Si1-xGex p-type metal–oxide–semiconductor field-effect transistors (pMOSFETs) with 15 and 30% Ge channel have been investigated and compared with those of Si control counterparts. Enhancement in effective hole mobility of 24 and 45% were obtained in strained-SiGe devices with a 15 and 30% Ge channel, respectively. The strained-SiGe pMOSFETs with a higher Ge buried channel exhibit lower 1/ f noise, indicating that more carriers are confined in the SiGe channel and interface scattering is remote. Moreover, we also found that the Ge concentration plays an important role in the noise mechanism. A new observation shows that carrier number fluctuation is more suitable for interpreting the mechanism of 1/ f noise in strained-SiGe devices with 30% Ge channel, while both number fluctuation noise and mobility fluctuation noise are likely to contribute to the characteristics of SiGe pMOSFETs with 15% Ge and the Si control device.

Si / Si 0.2 Ge 0.8 / Si quantum well Schottky barrier diodes

The hole confinement due to the valence band offset of the Si/SiGe/Si quantum well causes the shrinkage of depletion region for the n-type Si/Si0.2Ge0.8/Si Schottky barrier diodes with Pt gates. The capacitance of Si/Si0.2Ge0.8/Si Schottky diodes has approximately two times the capacitance of the control Si device. Moreover, the high electrical field leads to a high thermionic-field emission current and a large image-force lowering at both reverse and forward biases. The conventional capacitor-voltage method cannot be used to accurately measure the barrier height of Si/SiGe/Si quantum well Schottky diodes due to the shrinkage of depletion region.

Strained-Si nMOSFET formed on very thin SiGe buffer layer fabricated by ion implantation technique

We fabricated strained-Si n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) on very thin SiGe buffer layers. The ion implantation technique was successfully employed and the Si 0.83Ge 0.17 relaxed layer with the thickness as small as 100 nm was obtained. As a result, 2.0 times drive current, 2.6 times transconductance and 1.6 times mobility enhancements over the control Si device were obtained, indicating that the ion implantation technique is very promising for realization of high performance strained-Si devices on very thin SiGe virtual substrates.

Ge wire MOSFETs fabricated by three-dimensional Ge condensation technique

We propose a novel method to form Ge nano-wire structures by utilizing a three-dimensional (3D) Ge condensation technique. Since this method needs only top-down and Si compatible processes, Ge nano-wire MOSFETs fabricated by this technique are suitable for actual LSI applications. Based on this concept, we have fabricated SiGe on insulator wire pMOSFETs with Ge content up to 92% and diameter down to 35 nm. 3× enhancement of transconductance against a control Si device has been demonstrated in pMOSFETs with Ge content of 79%, though the performance enhancement in the highest Ge content device has not been obtained yet because of the non-optimized 3D Ge condensation processes. Further performance enhancement is expected after optimizing 3D Ge condensation processes especially for higher Ge content SiGe channels.

Characteristics of Strained-Si nMOSFET Using Nickel Silicide Source/Drain

In this paper, the optimum shallow trench isolation, together with Ni silicide technology, is introduced to implement the strained-Si negative-metal-oxide semiconductor field-effect transistors (nMOSFETs) and shows well-behaved characteristics using the complementary metal-oxide semiconductor process. It is found that the strained-Si nMOSFET provides a strong enhancement (up to 75%) in long-channel mobility when compared to a Si control device. The increased mobility behavior is translated into a 70% higher driving current for the large-area devices and a 51% higher driving current for device pattern down to . Significant pattern effects for strained-Si devices with NiSi is observed, which is the result of the formation of nonuniform Ni silicide at the source/drain region and is responsible for the increased source/drain resistance and off-state leakage.

Super critical thickness SiGe-channel heterostructure p-type metal-oxide-semiconductor field-effect transistors using laser spike annealing

Strained Si/strained Si0.3Ge0.7/relaxed Si0.7Ge0.3 heterostructure p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) with high mobility and low leakage are demonstrated using laser spike annealing, despite a strained Si0.3Ge0.7 channel thickness that is two times the equilibrium critical thickness. Measured hole mobility is enhanced four times for Si0.3Ge0.7 channel MOSFETs relative to Si control devices, at an inversion charge density of 1013cm−2. For supercritical thickness strained SiGe channel films, the use of laser spike annealing allows source/drain annealing at significantly higher temperatures than is possible with rapid thermal annealing (e.g., 975 versus 800°C), while achieving superior leakage characteristics. For laser spike annealing temperatures above 1000°C, mobility is found to degrade due to partial relaxation and dislocation formation in the Si0.3Ge0.7 channel.

Improved gate oxide integrity of strained Si n-channel metal oxide silicon field effect transistors using thin virtual substrates

This work presents a detailed study of ultrathin gate oxide integrity in strained Si metal oxide silicon field effect transistors (MOSFETs) fabricated on thin virtual substrates aimed at reducing device self-heating. The gate oxide quality and reliability of the devices are compared to those of simultaneously processed Si control devices and conventional thick virtual substrate devices that have the same Ge content (20%), strained Si channel thickness, and channel strain. The thin virtual substrates offer the same mobility enhancement as the thick virtual substrates (∼100% compared to universal mobility data) and are effective at reducing device self-heating. Up to 90% improvement in gate leakage current is demonstrated for the strained Si n-channel MOSFETs compared to that for the bulk Si controls. The lower leakage arises from the increased electron affinity in tensile strained Si and is significant due to the sizeable strain generated by using wafer-level stressors. The strain-induced leakage reductions also lead to major improvements in stress-induced leakage current (SILC) and oxide reliability. The lower leakage current of the thin and thick virtual substrate devices compares well to theoretical estimates based on the Wentzel–Kramers–Brillouin approximation. Breakdown characteristics also differ considerably between the devices, with the strained Si devices exhibiting a one order of magnitude increase in time to hard breakdown (THBD) compared to the Si control devices following high-field stressing at 17 MV cm−1. The strained Si devices are exempted from soft breakdown. Experimental based analytical leakage modeling has been carried out across the field range for the first time in thin oxides and demonstrates that Poole–Frenkel (PF) emissions followed by Fowler–Nordheim tunneling dominate gate leakage current at low fields in all of the devices. This contrasts to the frequently reported assumption that direct tunneling dominates gate leakage in ultrathin oxides. We also show that PF emissions are reduced in strained Si devices compared to bulk Si devices. The gate leakage, interface trap density, bulk oxide traps, breakdown characteristics, and SILC are further improved in the thin virtual substrate devices compared to the thick virtual substrate devices. The difference is attributed to surface roughness. The thick virtual substrates exhibit characteristic cross-hatching morphology, whereas the thin virtual substrates do not since they relax primarily through point defects rather than misfit dislocations. Virtual substrate growth techniques that minimize surface roughness will, therefore, benefit all state-of-the-art devices featuring strained Si, strained Si-on-insulator, and strained Ge that are generated by using relaxed SiGe platforms.

Control of Self-Heating in Thin Virtual Substrate Strained Si MOSFETs

This paper presents the first results and analysis of strained Si n-channel MOSFETs fabricated on thin SiGe virtual substrates. Significant improvements in electrical performance are demonstrated compared with Si control devices. The impact of SiGe device self-heating is compared for strained Si MOSFETs fabricated on thin and thick virtual substrates. This paper demonstrates that by using high-quality thin virtual substrates, the compromised performance enhancements commonly observed in short-gate-length MOSFETs and high-bias conditions due to self-heating in conventional thick virtual substrate devices are eradicated. The devices were fabricated with a 2.8-nm gate oxide and included NiSi to reduce the parasitic series resistance. The strained layers grown on the novel substrates comprising 20% Ge did not relax during fabrication. Good on-state performance, off-state performance, and cross-wafer uniformity are demonstrated. The results show that thin virtual substrates have the potential to circumvent the major issues associated with conventional virtual substrate technology. A promising solution for realizing high-performance strained Si devices suitable for a wide range of applications is thus presented

Growth of high-quality relaxed SiGe films with an intermediate Si 1− yC y layer for strained Si n-MOSFETs

High quality and thin relaxed SiGe films were grown on Si (0 0 1) using ultra high vacuum chemical vapor deposition (UHV/CVD) by employing an intermediate Si 1− y C y layer. The Si 1− y C y /SiGe bilayer was found to change mechanism of relaxation in the SiGe overlayer. Compared with the samples with a Si layer, the equilibrium critical thickness of top SiGe films with rough surface by introducing an intermediate Si 0.986C 0.014 layer are drastically reduced; this result was attributed to larger tensile stress in the inserted Si 0.986C 0.014 layer. With a 210-nm-thick Si 0.8Ge 0.2 overlayer, this Si 0.8Ge 0.2/Si 0.986C 0.014/Si 0.8Ge 0.2 heterostructure has a threading dislocation density (TDs) less than 1 × 10 5 cm −2 and a residual strain of 30%. The root mean square (RMS) of surface roughness for this sample was measured to be about 1.8 nm. In this SiGe/Si 1− y C y /SiGe structure, C atoms in the intermediate Si layer will improve the relaxation of thin SiGe overlayer, however, the relaxation for the 700-nm-thick SiGe overlayer is independent of the addition of C. The point defects rich Si 0.986C 0.014 layer plays the role to confine the misfit dislocations, which formed at the interface of the top Si 0.8Ge 0.2 and the Si 0.986C 0.014 layer, and blocked the propagation of TDs. Strained-Si n-channel metal-oxide-semiconductor transistors ( n-MOSFETs) with a 210-nm-thick Si 0.8Ge 0.2 overlayers as buffer were fabricated and examined. Drain current and effective electron mobility for the strained-Si device with this novel substrate technology was found to be 100 and 63% higher than that of control Si device. Our results show that thin relaxed Si 0.8Ge 0.2 films with the intermediate Si 0.986C 0.014 layer serve as good candidates for high-speed strained-Si devices.

Application of Microwave Plasma Gate Oxidation to Strained-Si/SiGe-on-Insulator

We have applied microwave-plasma oxidation at 400 °C to the gate oxide formation of a strained-Si/SiGe-on-insulator (SGOI) metal–oxide–semiconductor field-effect transistor (MOSFET). Application of low-temperature wet-O2 treatment to plasma oxide on strained-Si/Si0.85Ge0.15 significantly reduces the density of interface states and provides a 72% enhancement in transconductance compared with Si control devices. In the case of a thermally oxidized device, the junction leakage current was increased due to Ge condensation up to 50% Ge at the mesa island edge. On the other hand, the plasma oxide device showed a leakage current two orders of magnitude lower than that of the thermally oxidized device, owing to the suppression of the Ge condensation.

BC high-/spl kappa//metal gate Ge/C alloy pMOSFETs fabricated directly on Si (100) substrates

Buried-channel (BC) high-/spl kappa//metal gate pMOSFETs were fabricated on Ge/sub 1-x/C/sub x/ layers for the first time. Ge/sub 1-x/C/sub x/ was grown directly on Si (100) by ultrahigh-vacuum chemical vapor deposition using methylgermane (CH/sub 3/GeH/sub 3/) and germane (GeH/sub 4/) precursors at 450/spl deg/C and 5 mtorr. High-quality films were achieved with a very low root-mean-square roughness of 3 /spl Aring/ measured by atomic force microscopy. The carbon (C) content in the Ge/sub 1-x/C/sub x/ layer was approximately 1 at.% as measured by secondary ion mass spectrometry. Ge/sub 1-x/C/sub x/ BC pMOSFETs with an effective oxide thickness of 1.9 nm and a gate length of 10 /spl mu/m exhibited high saturation drain current of 10.8 /spl mu/A//spl mu/m for a gate voltage overdrive of -1.0 V. Compared to Si control devices, the BC pMOSFETs showed 2/spl times/ enhancement in the saturation drain current and 1.6/spl times/ enhancement in the transconductance. The I/sub on//I/sub off/ ratio was greater than 5/spl times/10/sup 4/. The improved drain current represented an effective hole mobility enhancement of 1.5/spl times/ over the universal mobility curve for Si.

Subnanometer-equivalent-oxide-thickness germanium p-metal-oxide-semiconductor field effect transistors fabricated using molecular-beam-deposited high-k/metal gate stack

Metal-oxide-semiconductor field effect transistors (MOSFET) with a thin high-k dielectric were fabricated on bulk n-type germanium substrates. Surface oxides were thermally desorbed in situ by heating the substrates under ultrahigh vacuum conditions. First an ultrathin passivating layer was formed by evaporating germanium in the presence of atomic oxygen and nitrogen supplied from a remote radio frequency plasma source. Subsequently, the HfO2 dielectric was deposited by evaporating hafnium in the presence of atomic oxygen. An in situ TaN metal gate was similarly deposited. Long channel devices were fabricated using a standard process flow. These devices exhibited a low equivalent oxide thickness (EOT) of 0.7nm with gate leakage less than 15mA∕cm2 at VFB+1V. Device mobility was extracted from Is-Vg and split C-V characteristics. Results indicate a 2× mobility enhancement in Ge p-MOSFET devices compared to Si control devices. The demonstration of subnanometer EOT suggests that high-k gate dielectrics on germanium are scalable to low EOT and suitable for use in ultrascaled MOSFET devices.