Control Of Short Channel Effects Research Articles

Impact of PVT Variations on Optimizing Silicon Power

The scaling of CMOS technology faces challenges as the demand rises, but FinFETs emerging as a vital alternative for 22nm technology node and lower. Otherwise, FinFETs tend to have multiple PVT variations, making static timing analysis (STA) more flexible and suitable to analyze the timing delay of the logic generation. Device simulation and statistical temporal analysis are used to derive PVT variation models for FinFET-based standard cell designs. Mixing different FinFET design styles shows promise in optimizing delays and leakage, as FinFETs offer better control of short-channel effects and processing scalability. Furthermore, lowering clock skew is also a prime design aspect to consider. However, as technology scales to smaller devices, process, voltage, and temperature (PVT) variations make minimizing clock distortion very difficult. To mitigate the effects of PVT variations, many previous works proposed a Post Silicon Tuning (PST) architecture to dynamically balance the skew of the clock tree. In this paper, we will disclose the details of clock tree synthesis optimizations and FinFET logic developments minimizing PVT variations.

Demonstration of Germanium Vertical Gate-All-Around Field-Effect Transistors Featured by Self-Aligned High-κ Metal Gates with Record High Performance.

A special Ge nanowire/nanosheet (NW/NS) p-type vertical sandwich gate-all-around (GAA) field-effect transistor (FET) (Ge NW/NS pVSAFET) with self-aligned high-κ metal gates (HKMGs) is proposed. The Ge pVSAFETs were fabricated by high-quality GeSi/Ge epitaxy, an exclusively developed self-limiting isotropic quasi atomic layer etching (qALE) of Ge selective to both GeSi and the (111) plane, top-drain implantation, and ozone postoxidation (OPO) channel passivation. The Ge pVSAFETs, which have hourglass-shaped (111) channels with the smallest size range from 5 to 20 nm formed by qALE, have reached a record high Ion of ∼291 μA/μm and exhibited good short channel effects (SCEs) control. The integration flow is compatible with mainstream CMOS processes, and Ge pVSAFETs with precise control of gate lengths/channel sizes were obtained.

Review of the Nanoscale FinFET Device for the Applications in Nano-regime

Background:The insatiable need for low-power and high-performance integrated circuit (IC) results in the development of alternative options for metal oxide semiconductor field effect transistor (MOSFET) in the ultra-nanoscale regime. The practical challenge of the device scaling limits the use of MOSFET for future technology nodes. ICs are equipped with billions of transistors whose size must be scaled while increasing performance. As the size of the transistor shrinks for the new technology node, the control of the gate over the channel also reduces, leading to sub-threshold leakage. The non-planar technology is the potential methodology to design the ICs for the future technology nodes. The fin-shaped field effect transistor (FinFET) is the most valuable non-planar technology. High sub-threshold slope, better short channel effect (SCE) control, high current drive strength, low dopant-prompted variations, and decreased power dissipation are the prominent features of FinFET technology.Objective:FinFET is an advanced version of MOSFET in terms of geometrical structure. Therefore, in this review paper, the different geometrical structures, working operations, design challenges, future aspects, and the different configurations of FinFETs are presented. The performance of the different configurations of a 1-bit full adder is evaluated and compared.Methods:An overview of FinFET evolution from the planar MOSFET, along with its architecture supported by the requisite equations, is presented in the paper. Besides this, it also gives an insight into the circuit simulation using the FinFETs for the process voltage temperature (PVT) variations, width quantization, design challenges, and the future of FinFETs. A comparative study of FinFET-based 1-bit full adder using various techniques is done to compute and compare the leakage power, delay, and power delay product (PDP).Results:The full adders using FinFETs show less leakage power and PDP. The AND-OR logicbased hybrid full adder using FinFETs shows the least energy consumption per switching. Fin- FET-based gate diffusion input adder shows a 74 % reduction in dynamic power compared to the full adder using MOSFET technology. The low power FinFET-based full adder shows a 54.16 % reduction in leakage power compared to the MOSFET-based full adder. The results signify the effect of multi-gates in curbing the leakage power dissipation.Conclusion:MOSFET faces the practical challenge of device scaling and SCEs at lower technology nodes. It initiates the multi-gate technology for future system generation. FinFET has the capability to design low-power and high-performance circuits in an ultra-nanoscale regime. The geometrical structure of FinFET plays a key role to improve the performance metrics in an ultrananoscale regime.

TCAD-Based Assessment of the Lateral GAA Nanosheet Transistor for Future CMOS

A physical assessment of the lateral gate-all-around (GAA) nanosheet transistor (NSFET) at the G40M16 node (gate length = 12 nm projected for 2028) of the newly defined beyond-Moore International Roadmap for Devices and Systems [~5 nm node of the predecessor International Technology Roadmap for Semiconductors (ITRS)], supported by 3-D numerical device simulations and based on a proposed per-footprint scheme, is presented. The traditional evaluation scheme to gauge the performance of the transistor “per effective channel width” is shown to be improper due to pervasive bulk inversion. Bulk inversion, along the width of the nanosheet and at its ends, obfuscates the dependence of current on sheet/channel width and undermines the presumed added benefit of short-channel effect (SCE) control in the GAA device. The NSFET provides a flexible sheet width, as opposed to that of the FinFET with discrete fins, but the allowed range of sheet width is limited due to significant parasitic capacitance at a relatively narrow width and degraded SCE control and increased resistance for desired wide width. Furthermore, the nanosheet (NS) device density is undermined at a narrow width, especially for decreasing pitch. The FinFET is shown to be a favorable alternative to the NSFET even at the G40M16 node.

In1 − xGaxAs Double Metal Gate-Stacking Cylindrical Nanowire MOSFET for Highly Sensitive Photo Detector

This paper proposed a highly sensitive Double Metal Gate-stacking Cylindrical Nanowire-MOSFET (DMG CL-NWMOSFET) photosensor by using In1 − xGaxAs. For the best control of short channel effects (SCEs), a double metal gate has been utilized and for efficient photonic absorption, III-V compound has been utilized as channel material. The currently available Conventional Filed-Effect-Transistors (CFET) based photosensor have been used threshold voltage as parameter for the calculation of sensitivity, but in the proposed photosensor, change in subthreshold current has been used as the detecting parameters for sensitivity (Iillumination/Idark). The scientifically electrons study and the photo-conductive characteristics of In1 − xGaxAs CL-NWMOSFET are taken through Silvaco Atlas Tools with two work-functions 4.83 eV and 4.41 eV of metal 1 and metal 2 respectively. After the analysis of In1 − xGaxAs dual Metal Gate Stacking Cylindrical NWMOSFET responds to detectable spectrum (~ 450 nm), incidents light with constant, reversible and fast response by responsivity (4.3 mAW− 1), high Iillumination/Idark (1.36 * 109) and quantum-efficiency (1.12 %). The obtained results of In1 − xGaxAs DMG CL-NWMOSFET based photodetectors have the potential in optoelectronics applications.

Silicon Nanowire Parameter Extraction Using DFT and Comparative Performance Analysis of SiNWFET and CNTFET Devices

The performance and scalability of silicon nanowire field-effect transistor (SiNWFET) and carbon nanotube field-effect transistor (CNTFET) with surround gate geometry were studied using such tools as material exploration and design analysis (MedeA) and device modeling and simulation SilvacoTCAD. The SiNWFET and CNTFET with gate-all-around (GAA) structure offer good gate electrostatic control, high On-current and better suppression of short-channel effects with complete encirclement of the device channel. Rather than using the bulk properties of silicon, estimation of properties silicon nanowire (SiNW) was made using MedeA VASP tool based on density functional theory (DFT). In this study, the device input (ID–VGS) and output (ID–VDS) have been analyzed and parameters like threshold voltage, IOn/IOff ratio, drain induced barrier lowering and sub-threshold slope extracted, and comparison is made between SiNWFET and CNTFET devices. The results point towards the DFT-based material parameter estimation to incorporate the quantum effects and use of SiNW/CNT-based GAA structure below 10 nm to meet scaling targets. The results suggest that the SiNWFET and CNTFET device with GAA geometry could be a better alternative to conventional MOSFETs and FinFET for numerous high-performance and low-power device applications.

(Invited) Device Scalability of InGaZnO TFTs for Next-Generation Displays

Amorphous oxide semiconductor thin-film transistors (TFTs) are used as the backplane for large-screen, high-resolution OLED and LCD displays. Amorphous InGaZnO (a-IGZO) TFTs are widely used in commercialized TVs, tablets, and wearable displays for its good device performance, stability, and process controllability. Also, due to its extremely low off-current, a-IGZO TFTs are used for low refresh rate and low-power displays. Furthermore, a-IGZO TFTs have a low process temperature, enabling fabrication on various substrates (including flexible films), and also hybrid integration with other backplane technologies, such as LTPS or Si CMOS. By taking advantage of the low off-current and low process temperature, a-IGZO can be monolithically integrated in the back-end of Si CMOS for low-power applications, as well as embedded memories for long retention and non-volatile operation. There are many incentives to shorten the channel length of IGZO TFTs. First, shorter channels can boost the current without incorporating high-mobility oxides, which usually suffer from reliability issues and small process margin. When gate drivers are integrated directly onto the panel, larger currents allow smaller device footprint, thinner bezel width, and less dead space. Second, transistors with sub-micron pitch are desired to bridge the pixel gap between smartphone displays and micro-displays, and to be used for consumer AR/VR displays with > 1000 ppi. Third, reduced device length is necessary for fine-grained integration with nanoscale CMOS. However, short-channel TFTs suffer from short-channel effects (SCE). For example, threshold voltage (Vt) roll-off, where the Vt reduces for short channel lengths, causes device variability and hence, worse process tolerance. Therefore understanding and control of SCE is critical for designing and fabricating short-channel TFTs.In this paper, we study the device scalability of short-channel IGZO TFTs down to 1μm. The electrical channel length (Leff) is not the same as the gate length (Lg), and is determined by the carrier profile at the gate edges. Leff ( = Lg - ΔL) is obtained by the transmission line method (TLM), or shift-and-ratio method. Accurate ΔL extraction is important in determining the exact device mobility. Since scalability is related to the carrier concentration profile, it is strongly dependent on the process, where oxygen and hydrogen content varies with process conditions, and profiles change during thermal treatments. Devices with higher carrier concentration generally result in larger ΔL and worse SCE. Device simulations using TCAD shows the dependence on overlap (Lov), slope of carrier Gaussian decay (Xc), channel carrier concentration (Nch) on the Leff and SCE. TCAD simulation results are matched with experimental measurements for verification of the simulation models and parameters used. We define a critical carrier concentration (Ncrit) which defines the Leff. Changing the carrier profile while maintaining Ncrit results in little difference in ΔL. For devices with an underlap, similar ΔL values result in similar SCE. However, for devices with an overlap, even with the similar ΔL values, SCE is more sensitive to carrier profile at the channel edges. This study shows that SCE may be controlled through shaping of the carrier concentration profile through optimization of the device structure and process conditions allowing fabrication of short-channel TFTs with good scalability.

Design of Fin-Diode-Triggered Rotated Silicon-Controlled Rectifier for High- Speed Digital Application in 16-nm FinFET Process

The FinFET architecture has widely been used in the digital circuit application, due to the good short channel effect control and driving current boost. However, the worse thermal dispassion and smaller effective silicon volume would cause the significant impacts during the circuits under electrostatic discharge (ESD) event. Thus, the ESD protection device should be installed into the high-speed digital circuit to enhance the ESD robustness. To avoid the effect of circuit performance, the parasitic capacitance of ESD device must be as low as possible. In this article, two types of Fin-diode-triggered rotated silicon-controlled rectifier (SCR) with dual ESD current path have been proposed and verified in a 16-nm FinFET CMOS process. The proposed devices have better current-handling capability, sufficiently low parasitic, compact layout area, and low leakage current.

On the Correlation Between Static and Low-Frequency Noise Parameters of Vertical Nanowire nMOSFETs

Introduction. The Gate-All-Around (GAA) Nanowire (NW) or nanosheet (NS) architecture provides superior short-channel effects control and is widely considered as one of the most promising candidates to replace finFETs in advanced Logic technology nodes. Compared with their horizontal implementation, vertical NWs (or NSs) FETs [1] offer some clear advantages, appearing promising devices to overcome some of the limitations encountered by conventional CMOS scaling as it reaches its physical limits and faces interconnect routing congestion. They have the potential to yield smaller circuits with reduced power consumption [2], allowing relaxed Lgate without impacting the device footprint. While their fabrication is challenging, several schemes have been proposed for improved process control and device performance [1]. In this work, the static parameters of vertical NW junctionless (JL) nMOSFETs have been studied for devices with two different Replacement Metal Gate (RMG) cap layer widths (see schematics in figure 1), encapsulating the top part of the pillars during processing at the RMG module. It will be shown that this strongly impacts the static device parameters: the threshold voltage (VT), the maximum transconductance (gmmax) and the dynamic output resistance (rout). Moreover, a correlation is shown with the input-referred voltage noise Power Spectral Density (PSD) SVG at 10 Hz, which could be explained in terms of a process-induced variation in the diameter D of the NWs. Experimental. A detailed process description has been recently reported [1]. A 55 nm in situ P-doped n+ layer is deposited by CVD on a low-resistivity silicon substrate (source contact), followed by 90 nm undoped silicon and again 55 nm n+ Si. The RMG stack consists of IL-SiO2/HfO2/TiN/W. An RMG cap consisting of SiO2 is used to encapsulate the top of the pillars. Here, devices with two different cap widths and 100 wires in parallel are compared. On-wafer DC and low-frequency noise measurements have been performed using a BT1500 Parameter Analyzer and an E4727A Advanced Low-Frequency Noise Analyzer from Keysight, respectively. Measurements have been performed in linear operation at a drain voltage VDS=50 mV, while the gate voltage VGS is stepped from weak to strong inversion. Results and Discussion. Figure 1 and 2 compares the linear input ID-VGS characteristics of a set of narrow and wide cap vertical NW nFETs. While there is obvious device-to-device variability, the wide-gap devices (Fig. 2) clearly exhibit a lower VT than their narrow-gap counterparts in Fig. 1. The transconductance (gm) plots of Figs 3 and 4 reveal another trend: devices with a high VT generally exhibit a lower gmmax and vice versa. This is even so within each flavour of devices in Figs 3 and 4. As will be shown, nFETs with a high(er) VT and lower gmmax also tend to exhibit a higher rout. Finally, Figs 5 and 6 demonstrate that the corresponding SVG at f=10 Hz is smaller for the wide-cap devices, especially around VT, where the minimum noise PSD is found. As will be shown, the noise spectra are dominated by 1/f-like noise (f<1 kHz). A possible explanation of the observed parameter variations should provide a consistent picture for the reported correlations. For these particular devices, the NW doping density can be ruled out, as we are studying undoped pillars. The difference in SVG could suggest a difference in oxide/interface trap density, but this is not reflected in the subthreshold swing nor in the PBTI behaviour [1]. On the other hand, it has been reported before that the VT of NW transistors increases for reduce D [3]. This could well explain also the lower gmmax (scales with D) and the higher SVG (scales with 1/D). The different NW diameter could result from the different dummy dielectric removal [1].

Threshold Voltage Variability in Nanosheet GAA Transistors

Nanosheet gate-all-around (GAA) field-effect transistor (NSFET) is a potential replacement for the FinFET at advanced technology nodes owing to better control of short-channel effects and higher drive current. Due to the increased complexity of the GAA stacked structure, new forms of process variability come into the picture, which are dominant over the conventional process variability such as metal gate granularity (MGG) and line edge roughness (LER) for FinFETs. In this article, we show one such process variability called as metal thickness variation (MTV). MTV causes WF variations on the gates of the GAA sheet transistor and results in a significant VT variability. The impact of MTV is studied using an analytical framework. We studied three variants of NSFETs and reported variability in terms of key device design parameters such as intersheet spacing and metal thicknesses. The results presented here help in designing the process flow for a type of NSFET to minimize the VT variability.

Realization with fabrication of double-gate MOSFET based differential amplifier

This research work designed a differential amplifier with Double-Gate (DG) MOSFET which can be used in electronic devices at Micro- and Nano-technology level. The DG MOSFET has been selected due to its minimal impurity scattering, high current drive, and better control of short channel effects as compared to Diodes, BJTs, and other MOSFETs. Configurations of the differential amplifier have been considered for DG MOSFET. The DG MOSFET based differential amplifier has been analysed with its small signal model, after that it has been fabricated and tested for various parameters such as differential mode gain, common mode gain, Common Mode Rejection Ratio (CMRR), and frequency response. The testing process results the differential mode gain (differential output) −8.69 V/V, common mode voltage gain (single-ended) -0.40 V/V, CMRR 19.06 dB (single-ended output) and simulated frequency response 32 MHz.

High performance dual-gate SiGe MOSFET for radio-frequency applications

In this paper, we propose a new Si0.6Ge0.4 n-channel dual-gate metal-oxide-semiconductor field-effect transistor (DGMOS) structure for high frequency small signal applications. The gate length of the device is 60 nm and gate-oxide (SiO2) thickness is 2 nm with n+ poly-silicon as gate material. Both the gates of DGMOS are placed in the oxide-filled trenches leading to formation of dual conduction channels which enhances the drive current, gain and frequency response. Two-dimensional simulation tool (ATLAS) is used to analyse and compare the performance of the proposed structure with conventional device. The DGMOS provides 5.35 times higher current drivability, 306% improvement in peak transconductance, 114% enhancement in unity current gain cut-off frequency and 3.75 times higher oscillation frequency with good control of short channel effects in comparison to the conventional MOSFET.

Modeling of electrical behavior of undoped symmetric Double-Gate (DG) MOSFET using carrier-based approach

PurposeThis study aims to develop a compact analytical models for undoped symmetric double-gate MOSFET based on carrier approach. Double-Gate (DG) MOSFET is a newly emerging device that can potentially further scale down CMOS technology owing to its excellent control of short channel effects, ideal subthreshold slope and free dopant-associated fluctuation effects. DG MOSFET is of two types: the symmetric DG MOSFET with two gates of identical work functions and asymmetric DG MOSFET with two gates of different work functions. To fully exploit the benefits of DG MOSFETs, the body of DG MOSFETs is usually undoped because the undoped body greatly reduces source and drain junction capacitances, which enhances the switching speed. Highly accurate and compact models, which are at the same time computationally efficient, are required for proper modeling of DG MOSFETs.Design/methodology/approachThis paper presents a carrier-based approach to develop a compact analytical model for the channel potential, threshold voltage and drain current of a long channel undoped symmetric DG MOSFETs. The formulation starts from a solution of the 2-D Poisson’s equation in which mobile charge term has been included. The 2-D Poisson’s equation in rectangular coordinate system has been solved by splitting the total potential into long-channel (1-D Poisson’s equation) and short-channel components (remnant 2-D differential equation) in accordance to the device physics. The analytical model of the channel potential has been derived using Boltzmann’s statistics and carrier-based approach.FindingsIt is shown that the metal gate suppresses the center potential more than the poly gate. The threshold voltage increases with increasing metal work function. The results of the proposed models have been validated against the Technology Computer Aided Design simulation results with close agreement.Originality/valueCompact Analytical models for undoped symmetric double gate MOSFETs.

Symmetric dual gate insulator‐based FinFET module and design window for reliable circuits

High-k spacer and gate insulator materials have been exhaustively studied nowadays for the enhancement of electrostatic control and reduction of short-channel effects in scaled devices. The work presents a high-performance and charge trap tolerant FinFET module at 10 nm gate length. Dual layer gate insulator (inner low-k and outer high-k) introduces to reduce charge trapping from the channel and outside into the gate oxide. It reduces the gate leakage current by 51.6% compared to conventional FinFET. Further, they demonstrate single charge trapping (SCT) induce effects and proposed optimised high-k spacer width of the SCT tolerant design. SCT analysis is presented in different high-k spacer materials and back-gate voltages. Process variation sources such as line edge roughness and line width roughness are also analysed for the circuit design.

Analytical model development of channel potential, electric field, threshold voltage and drain current for gate workfunction engineered short channel E-mode N-polar GaN MOS-HEMT

In this paper an enhancement mode (E-mode) short channel N-polar GaN MOS-HEMT is proposed. In order to mitigate different short channel effects, workfunction engineering technique is applied to the gate electrode. An analytical model for channel potential, electric field threshold voltage and drain current is developed for the device and validated with Atlas TCAD simulation results. The variation of minimum channel potential and threshold voltage with respect to different channel lengths is also performed. It is observed that device with triple material gate shows better control of short channel effects as compared to single and double material gate based devices.

Performance Enhancement of FinFET Devices with Gate-Stack (GS) High-K Dielectrics for Nanoscale Applications

The Fin shaped Field Effect Transistors (FinFETs), are the front runner of the current sub-nanometer technology node. The semiconductor industry adopts it in high-performance (HP) and low-power (LP) applications due to greater electrostatic control and better scalability. This paper explores the numerically simulation based comparison of bulk and silicon-on-insulator (SOI) technology double gate (DG), triple gate (TG) FinFETs. The essential processing steps required to create the GS high-k dielectric bulk and SOI FinFETs are demonstrated. The electrical performance parameters of the device such as Ion/Ioff ratio, subthreshold swing (SS), and drain induced barrier lowering (DIBL) are extracted. Based on the three-dimensional (3D) ATLASTM simulation results, TG FinFET shows an ameliorated performance over DG in bulk and SOI technology as well. In order to control the short channel effects (SCEs), gate-stack (GS) high-k dielectrics are introduced with fixed thickness interfacial-layer (IL) and high-k dielectric material in between the gate material and semiconductor. The GS high-k dielectrics suppress the SCEs to large extent in both devices and technologies. The GS SOI FinFETs demonstrates the improved performance over the bulk counterpart and TG FinFET is the best among them. Further, the similar kind of investigation has been carried out for Tfin variations. These devices reveal the excellent control of SCEs when the fin is narrow. The ratio of SOI and bulk TG FinFET Ion/Ioff ratio with Tfin variations provide evidence that, the SOI based devices are competent for HP and LP applications.

High-performance GeSn photodetector and fin field-effect transistor (FinFET) on an advanced GeSn-on-insulator platform.

We report the first demonstration of high-performance GeSn metal-semiconductor-metal (MSM) photodetector and GeSn p-type fin field-effect transistor (pFinFET) on an advanced GeSn-on-insulator (GeSnOI) platform by complementary metal-oxide-semiconductor (CMOS) compatible processes. The detection range of GeSn photodetector is extended beyond 2 µm, with responsivities of 0.39 and 0.10 A/W at 1550 nm and 2003 nm, respectively. Through the insertion of an ultrathin Al2O3 Schottky-barrier-enhancement layer, the dark current IDark of the GeSn photodetector is suppressed by more than 2 orders of magnitude. An impressive IDark of ~65 nA was achieved at an operating voltage of 1.0 V. A frequency response measurement reveals the achievement of a 3-dB bandwidth of ~1.4 GHz at an illumination wavelength of 2 µm. GeSn pFinFET with fin width (Wfin) scaled down to 15 nm was also fabricated on the GeSnOI platform, exhibiting a small subthreshold swing (S) of 93 mV/decade, a high drive current of 176 µA/µm, and good control of short channel effects (SCEs). This work paves the way for realizing compact, low-cost, and multi-functional GeSn-on-insulator opto-electronic integrated circuits.

Control of short-channel effects in InAlN/GaN high-electron mobility transistors using graded AlGaN buffer

A graded AlGaN buffer is designed to realize the p-type buffer by inducing polarization-doping holes. Based on the two-dimensional device simulator, the effect of the graded AlGaN buffer on the direct-current (DC) and radio-frequency (RF) performance of short-gate InAlN/GaN high-electron mobility transistors (HEMTs) are investigated, theoretically. Compared to standard HEMT, an enhancement of electron confinement and a good control of short-channel effect (SCEs) are demonstrated in the graded AlGaN buffer HEMT. Accordingly, the pinched-off behavior and the ability of gate modulation are significantly improved. And, no serious SCEs are observed in the graded AlGaN buffer HEMT with an aspect ratio (LG/tch) of about 6.7, much lower than that of the standard HEMT (LG/tch = 13). In addition, for a 70-nm gate length, a peak current gain cutoff frequency (fT) of 171 GHz and power gain cutoff frequency (fmax) of 191 GHz are obtained in the grade buffer HEMT, which are higher than those of the standard one with the same gate length.

Consideration of UFET Architecture for the 5 nm Node and Beyond Logic Transistor

In this paper, we propose a trench MOS architecture for the upcoming 5 nm node and beyond logic transistor. The intended device has a gate formed vertically downward, with added spacers along the gate to S/D sidewall. In doing so, the recessed device having longer channel length (than the defined gate footprint) would be a constructive approach to limit the short channel effects (SCE). The novel transistor has the potential to enable the scaling of gate length (footprint) less than 10 nm and contacted gate pitch below 32 nm, resulting in the smallest active area (on-wafer footprint) for a single device. Novel process steps are simulated depicting easier fabrication while the electrical analysis shows a better electrostatic control over any unwanted leakage flows. Along with the area scaling and SCE control, the planar upper surface allows a vertical integration. Growing another flipped device on top surface permits the designer to implement a logic circuit on a footprint of a single device, achieving ~50% area gain further. TCAD based simulations were performed to design and characterize the performances of an individual device and the vertical inverter.

Statistical Optimization of FinFET Processor Architectures under PVT Variations Using Dual Device-Type Assignment

With semiconductor technology scaling to the 22nm node and beyond, fin field-effect transistor (FinFET) has started replacing complementary metal-oxide semiconductor (CMOS), thanks to its superior control of short-channel effects and much lower leakage current. However, process, supply voltage, and temperature (PVT) variations across the integrated circuit (IC) become worse with technology scaling. Thus, to analyze timing, leakage power, and dynamic power under PVT variations, statistical analysis/optimization techniques are more suitable than traditional static timing/power analysis and optimization counterparts. In this article, we propose a statistical optimization framework using dual device-type assignment at the architecture level under PVT variations that takes spatial correlations into account and leverages circuit-level statistical analysis techniques. To the best of our knowledge, this is the first work to study statistical optimization at the system level under PVT variations. Simulation results show that leakage power yield and dynamic power yield at the mean value of the baseline can be improved by up to 44.2% and 21.2%, respectively, with no loss in timing yield for a single-core processor and up to 43.0% and 50.0%, respectively, without any loss in timing yield for an 8-core chip multiprocessor (CMP), at little area overhead. Under the same (99.0%) power yield constraints, leakage power and dynamic power are reduced by up to 91.2% and 4.3%, respectively, for a single-core processor, and up to 44.6% and 12.5%, respectively, for an 8-core CMP, with no loss in timing yield. We also show that optimizations performed without taking module-to-module and core-to-core spatial correlations into account overestimate yield, establishing the importance of taking such correlations into account.