Control Circuitry Research Articles

Design of a 500 GHz Frequency Tripler With a Probe-based Idle Harmonic Control Technique

In this paper, a 500 GHz frequency tripler with an idle harmonic control technique is proposed, in which the 3rd-harmonic wave at the input port and the fundamental-wave at the output port are recycled with simple control circuitry. Especially for the output fundamental-wave, it is controlled by a carefully designed function-combined probe. Besides, both of input and output probes adopted an inline waveguide-to-microstrip transition using a wedge-waveguide iris to realize an inline input-output configuration. The designed tripler was fabricated, and measured. The measured maximum efficiency is 3% under 20 mW input power with a peak output power of 0.55 mW at 500 GHz, and the available bandwidth convers a range of 460-540 GHz. With the proposed harmonic-wave control technique, the conversion efficiency of the tripler was improved. The good output performance of the 500 GHz tripler verifies the effectiveness of the proposed idle harmonic control technique and function-combined design concept.

Design of a Double-Sided LCLC-Compensated Capacitive Power Transfer System With Predesigned Coupler Plate Voltage Stresses

A high-performance capacitive power transfer (CPT) system is expected to achieve the load-independent constant output, near-zero reactive power, and soft switching of power switches simultaneously, resulting in a reduced power stage, simple control circuitry, and minimum component ratings. However, a well-compensated CPT system still suffers very-high-voltage stresses among not only the main coupled plates but also the leakage coupled plates due to the small coupling and edge emission, which increases the risk of air breakdown and deteriorate the electromagnetic interference (EMI) issue. To solve this problem, the voltage stresses among such coupler plates should be predesigned at an acceptable level. This article systematically analyzes the characteristics of a double-sided <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LCLC$ </tex-math></inline-formula> -compensated CPT converter that is proven to have enough design freedom providing predesigned voltage stresses for two kinds of coupled plates. Also, three operating frequencies with load-independent constant current (CC) output and input zero-phase angle (ZPA) are found. Without reactive power in the circuit, a parameter design method is proposed for the double-sided <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LCLC$ </tex-math></inline-formula> -compensated CPT converter at each frequency to satisfy the desired CC output and the predesigned voltage limitations. In this way, the breakdown and EMI issues can be well mitigated by the intended design, and this method can also be extended to other CPT circuits. Finally, a CPT prototype is built to verify the theoretical analysis with the predesigned voltage stresses among the coupler plates.

Modified Efficient OMS LUT Design for Memory-Based Multiplication

This paper proposes an efficient LUT (Look-Up-Table) design called Efficient EOMS (Efficient-OMS Design) for memory-based operations. This proposed design can be used for FPGA implementation as well as ASIC. The proposed design is a better choice than ordinary OMS (Odd Multiplier Store) and is preferred in many DSP calculations where one of the inputs to the filter coefficients is fixed. In this design (N+1), the possible product terms of the input multiplicands with fixed coefficients are stored directly in memory. Doing so allows for a simpler and faster design, unlike the previous proposal OMS (Odd Multiple Storage).Designs that extract odd multiples of the product term can significantly reduce path delay and area complexity with very simple control circuitry. Using (N+1) technology can significantly reduce the area compared to ordinary OMS technology. Additionally, the EOMS technical design is coded in Verilog and simulated and synthesized using Xilinx tools.

Design and investigation of a triple boost multilevel inverter with self‐balanced switched capacitors and reduced voltage stress

AbstractMultilevel inverters (MLI) play a key role in various medium voltage and high power industrial applications. This paper proposes a triple boost multilevel inverter (TBMLI) comprising switched capacitors. The special features of the proposed circuit are three times boosted output voltage, reduced voltage stress on switches, and the presence of a single dc source. Moreover, the self‐balancing in the capacitors voltage which eliminates the need of auxiliary control circuitry and reduced number of overall components also add to the salient qualities of proposed MLI. The simulation has been done using MATLAB/Simulink, whereas the loss analysis, describing the distribution of the various power loss, has been completed with the help of PLECS software. The proposed topology has a maximum efficiency of 98.3%, whereas the THD in output voltage is 13.65%. The proposed MLI is experimentally investigated to see its performance. A comparison has been conducted to assess the proposed MLI on various parameters.

Reduced Auxiliary Circuit Switch Nine-Level Inverter for Renewable Energy Applications

Multilevel Inverters (MLI) created a milestone due to increasing demand in high power medium voltage applications. To decrease the harmonics content and stress across power semiconductor devices, multilevel inverters are used. In this paper, a nine-level inverter is presented with a auxiliary circuit that requires a minimum number of power devices compared to the traditional MLI topologies. The suggested nine-level inverter's control circuitry is controlled by an ATmega8 microcontroller in this study. Opto-isolators with galvanic isolation supply the triggering pulses to operate switches. A nine-level inverter to power 100 W load is implemented using two proposed auxiliary circuits for renewable energy applications. The presented nine-level inverter's control switches are driven using a DC level shifting method. The suggested inverter's functionality and feasibility are confirmed by the experimental and simulation findings.

Multilayer Crossbar Array of Amorphous Metal-Oxide Semiconductor Thin Films for Neuromorphic Systems

A multilayer crossbar array has been developed using amorphous metal-oxide semiconductor (AOS) thin films and implemented into a neuromorphic system. The multilayer structure can be realized, because the AOS thin films can be deposited by a simple sputtering method without heat treatment, which does not damage the underlying structures. First, Au thin films are deposited by vapor evaporation as electrodes, an amorphous In-Ga-Zn-O (α-IGZO) thin film is deposited by a sputtering method as a conductance change layer, these processes are repeated, and a multilayer crossbar array is completed, where each of the three conductance change layers is sandwiched between the electrodes. Next, the multilayer crossbar array is implemented into a neuromorphic system with modified Hebbian learning, which enables autonomous learning without control circuitry, and an associative memory function is confirmed, which guarantees the possibility of further advanced functions. These results lead to astronomical large-scale integration (LSI) of synaptic elements in neuromorphic systems in the future.

A Process-Based Temperature Compensated On-Chip CMOS VHF VCRO in 130-nm Si-Ge BiCMOS by Implementing an Empirical Control Equation

This paper presents a low-power CMOS temperature and process compensated 150.9 MHz Very-high-frequency (VHF) voltage-controlled-ring-oscillator (VCRO) for on-chip integration. The design employs a CMOS temperature-sensor and novel feedback control circuitry to generate the internal control-voltage for the VCRO which ensures oscillation in the vicinity of the desired frequency despite variations in temperature. The control circuitry is the implementation of an empirical equation expressing a temperature sensor-voltage into a specific control-voltage for three different process corners using three different switches. The control-voltage calibrates against temperature variation for the specific process-corner in order to maintain the same frequency of oscillation. Simulations shows that the proposed design maintains the oscillator’s frequency within 0.39% from -10°C to 90°C. The fabricated chip implemented in 130-nm GF 8HP Si-Ge BiCMOS process, occupies an area of 0.0242-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 325 μW while operating with a 1 V supply-voltage. The performance was verified through experimental immersion of DUT (device-under-test) in a temperature-controlled water-bath in the range 22.5°C - 70°C.

Multiphase Digital Low-Dropout Regulators

In this work, multiphase digital low-dropout (MP-DLDO) regulators are designed with resonant rotary clocks (ReRoCs) in order to improve on the tradeoff of conventional DLDOs between current efficiency and transient response speed. The proposed DLDOs are multiphased, coined MP-DLDOs, designed with a clock-gated control technique to provide high current efficiencies along with transient response improvements at GHz frequency levels. The multiple phases within the MP-DLDO are served with ReRoCs that provide: 1) a robust high-speed low-power resonant clock distribution solution for the synchronous elements in the multiphase DLDO architecture and 2) improve the transient response characteristics (dynamic voltage scaling (DVS) speed and voltage ripple) while saving power in the controller circuitry. The proposed MP-DLDOs are distributed across the chip to achieve low voltage ripple. SPICE simulations are performed on post-layout, parasitic-extracted models to evaluate the MP-DLDO architecture on open-source digital cores, with performance metrics that include the voltage ripple reduction, transient response speed improvement, and power savings in the control logic. The proposed MP-DLDO architecture, evaluated on an RISC-V design, demonstrates a DVS speed of 6.5 V/μs and an output voltage ripple of 21.1 mV (38% reduction when compared to a conventional DLDO) with a sampling frequency of 2 GHz.

Editorial: Neuroimaging: How Can Clues from the Brain Help Pain Management?

Editorial: Neuroimaging: How Can Clues from the Brain Help Pain Management?

Ultra-High Extinction Dual-Output Thin-Film Lithium Niobate Intensity Modulator

A low voltage, wide bandwidth compact electro-optic modulator is a key building block in the realization of tomorrow’s communication and networking needs. Recent advances in the fabrication and application of thin-film lithium niobate, and its integration with photonic integrated circuits based in silicon make it an ideal platform for such a device. In this work, a high-extinction dual-output folded electro-optic Mach Zehnder modulator in the silicon nitride and thin-film lithium niobate material system is presented. This modulator has an interaction region length of 11 mm and a physical length of 7.8 mm. The device demonstrates a fiber-to-fiber loss of roughly 12 dB using on-chip fiber couplers and DC half wave voltage (Vπ) of less than 3.0 V, or a modulation efficiency (Vπ∙L) of 3.3 V∙cm. The device shows a 3 dB bandwidth of roughly 30 GHz. Notably, the device demonstrates a power extinction ratio over 45 dB at each output port without the use of cascaded directional couplers or additional control circuitry; roughly 31 times better than previously reported devices. Paired with a balanced photo-diode receiver, this modulator can be used in various photonic communication systems. Such a detecting scheme is compatible with complex modulation formats such as differential phase shift keying and differential quadrature phase shift keying, where a dual-output, ultra-high extinction device is fundamentally paramount to low-noise operation of the system.

PTSD symptomatology is selectively associated with impaired sustained attention ability and dorsal attention network synchronization

Posttraumatic Stress Disorder (PTSD) symptomatology is associated with dysregulated sustained attention, which produces functional impairments. Performance on sustained attention paradigms such as continuous performance tasks are influenced by both the ability to sustain attention and response strategy. However, previous studies have not dissociated PTSD-related associations with sustained attention ability and strategy, which limits characterization of neural circuitry underlying PTSD-related attentional impairments. Therefore, we characterized and replicated PTSD-related associations with sustained attention ability and response strategy in trauma-exposed Veterans, which guided characterization of PTSD-related differences in neural circuit function. In Study 1, PTSD symptoms were selectively associated with reduced sustained attention ability, but not more impulsive response strategies. In Study 2, we utilized task and resting-state fMRI to characterize neural circuitry underlying PTSD-related differences in sustained attention ability. Both PTSD symptomatology and sustained attention ability exhibited converging associations with reduced dorsal attention network (DAN) synchronization to endogeneous attentional fluctuations. Post-hoc time course analyses demonstrated that PTSD symptoms were most accurately characterized by delayed, rather than globally reduced, DAN synchronization to endogenous attentional fluctuations. Together, these findings suggest that PTSD symptomatology may selectively impair sustained attention ability by disrupting proactive engagement of attentional control circuitry.

An Ultra-Low Quiescent Current Tri-Mode DC-DC Buck Converter With 92.1% Peak Efficiency for IoT Applications

An ultra-low quiescent current tri-mode DC-DC buck converter is presented in this paper, which is able to handle a 100,000X load range. In pulse width modulation (PWM) and pulse frequency modulation (PFM) mode, adaptive on-time (AOT) V² control is utilized to achieve seamless mode transition and constant switching frequency in PWM mode. A deep green mode (DGM) is proposed for light load, where both the switching loss and the power of control circuitry are minimized. By reducing the comparator current, a delay-based hysteresis window adaptive to load current is generated, reducing the switching frequency and the loss. Meanwhile, the average current of zero current detector (ZCD) and AOT controller are reduced significantly by dynamic biasing. As a result, the efficiency of the converter is improved while maintaining a reasonable output ripple. The proposed converter is implemented in a 0.18μ m BCD technology. Experimental results show that the converter can provide a 1.6 V output from a 2.7 to 4.7V input for 1μ A to 100 mA load, while consuming only 490nA quiescent current. The proposed converter achieves a 92.1% peak efficiency and efficiency can be maintained above 80% in a load range of 20μ A to 60 mA.

Cryogenic Controller for Electrostatically Controlled Quantum Dots in 22-nm Quantum SoC

We present a fully integrated cryogenic controller for electrostatically controlled quantum dots (QDs) implemented in a commercial 22-nm FD-SOI CMOS process and operating in a quantum regime. The QDs are realized in local well areas of transistors separated by tunnel barriers controlled by voltages applied to gate terminals. The QD arrays (QDA) are co-located with the control circuitry inside each quantum experiment cell, with a total of 28 of such cells comprising this system-on-chip (SoC). The QDA structure is controlled by small capacitive digital-to-analog converters (CDACs) and its quantum state is measured by a single-electron detector. The SoC operates at a cryogenic temperature of 3.4 K. The occupied area of each QD array is 0.7×0.4 μm, while each QD occupies only 20×80 nm. The low power and miniaturized area of these circuits are an important step on the way for integration of a large quantum core with millions of QDs, required for practical quantum computers. The performance and functionality of the CDAC are validated in a loop-back mode with the detector sensing the CDAC-compelled electron tunneling from the quantum point contact (QPC) node into the quantum structure. Position of the injected charge inside the QD array is intended to be controlled through the CDAC codes and programmable pulse width. Quantum effects are shown by an experimental characterization of charge injection and quantization into the QD array consisting of three coupled QDs. The charge can be transferred to a QD and sensed at the QPC, and this process is controlled by the relevant voltages and CDACs.

SMART CABIN TEMPERATURE AND GAS CONTROLLING SYSTEM FOR CAR

Car owners especially in these days, are facing more problems due to the high temperatures when parking the car under burning sun due to the air temperature rise inside the car and production of harmful gases. In this paper, the design and development of a smart car air cooling system with the help of a temperature sensor and carbon monoxide sensor has described. The system was developed with microcontroller, Wi-Fi module, fan, sensors and other control circuitry to manage the system to operate manually and automatically. With the help of mobile application, the owner is able to receive the information regarding the level of temperature and the percentage of gas inside the car. The system is able to begin working when the temperature reaches 30°C and stop automatically when the temperature comes below 25°C. The temperature level inside and outside of the car was measured and the highest temperature inside the car cabin was observed to be 61°C. The principle of operation and theoretical analysis was provided. The experimental results were provided with the level of temperature and percentage of gas emissions inside the car under sunlight.

Propane Gas Thermoelectric Generator with Microcontroller Integrated Development Environment Hot Side Temperature Control

A thermoelectric generator consists of various thermocouples arranged in series. A voltage is generated when a temperature gradient exists across the junctions of the thermocouples. This research modelled, developed and tested a thermoelectric generator with hot side temperature control using propane gas, in a microcontroller integrated development environment to protect the modules from excessive high temperatures. The models were solved using MATLAB for pictorial representation of the performance of the generator with temperature gradient, hot and cold side temperatures. The thermoelectric generator was developed using ten SP-184827145-SA modules. The temperature control circuitry consists of an ATMEGA32 microcontroller, DS18B30 temperature sensors, stepper motor, computer interface and power supply unit whose sole aim is to regulate the gas supply and hence control the flame temperature. The maximum open circuit voltage gotten was 25 V at 300 secs with hot side temperature of 120°C and cold side temperature 30°C, with an efficiency of 3.6%. It was also found out that the higher the temperature gradient the higher the voltage produced.

Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models

Cryogenic CMOS is a crucial component in building scalable quantum computers, predominantly for interface and control circuitry. Further, high-performance computing can also benefit from cryogenic boosters. This necessitates an in-depth understanding of the power and performance trade-offs in the cryogenic operation of digital logic. In this article, we analyze digital standard cells in a 28 nm high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> metal gate (HKMG) CMOS foundry process design kit (PDK). We have developed Berkeley Short-channel IGFET Model (BSIM)4 of cryogenic CMOS and calibrated them with experimental measurements. Since low-temperature operation leads to an exponential decrease in the leakage current of the transistors, we further tune the threshold voltage of the devices to achieve iso-leakage. In this article, we present inverter static and dynamic characteristics and multiple ring oscillator (RO) structures. The simulation study shows that we can achieve 28% (FO4-RO) – 59% (NAND3-RO) higher performance under iso- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {DD}}$ </tex-math></inline-formula> scenario and up to 90% improvement in the energy-delay product (EDP) under iso-overdrive scenario at 6 K compared to room temperature.

A Reconfigurable Differential-to-Single-Ended Autonomous Current Adaptation Buffer Amplifier Suitable for Biomedical Applications.

A reconfigurable differential-to-single-ended autonomous current adaptation buffer amplifier (ACABA) is proposed. The ACABA, based on floating-gate technologies, is a capacitive circuit, of which output DC level and bandwidth can be adjusted by programming charges on floating nodes. The gain is variable by switching different amounts of capacitors without altering the output DC level. Without extra sensing and control circuitries, the current consumption of the proposed ACABA increases spontaneously when the input signal is fast or large, achieving a high slew rate. The supply current dwindles back to the low quiescent level autonomously when the output voltage reaches equilibrium. Therefore, the proposed ACABA is power-efficient and suitable for processing physiological signals. A prototype ACABA has been designed and fabricated in a [Formula: see text] CMOS process occupying an area of [Formula: see text]. When loaded by a [Formula: see text] capacitor, it consumes [Formula: see text] to achieve a unity-gain bandwidth of [Formula: see text] with a measured IIP2 value of [Formula: see text] and a slew rate of [Formula: see text].

Semiconductor Quantum Computing: Toward a CMOS quantum computer on chip

Quantum computing has the potential to create a paradigm shift in computing technology, which can lead to breakthroughs in emerging applications that rely on ultra-high-performance computing, e.g., artificial intelligence. Among several implementation approaches for quantum computers, semiconductor-based quantum computing, especially using CMOS technologies, is promising because it can be used to implement large arrays of qubits with their control and readout circuitry on a single chip.

A Low-Cost Cell-Level Differential Power Processing CMOS IC for Single Junction Photovoltaic Cells

This article presents a cell-level differential power processing IC to maximize the power yield under partial shading and mismatch condition in series-connected single junction photovoltaic (PV) cells. A 3-MHz bidirectional buck-boost converter is employed to realize voltage equalization technique forcing the PV cells to constantly operate close to their maximum power points. A novel and simple low-power low-area analog control circuit is proposed to maintain the high system efficiency at low and high levels of mismatch by obviating the need for power hungry blocks such as analog to digital converters, digital to analog converters, op-amps, saw-tooth generator, and regulators. The voltage of adjacent PV cells is used to drive the high-side switches through bootstrap supplies eliminating the need for voltage regulators. The performance of the proposed IC, fabricated in 130 nm CMOS process, is validated through simulation and experimental results. The converter is capable of processing mismatch currents up to 4 A while the control circuitry consumes less than 40 mW and a system efficiency above 95% is achieved.

A Holistic Solution for Reliability of 3D Parallel Systems

Monolithic 3D technology is emerging as a promising solution that can bring massive opportunities, but the gains can be hindered due to the reliability issues exaggerated by high temperature. Conventional reliability solutions focus on one specific feature and assume that the other required features would be provided by different solutions. Hence, this assumption has resulted in solutions that are proposed in isolation of each other and fail to consider the overall compatibility and the implied overheads of multiple isolated solutions for one system. This article proposes a holistic reliability management engine, R2D3, for post-Moore’s M3D parallel systems that have low yield and high failure rate. The proposed engine, comprising a controller, reconfigurable crossbars, and detection circuitry, provides concurrent single-replay detection and diagnosis, fault-mitigating repair, and aging-aware lifetime management at runtime. This holistic view enables us to create a solution that is highly effective while achieving a low overhead. Our solution achieves 96% coverage of defect; reduces V th degradation by 53%, leading to a 78% performance improvement on average over 8 years for an eight-core system; and ultimately yields a 2.16× longer mean-time-to-failure (MTTF) while incurring an overhead of 7.4% in area, 6.5% in power, and an 8.2% decrease in frequency.